SCI Reflective Memory
|
|
- Easter Freeman
- 6 years ago
- Views:
Transcription
1 Embedded SCI Solutios SCI Reflective Memory (Experimetal) Atle Vesterkjær Dolphi Itercoect Solutios AS Olaf Helsets vei 6, N-0621 Oslo, Norway Phoe: (47) Fax: (47) Mail: 1
2 Itroductio This presetatio aims to give you a idea of how SCI ca be used for embedded / realtime solutios. SCI Reflective Memory is a software Reflective Memory solutio. SCI Reflective Memory is a library that you ca use to build Reflective Memory applicatios from, without havig to cosider the low-level implemetatio of SCI. Dolphi Itercoect Solutios AS 2
3 SCI Reflective Memory Applicatio specific code built i Reflective Memory shell SISCI library SISCI Driver IRM Driver Reflective Memory Dolphi Itercoect Solutios AS 3
4 Cotets Itroductio to Reflective Memory Dolphis HW ad SW used i buildig SCI Reflective Memory SCI Reflective Memory techical descriptio, features ad beefits Dolphi Itercoect Solutios AS 4
5 SCI Reflective Memory Lab Test ad evaluatio of SCI Reflective Memory demo programs. The exercises are foud i your labmaual (oe sheet). Dolphi Itercoect Solutios AS 5
6 Reflective Memory Applicatio specific code built i Reflective Memory shell SISCI library SISCI Driver IRM Driver Reflective Memory Dolphi Itercoect Solutios AS 6
7 Reflective Memory Reflective Memory systems are a solutio to problems raised by message passig i multicomputer eviromets. Reflective Memory systems belog to the class of disributed shared memory systems (DSM) Dolphi Itercoect Solutios AS 7
8 Reflective Memory Private memory module Reflective Memory Private memory module Reflective Memory Private memory module Reflective Memory Each system processor icludes a dual-ported local physical memory. A part of memory is cofigured as logically shared. The Reflective Memory is composed of all these physically distributed, logically shared memory parts mapped ito a global (shared) address space: The Reflective Memory Space. Dolphi Itercoect Solutios AS 8
9 Reflective Memory Private memory module Reflective Memory Private memory module Reflective Memory Private memory module Reflective Memory The mai idea of Reflective Memory is that if a shared data item might be reused, a accurate copy of it should be kept i each processors local memory. Dolphi Itercoect Solutios AS 9
10 Reflective Memory Private memory module Private memory module Read operatios are performed o local memory Reflective Memory Private memory module Reflective Memory Reflective Memory Write operatios geerates automatic updates of all system copies by a broadcast trasactio Dolphi Itercoect Solutios AS 10
11 Advatages ad disadvatages of Reflective Memory systems compared to other DSM systems: Advatages: Computatio typically overlaps with commuicatio Memory access time is usually costat ad thus determiistic. Because of their iheret replicatio thay are good for fault tolerace Simpler, ad have bee commercially implemeted for decades. Read operatios are fast. Disadvatages: For applicatios characterized with loger sequeces of writes to the same segmets, RM systems may produce ueccessary traffic. The itercoectio medium usually represet a bottleeck due to may data trasfers. Processes that write to the same shared memory locatio must be explicitly sychroized. Dolphi Itercoect Solutios AS 11
12 Reflective Memory applicatios Aircraft, Ship ad Submarie Simulators Automated Testig Systems Idustrial Automatio High-Speed Data Acquisitio Dolphi Itercoect Solutios AS 12
13 Reflective Memory features Reflective Memory updates ca occur o ay type of itercoect. Reflective Memory systems ca use ay type of topology. Reflective Memory systems are ot limited by ay particular memory cosistecy model. The shared memory regios ca be mapped either dyamically or statically. Dolphi Itercoect Solutios AS 13
14 Typical Reflective Memory features u Automatic updates of remote shared memory copies u Data filterig: Maybe ot every temporarily stored variable have to be reflected? u Reflective Memory cosistecy: The shared regio ca oly be accessed by oe party at the time. u Oly shared writes are propagated through the system Dolphi Itercoect Solutios AS 14
15 Typical Reflective Memory features u oe-to-all broadcast commuicatio (hardware based) u computatio overlaps with commuicatio u Hardware support for heterogeeous computig could sigificatly improve system usability. u explicitly sychroizatio (hardware based): Hardware support for sychroizatio icrease performace. Dolphi Itercoect Solutios AS 15
16 Why SCI Reflective Memory? Reflective Memory is a DSM architecture, like SCI, oly orgaized i aother way. Reflected Memory could easily be implemeted i Dolphi s HW ad SW. SCI systems have good fault tolerace ad redudacy characteristics. Competitive performace ratio for Dolphi s SCI products (Will get back to this later). Dolphi Itercoect Solutios AS 16
17 SCI Reflective Memory Applicatio specific code built i Reflective Memory shell SISCI library SISCI Driver IRM Driver Reflective Memory SCI Reflective Memory is a software reflective memory solutio based o Dolphis Adapter cards ad software. SCI Reflective Memory is a SISCI programmig shell that programmers ca use to write applicatio specific code for their Reflective Memory applicatio. Dolphi Itercoect Solutios AS 17
18 PMC/PCI SCI-64 Adapter Card SCI Reflective Memory is a SISCI based SCI solutio ad ca be used with all dolphi products that supports SISCI. Adapter Cards u D307 - SBus u D310 - PCI32 u D314 - PMC32 u D320 - PCI64 u D323 - PMC64 u D330 - PCI 66 Switches u D505-4 way (SBus) u D512-4 way (PCI) u D way (PCI) u D525-8 way switch Dolphi Itercoect Solutios AS 18
19 Programmig Iterface: Applicatio (Performace tool) SISCI library SISCI Driver IRM Driver Applicatio (i.e C- style) SISCI API SISCI driver IRM driver Hardware abstractio layer (PAL) PCI-SCI adapter card Dolphi Itercoect Solutios AS 19
20 SISCI features Access to High Performace HW Highly Portable Cross Platform / Cross Operatig system iteroperable Simplified SCI Programmig Flexible Reliable Data trasfers Hostbridge / Adapter Optimizatio i libraries Dolphi Itercoect Solutios AS 20
21 SCI Reflective Memory Applicatio specific code built i Reflective Memory shell SISCI library SISCI Driver IRM Driver Reflective Memory Dolphi Itercoect Solutios AS 21
22 SCI Reflective Memory: Geeral SISCI API SISCI IRM Socket API TCP/UDP IP DLPI/ NDIS User Space Kerel Space GENIF The first demo of SCI Reflective Memory is implemeted for a two ode reflective memory cofiguratio. The implemetatio is doe i User Space. Reflective memory Hardware implemetatio Software implemetatio User Space Kerel Space Dolphi Itercoect Solutios AS 22
23 SCI Reflective Memory: Overview SCI Reflective Memory Library SCI Reflective Memory Features Reflective Memory Example programs Performace Dolphi Itercoect Solutios AS 23
24 SCI Reflective Memory Library: Overview Idea Structure u Memory Maagemet u Sychroizatio Applicatios Dolphi Itercoect Solutios AS 24
25 SCI Reflective Memory Library: Idea A library to build applicatios from i order to provide a flexible iterface to our cards. SISCI fuctios Relatio to other SISCI C- programs Sychroizatio Dolphi Itercoect Solutios AS 25
26 SCI Reflective Memory Library: Structure Memory maagemet u Applicatio specific code should be used for processig, ad the SISCI fuctios for memory access Sychroizatio u I order to guaratee that the local shared reflective memory copies are kept up to date oly oe ode is grated writeaccess at the time. u Read operatios ca occur at ay time. Dolphi Itercoect Solutios AS 26
27 SCI Reflective Memory Library: Memory Maagemet Segmets, duplex mappig. Memory read ad write operatios Dolphi Itercoect Solutios AS 27
28 SCI Reflective Memory Library: Segmets, duplex mappig Local segmet(node1) Remote segmet map (Node2) Remote segmet map (Node1) Local segmet (Node2) The ode preparig to trasfer data has to coect to a segmet o the ode receivig data. I order to get the two odes to write to each other, they both have to create (at least) oe local segmet, ad they both have to ope up a coectio to the remote segmet (which is created as local o the other ode) Dolphi Itercoect Solutios AS 28
29 SCI Reflective Memory Library: Segmets, duplex mappig Local segmet (Node1) Remote segmet map (Node1) Local segmet (Node2) Remote segmet map (Node2) For all RM copies to be uiform, there is a eed for a additioal mappig as show above. This mappig is carried out by by writig to both the localsegmet- ad remotesegmet mappig durig each write operatio. The operatios are the same o both odes. Dolphi Itercoect Solutios AS 29
30 SCI Reflective Memory Library: Segmets, duplex mappig Node1: local-map: Create, prepare, map (local), set available remote-map: Coect, map (remote) For each write operatio to local memory, a write operatio to the remote memory is automatically carried out by software. Node2: local-map: Create, prepare, map (local), set available remote-map: Coect, map (remote) For each write operatio to local memory, a write operatio to the remote memory is automatically carried out by software. Dolphi Itercoect Solutios AS 30
31 SCI Reflective Memory Library: Segmets, duplex mappig If data is writte to the Reflective Memory, it is first writte ito local memory, the trasferred to remote memory by ay of the SISCI data trasfer fuctios. The programmer is resposible for obeyig the strict orderig rule: All write operatios to the local memory shall be reflected to the remote memory immediately. Dolphi Itercoect Solutios AS 31
32 SCI Reflective Memory Library: Memory read ad write operatios Remote access by SISCI fuctios SCIMemCopy SCITrasferBlock SISCI DMA Egie *remoteptr = value; u Local access by *localptr=value; memcpy(localbuffer, dummybuffer, size); Dolphi Itercoect Solutios AS 32
33 SCI Reflective Memory Library: Data trasfer SRC Buffer Private Size Local Segmet Local RM Remote Segmet offset Remote RM A private memory buffer is copied ito the Reflective Memory Space All three steps are madatory Dolphi Itercoect Solutios AS 33
34 SCI Reflective Memory Library: Sychroizatio A cetral poit i a RM system is RM cosistecy. RM read operatios ca be performed o local memory, but it should ot be possible to have modified data aother place i the system. A method that esures cosistet RM copies whe odes are competig for the shared resources is eeded. Practically this meas that a local access should ot be possible whe a remote access is i progress, ad oly oe ode should have write access to the shared data at the time. Dolphi Itercoect Solutios AS 34
35 SCI Reflective Memory Library: Sychroizatio Reflective Memory cosistecy u Pollig - asychroous u Iterrupts timesliced Pollig is used for better flexibility Dolphi Itercoect Solutios AS 35
36 SCI Reflective Memory: How to build Reflective Memory applicatios Memory access is take care of by the reflective memory trasfer fuctios Sychroizatio is used to protect the shared data from corruptio Dolphi Itercoect Solutios AS 36
37 SCI Reflective Memory: Features The SCI Reflective Memory is for a two ode reflective memory cofiguratio. If more odes shall be supported a modified sychroizatio sheme has to be implemeted. Apart from that there is o other limits i makig a multiode SCI Reflective Memory Dolphi Itercoect Solutios AS 37
38 SCI Reflective Memory: Geeral features All odes share the RM space. All odes have a local copy of the etire RM space. The local copies o the subsequet odes are automatically updated. The sychroizatio logic esures that oly oe ode has write access to the RM at the time, keepig all RM copies cosistet. RM write operatios are multicasted to all odes i the system. Dolphi Itercoect Solutios AS 38
39 SCI Reflective Memory: Geeral features computatio overlaps with commuicatio: Usig DMA trasfers for update of remote RM copies eables computatio to overlap with commuicatio, whe specific flags are set. Oe-to-all multicast commuicatio is used for remote RM updates. Shared data regios are orgaized as segmets Dolphi Itercoect Solutios AS 39
40 SCI Reflective Memory: Geeral features Push-oly: Oly shared write operatios are propagated through the system. A write to the local RM is distributed (reflected) to the RM o all odes. RM read operatios are performed o the local RM copy. DMA-, block-, memcopy- ad shared memory trasfers are supportedby the SISCI API ad the SCI Reflective Memory. Whe buildig a applicatio the desired trasfer mechaism ca be selected. Dolphi Itercoect Solutios AS 40
41 SCI Reflective Memory: Supported OS I geeral this is just like for the rest of the SISCI package, but sice SCI Reflective Memory is uder developmet we have ot bee able to port to all operatig systems (OS) yet. Curretly supported OS are: u Widows (NT & 2000, x86) u Liux (2.2) u Solaris (2.6 / 7, SPARC) Next i lie of OS that are beig ported to: u Lyx u VxWorks (POWERPC) Dolphi Itercoect Solutios AS 41
42 SCI Reflective Memory example programs Geeral Reflective Memory Special Reflective Memory Multimap Reflective Memory Dolphi Itercoect Solutios AS 42
43 Geeral Reflective Memory Local Segmet Node 1 Local Segmet Node 2 Oly oe SISCI segmet is created o each ode The segmets are liked together i RM style. Dolphi Itercoect Solutios AS 43
44 Special Reflective Memory Local Segmet Node 1 - Write access ode 1 - Write access ode 2 Local Segmet Node 2 Bot odes have read access to the whole Reflective Memory Space segmet, but write access to differet halves of the Reflective Memroy Space. Not really a Reflective Memory solutio, but a example of how it ca be maipulated for specific applicatios Dolphi Itercoect Solutios AS 44
45 Multimap Reflective Memory Local Segmet 1 Node 1 Local Segmet 2 Node 1 Local Segmet 3 Node 1 Local Segmet N Node 1 Local Segmet 1 Node 2 Local Segmet 2 Node 2 Local Segmet 3 Node 2 Local Segmet N Node 2 Istead of puttig the whole RM space i oe segmet, the user of rm_multimap cotrols several segmets. Thus the oly time odes are competig for a resource is whe the same segmet is requested by more tha oe (both odes) at the same time. Dolphi Itercoect Solutios AS 45
46 How to ru the example programs I the start-up face of each program you will be asked to eter: u Adapter umber u Remote Nodeid u SegmetSize u (Number of segmets) u help Dolphi Itercoect Solutios AS 46
47 How to ru the example programs These are the available commads: rm-read: Read from Reflected Memory. rm-write: Write data to the Reflected Memory. Special RM write fuctios: rm-dma: DMA trasfers betwee two odes. rm-block: Block trasfers betwee two odes. rm-shmem: Shared memory trasfers betwee two odes. rm-memcopy: Trasfer data to a previously mapped remote area. Dolphi Itercoect Solutios AS 47
48 How to ru the example programs Special RM test fuctios: bech-dma: DMA trasfers betwee two odes. RM style. bech-block: Block trasfers betwee two odes.rm style. bech-shmem: Shared memory trasfers betwee two odes.rm style. bech-memcopy: Trasfer data to a previously mapped remote area. bech-full: Test of all RM write-trasfers betwee two odes. Special RM test fuctios where oly the remote copy is writte to: sigle-dma: DMA trasfers betwee two odes. sigle-block: Block trasfers betwee two odes. sigle-shmem: Shared memory trasfers betwee two odes. sigle-memcopy: Trasfer data to a previously mapped remote area. sigle-full: Test of all RM write-trasfers betwee two odes. Dolphi Itercoect Solutios AS 48
49 How to ru the example programs test-dma: DMA trasfers betwee two odes, o syc. test-block: Block trasfers betwee two odes, o syc. test-shmem: Shared memory trasfers betwee two odes, o syc. test-memcopy:trasfer data to a previously mapped remote area, o syc. test-full: Test of all NON-RM write-trasfers betwee two odes. file: Prit performace parameters to file performace: Prit performace parameters for this ode parameters: Prit key parameters for this ode loops: Number of write-commads i the test routies costart: Test with traffic from both odes startig cocurretly costop: Disable cocurret start sigal help: This helpscree q: quit Dolphi Itercoect Solutios AS 49
50 Performace The measuremets have bee made uder the operatig system (OS) Widows 2000, but performace is ot OS depedet. Dolphi Itercoect Solutios AS 50
51 SISCI Performace Highly depedet of the PC Chipsets Latecy 2.2 microsecods Throughput Applicatio to Applicatio usig SISCI u 85 MB/s (33Mhz/32 Bit PCI) u 120 MB/s (33 Mhz/64 Bit PCI) u 240 MB/s* (66 Mhz/64 Bit PCI) Dolphi Itercoect Solutios AS 51
52 Performace The characteristics of the test machies were: u DELL PowerEdge 6300 u Petium II Xeo u CPU clock 400 MHz u 256 MB RAM u 512 KB Level 2 Cache Memory u 440 NX PCI Chipset u Four system processors Dolphi Itercoect Solutios AS 52
53 Performace (oe-way) The throughput of remote write operatios The throughput of a loop cotaiig RM sychroizatio ad remote write operatios. The throughput of a loop cotaiig RM sychroizatio, local write operatios ad remote write operatios. RM-style Dolphi Itercoect Solutios AS 53
54 Performace (oe-way) RM SCIMemCopy trasfers without writig to the local segmet: Segmet size: Latecy: Throughput: us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us 7.49 MB/s us 4.38 MB/s Dolphi Itercoect Solutios AS 54
55 Performace RM SCIMemCopy trasfers: Segmet size: Latecy: Throughput: us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us 7.40 MB/s us 4.35 MB/s Dolphi Itercoect Solutios AS 55
56 Performace NON-RM SCIMemCopy trasfers: Segmet size: Latecy: Throughput: us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s Dolphi Itercoect Solutios AS 56
57 Performace (Trasfer i both directios simultaously) The throughput of remote write operatios The throughput of a loop cotaiig RM sychroizatio ad remote write operatios. The throughput of a loop cotaiig RM sychroizatio, local write operatios ad remote write operatios. RM-style Dolphi Itercoect Solutios AS 57
58 Performace RM SCIMemCopy trasfers without writig to the local segmet: Segmet size: Latecy: Throughput: us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us 8.69 MB/s Dolphi Itercoect Solutios AS 58
59 Performace RM SCIMemCopy trasfers: Segmet size: Latecy: Throughput: us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us 8.63 MB/s Dolphi Itercoect Solutios AS 59
60 Performace NON-RM SCIMemCopy trasfers: Segmet size: Latecy: Throughput: us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s us MB/s Dolphi Itercoect Solutios AS 60
61 Future Plas We are workig i fidig parters that are iterested i joiig us i developig a applicatio based o SCI Reflective Memory for them. PSB66 release Dig deeper ito kerel space ad/or hardware to optimize performace ad ease of use Dolphi Itercoect Solutios AS 61
62 Key statemet The idusty leadig throughput, ad latecy of Dolphis itercoect solutios will soo be available for the Reflective Memory market. Dolphi Itercoect Solutios AS 62
63 Importat terms We hope that you ow will uderstad the meaig of the terms: u Reflective Memory u PMC/PCI Adapter Cards u SISCI u SCI Reflective Memory trasfer fuctios u SCI Reflective Memory sychroizatio u SCI Reflective Memory duplex mappig of segmets Dolphi Itercoect Solutios AS 63
64 Questios? Dolphi Itercoect Solutios AS 64
65 Thak you for listeig to this presetatio! See you i the Lab i half a hour! SCI Reflective Memory Atle Vesterkjær Dolphi Itercoect Solutios AS Olaf Helsets vei 6, N-0621 Oslo, Norway Phoe: (47) Fax: (47) Mail: atleve@dolphiics.o Dolphi Itercoect Solutios AS 65
Chapter 4 Threads. Operating Systems: Internals and Design Principles. Ninth Edition By William Stallings
Operatig Systems: Iterals ad Desig Priciples Chapter 4 Threads Nith Editio By William Stalligs Processes ad Threads Resource Owership Process icludes a virtual address space to hold the process image The
More informationCMSC Computer Architecture Lecture 12: Virtual Memory. Prof. Yanjing Li University of Chicago
CMSC 22200 Computer Architecture Lecture 12: Virtual Memory Prof. Yajig Li Uiversity of Chicago A System with Physical Memory Oly Examples: most Cray machies early PCs Memory early all embedded systems
More informationMulti-Threading. Hyper-, Multi-, and Simultaneous Thread Execution
Multi-Threadig Hyper-, Multi-, ad Simultaeous Thread Executio 1 Performace To Date Icreasig processor performace Pipeliig. Brach predictio. Super-scalar executio. Out-of-order executio. Caches. Hyper-Threadig
More informationCopyright 2016 Ramez Elmasri and Shamkant B. Navathe
Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe CHAPTER 20 Itroductio to Trasactio Processig Cocepts ad Theory Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe Itroductio Trasactio Describes local
More informationn Explore virtualization concepts n Become familiar with cloud concepts
Chapter Objectives Explore virtualizatio cocepts Become familiar with cloud cocepts Chapter #15: Architecture ad Desig 2 Hypervisor Virtualizatio ad cloud services are becomig commo eterprise tools to
More informationCOMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Part A Datapath Design
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter The Processor Part A path Desig Itroductio CPU performace factors Istructio cout Determied by ISA ad compiler. CPI ad
More informationOutline. CSCI 4730 Operating Systems. Questions. What is an Operating System? Computer System Layers. Computer System Layers
Outlie CSCI 4730 s! What is a s?!! System Compoet Architecture s Overview Questios What is a?! What are the major operatig system compoets?! What are basic computer system orgaizatios?! How do you commuicate
More informationCopyright 2016 Ramez Elmasri and Shamkant B. Navathe
Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe CHAPTER 18 Strategies for Query Processig Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe Itroductio DBMS techiques to process a query Scaer idetifies
More informationCSC 220: Computer Organization Unit 11 Basic Computer Organization and Design
College of Computer ad Iformatio Scieces Departmet of Computer Sciece CSC 220: Computer Orgaizatio Uit 11 Basic Computer Orgaizatio ad Desig 1 For the rest of the semester, we ll focus o computer architecture:
More informationGE FUNDAMENTALS OF COMPUTING AND PROGRAMMING UNIT III
GE2112 - FUNDAMENTALS OF COMPUTING AND PROGRAMMING UNIT III PROBLEM SOLVING AND OFFICE APPLICATION SOFTWARE Plaig the Computer Program Purpose Algorithm Flow Charts Pseudocode -Applicatio Software Packages-
More informationPython Programming: An Introduction to Computer Science
Pytho Programmig: A Itroductio to Computer Sciece Chapter 1 Computers ad Programs 1 Objectives To uderstad the respective roles of hardware ad software i a computig system. To lear what computer scietists
More informationAvid Interplay Bundle
Avid Iterplay Budle Versio 2.5 Cofigurator ReadMe Overview This documet provides a overview of Iterplay Budle v2.5 ad describes how to ru the Iterplay Budle cofiguratio tool. Iterplay Budle v2.5 refers
More informationCourse Site: Copyright 2012, Elsevier Inc. All rights reserved.
Course Site: http://cc.sjtu.edu.c/g2s/site/aca.html 1 Computer Architecture A Quatitative Approach, Fifth Editio Chapter 2 Memory Hierarchy Desig 2 Outlie Memory Hierarchy Cache Desig Basic Cache Optimizatios
More informationElementary Educational Computer
Chapter 5 Elemetary Educatioal Computer. Geeral structure of the Elemetary Educatioal Computer (EEC) The EEC coforms to the 5 uits structure defied by vo Neuma's model (.) All uits are preseted i a simplified
More informationMultiprocessors. HPC Prof. Robert van Engelen
Multiprocessors Prof. Robert va Egele Overview The PMS model Shared memory multiprocessors Basic shared memory systems SMP, Multicore, ad COMA Distributed memory multicomputers MPP systems Network topologies
More information1. SWITCHING FUNDAMENTALS
. SWITCING FUNDMENTLS Switchig is the provisio of a o-demad coectio betwee two ed poits. Two distict switchig techiques are employed i commuicatio etwors-- circuit switchig ad pacet switchig. Circuit switchig
More informationMorgan Kaufmann Publishers 26 February, COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 5.
Morga Kaufma Publishers 26 February, 208 COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter 5 Virtual Memory Review: The Memory Hierarchy Take advatage of the priciple
More informationCopyright 2016 Ramez Elmasri and Shamkant B. Navathe
Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe CHAPTER 22 Database Recovery Techiques Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe Itroductio Recovery algorithms Recovery cocepts Write-ahead
More informationn Learn how resiliency strategies reduce risk n Discover automation strategies to reduce risk
Chapter Objectives Lear how resiliecy strategies reduce risk Discover automatio strategies to reduce risk Chapter #16: Architecture ad Desig Resiliecy ad Automatio Strategies 2 Automatio/Scriptig Resiliet
More information1 Enterprise Modeler
1 Eterprise Modeler Itroductio I BaaERP, a Busiess Cotrol Model ad a Eterprise Structure Model for multi-site cofiguratios are itroduced. Eterprise Structure Model Busiess Cotrol Models Busiess Fuctio
More informationFAST BIT-REVERSALS ON UNIPROCESSORS AND SHARED-MEMORY MULTIPROCESSORS
SIAM J. SCI. COMPUT. Vol. 22, No. 6, pp. 2113 2134 c 21 Society for Idustrial ad Applied Mathematics FAST BIT-REVERSALS ON UNIPROCESSORS AND SHARED-MEMORY MULTIPROCESSORS ZHAO ZHANG AND XIAODONG ZHANG
More informationData Warehousing. Paper
Data Warehousig Paper 28-25 Implemetig a fiacial balace scorecard o top of SAP R/3, usig CFO Visio as iterface. Ida Carapelle & Sophie De Baets, SOLID Parters, Brussels, Belgium (EUROPE) ABSTRACT Fiacial
More informationArchitectural styles for software systems The client-server style
Architectural styles for software systems The cliet-server style Prof. Paolo Ciacarii Software Architecture CdL M Iformatica Uiversità di Bologa Ageda Cliet server style CS two tiers CS three tiers CS
More informationCopyright 2016 Ramez Elmasri and Shamkant B. Navathe
Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe CHAPTER 19 Query Optimizatio Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe Itroductio Query optimizatio Coducted by a query optimizer i a DBMS Goal:
More informationEnd Semester Examination CSE, III Yr. (I Sem), 30002: Computer Organization
Ed Semester Examiatio 2013-14 CSE, III Yr. (I Sem), 30002: Computer Orgaizatio Istructios: GROUP -A 1. Write the questio paper group (A, B, C, D), o frot page top of aswer book, as per what is metioed
More informationChapter 1. Introduction to Computers and C++ Programming. Copyright 2015 Pearson Education, Ltd.. All rights reserved.
Chapter 1 Itroductio to Computers ad C++ Programmig Copyright 2015 Pearso Educatio, Ltd.. All rights reserved. Overview 1.1 Computer Systems 1.2 Programmig ad Problem Solvig 1.3 Itroductio to C++ 1.4 Testig
More informationService Oriented Enterprise Architecture and Service Oriented Enterprise
Approved for Public Release Distributio Ulimited Case Number: 09-2786 The 23 rd Ope Group Eterprise Practitioers Coferece Service Orieted Eterprise ad Service Orieted Eterprise Ya Zhao, PhD Pricipal, MITRE
More information1&1 Next Level Hosting
1&1 Next Level Hostig Performace Level: Performace that grows with your requiremets Copyright 1&1 Iteret SE 2017 1ad1.com 2 1&1 NEXT LEVEL HOSTING 3 Fast page loadig ad short respose times play importat
More informationMaster Informatics Eng. 2017/18. A.J.Proença. Memory Hierarchy. (most slides are borrowed) AJProença, Advanced Architectures, MiEI, UMinho, 2017/18 1
Advaced Architectures Master Iformatics Eg. 2017/18 A.J.Proeça Memory Hierarchy (most slides are borrowed) AJProeça, Advaced Architectures, MiEI, UMiho, 2017/18 1 Itroductio Programmers wat ulimited amouts
More informationCMSC Computer Architecture Lecture 11: More Caches. Prof. Yanjing Li University of Chicago
CMSC 22200 Computer Architecture Lecture 11: More Caches Prof. Yajig Li Uiversity of Chicago Lecture Outlie Caches 2 Review Memory hierarchy Cache basics Locality priciples Spatial ad temporal How to access
More informationReview: The ACID properties
Recovery Review: The ACID properties A tomicity: All actios i the Xactio happe, or oe happe. C osistecy: If each Xactio is cosistet, ad the DB starts cosistet, it eds up cosistet. I solatio: Executio of
More informationPython Programming: An Introduction to Computer Science
Pytho Programmig: A Itroductio to Computer Sciece Chapter 6 Defiig Fuctios Pytho Programmig, 2/e 1 Objectives To uderstad why programmers divide programs up ito sets of cooperatig fuctios. To be able to
More informationCOMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Single-Cycle Disadvantages & Advantages
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter 4 The Processor Pipeliig Sigle-Cycle Disadvatages & Advatages Clk Uses the clock cycle iefficietly the clock cycle must
More information. Written in factored form it is easy to see that the roots are 2, 2, i,
CMPS A Itroductio to Programmig Programmig Assigmet 4 I this assigmet you will write a java program that determies the real roots of a polyomial that lie withi a specified rage. Recall that the roots (or
More informationLecture 28: Data Link Layer
Automatic Repeat Request (ARQ) 2. Go ack N ARQ Although the Stop ad Wait ARQ is very simple, you ca easily show that it has very the low efficiecy. The low efficiecy comes from the fact that the trasmittig
More informationThe University of Adelaide, School of Computer Science 22 November Computer Architecture. A Quantitative Approach, Sixth Edition.
Computer Architecture A Quatitative Approach, Sixth Editio Chapter 2 Memory Hierarchy Desig 1 Itroductio Programmers wat ulimited amouts of memory with low latecy Fast memory techology is more expesive
More informationIntroduction to Computing Systems: From Bits and Gates to C and Beyond 2 nd Edition
Lecture Goals Itroductio to Computig Systems: From Bits ad Gates to C ad Beyod 2 d Editio Yale N. Patt Sajay J. Patel Origial slides from Gregory Byrd, North Carolia State Uiversity Modified slides by
More informationArquitectura de Computadores
Arquitectura de Computadores Capítulo 5. Almaceamieto y otros aspectos de la E/S Based o the origial material of the book: D.A. Patterso y J.L. Heessy Computer Orgaizatio ad Desig: The Hardware/Software
More informationAppendix D. Controller Implementation
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Appedix D Cotroller Implemetatio Cotroller Implemetatios Combiatioal logic (sigle-cycle); Fiite state machie (multi-cycle, pipelied);
More informationOutline n Introduction n Background o Distributed DBMS Architecture
Outlie Itroductio Backgroud o Distributed DBMS Architecture Datalogical Architecture Implemetatio Alteratives Compoet Architecture o Distributed DBMS Architecture o Distributed Desig o Sematic Data Cotrol
More informationSoftware development of components for complex signal analysis on the example of adaptive recursive estimation methods.
Software developmet of compoets for complex sigal aalysis o the example of adaptive recursive estimatio methods. SIMON BOYMANN, RALPH MASCHOTTA, SILKE LEHMANN, DUNJA STEUER Istitute of Biomedical Egieerig
More informationSession Initiated Protocol (SIP) and Message-based Load Balancing (MBLB)
F5 White Paper Sessio Iitiated Protocol (SIP) ad Message-based Load Balacig (MBLB) The ability to provide ew ad creative methods of commuicatios has esured a SIP presece i almost every orgaizatio. The
More informationCIS 121 Data Structures and Algorithms with Java Spring Stacks and Queues Monday, February 12 / Tuesday, February 13
CIS Data Structures ad Algorithms with Java Sprig 08 Stacks ad Queues Moday, February / Tuesday, February Learig Goals Durig this lab, you will: Review stacks ad queues. Lear amortized ruig time aalysis
More informationPanel for Adobe Premiere Pro CC Partner Solution
Pael for Adobe Premiere Pro CC Itegratio for more efficiecy The makes video editig simple, fast ad coveiet. The itegrated pael gives users immediate access to all medialoopster features iside Adobe Premiere
More informationCode Review Defects. Authors: Mika V. Mäntylä and Casper Lassenius Original version: 4 Sep, 2007 Made available online: 24 April, 2013
Code Review s Authors: Mika V. Mätylä ad Casper Lasseius Origial versio: 4 Sep, 2007 Made available olie: 24 April, 2013 This documet cotais further details of the code review defects preseted i [1]. of
More informationOne advantage that SONAR has over any other music-sequencing product I ve worked
*gajedra* D:/Thomso_Learig_Projects/Garrigus_163132/z_productio/z_3B2_3D_files/Garrigus_163132_ch17.3d, 14/11/08/16:26:39, 16:26, page: 647 17 CAL 101 Oe advatage that SONAR has over ay other music-sequecig
More informationK-NET bus. When several turrets are connected to the K-Bus, the structure of the system is as showns
K-NET bus The K-Net bus is based o the SPI bus but it allows to addressig may differet turrets like the I 2 C bus. The K-Net is 6 a wires bus (4 for SPI wires ad 2 additioal wires for request ad ackowledge
More informationCMSC Computer Architecture Lecture 15: Multi-Core. Prof. Yanjing Li University of Chicago
CMSC 22200 Computer Architecture Lecture 15: Multi-Core Prof. Yajig Li Uiversity of Chicago Course Evaluatio Very importat Please fill out! 2 Lab3 Brach Predictio Competitio 8 teams etered the competitio,
More informationIntroduction to SWARM Software and Algorithms for Running on Multicore Processors
Itroductio to SWARM Software ad Algorithms for Ruig o Multicore Processors David A. Bader Georgia Istitute of Techology http://www.cc.gatech.edu/~bader Tutorial compiled by Rucheek H. Sagai M.S. Studet,
More informationLecture Notes 6 Introduction to algorithm analysis CSS 501 Data Structures and Object-Oriented Programming
Lecture Notes 6 Itroductio to algorithm aalysis CSS 501 Data Structures ad Object-Orieted Programmig Readig for this lecture: Carrao, Chapter 10 To be covered i this lecture: Itroductio to algorithm aalysis
More informationCORD Test Project in Okinawa Open Laboratory
CORD Test Project i Okiawa Ope Laboratory Fukumasa Morifuji NTT Commuicatios Trasform your busiess, trasced expectatios with our techologically advaced solutios. Ageda VxF platform i NTT Commuicatios Expectatio
More informationData diverse software fault tolerance techniques
Data diverse software fault tolerace techiques Complemets desig diversity by compesatig for desig diversity s s limitatios Ivolves obtaiig a related set of poits i the program data space, executig the
More informationIsn t It Time You Got Faster, Quicker?
Is t It Time You Got Faster, Quicker? AltiVec Techology At-a-Glace OVERVIEW Motorola s advaced AltiVec techology is desiged to eable host processors compatible with the PowerPC istructio-set architecture
More informationSecurity and Communication. Ultimate. Because Intercom doesn t stop at the hardware level. Software Intercom Server for virtualised IT platforms
Because Itercom does t stop at the hardware level by Commed Software Itercom Server for virtualised IT platforms Ready for VMware Ready for Hyper-V VoIP Ultimate availability Itercom Server as a app The
More informationWeb OS Switch Software
Web OS Switch Software BBI Quick Guide Nortel Networks Part Number: 213164, Revisio A, July 2000 50 Great Oaks Boulevard Sa Jose, Califoria 95119 408-360-5500 Mai 408-360-5501 Fax www.orteletworks.com
More informationOPC Server ECL Comfort 210/310 OPC Server
OPC Server Descriptio j l j o j l k j l j Modbus-RS485 k Etheret or Iteret l Modbus-TCP ECL Cofort cotroller Heat eter o SCADA server The Dafoss is a OPC-copliat server that serves data to OPC cliets.
More informationJavaFX. JavaFX 2.2 Installation Guide Release 2.2 E August 2012 Installation instructions by operating system for JavaFX 2.
JavaFX JavaFX 2.2 Istallatio Guide Release 2.2 E20474-06 August 2012 Istallatio istructios by operatig system for JavaFX 2.2 JavaFX/JavaFX 2.2 Istallatio Guide E20474-06 Copyright 2008, 2012, Oracle ad/or
More informationThe Magma Database file formats
The Magma Database file formats Adrew Gaylard, Bret Pikey, ad Mart-Mari Breedt Johaesburg, South Africa 15th May 2006 1 Summary Magma is a ope-source object database created by Chris Muller, of Kasas City,
More informationStructuring Redundancy for Fault Tolerance. CSE 598D: Fault Tolerant Software
Structurig Redudacy for Fault Tolerace CSE 598D: Fault Tolerat Software What do we wat to achieve? Versios Damage Assessmet Versio 1 Error Detectio Iputs Versio 2 Voter Outputs State Restoratio Cotiued
More informationOperating System Concepts. Operating System Concepts
Chapter 4: Mass-Storage Systems Logical Disk Structure Logical Disk Structure Disk Schedulig Disk Maagemet RAID Structure Disk drives are addressed as large -dimesioal arrays of logical blocks, where the
More informationCAEN Tools for Discovery
Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Viareggio 9 May 2013 Itroductio High speed digitizers fid applicatios i several fields ragig from the idustry
More informationThreads and Concurrency in Java: Part 1
Cocurrecy Threads ad Cocurrecy i Java: Part 1 What every computer egieer eeds to kow about cocurrecy: Cocurrecy is to utraied programmers as matches are to small childre. It is all too easy to get bured.
More informationCS2410 Computer Architecture. Flynn s Taxonomy
CS2410 Computer Architecture Dept. of Computer Sciece Uiversity of Pittsburgh http://www.cs.pitt.edu/~melhem/courses/2410p/idex.html 1 Fly s Taxoomy SISD Sigle istructio stream Sigle data stream (SIMD)
More informationBaan Tools User Management
Baa Tools User Maagemet Module Procedure UP008A US Documetiformatio Documet Documet code : UP008A US Documet group : User Documetatio Documet title : User Maagemet Applicatio/Package : Baa Tools Editio
More informationThreads and Concurrency in Java: Part 1
Threads ad Cocurrecy i Java: Part 1 1 Cocurrecy What every computer egieer eeds to kow about cocurrecy: Cocurrecy is to utraied programmers as matches are to small childre. It is all too easy to get bured.
More informationU8 Flash Memory Controller
U8 Flash Memory Cotroller U8 U8 Flash Memory Cotroller The Hyperstoe U8 family of Flash Memory Cotrollers together with provided applicatio ad Flash specific firmware offers a easy-to-use turkey platform
More informationCS 111 Green: Program Design I Lecture 27: Speed (cont.); parting thoughts
CS 111 Gree: Program Desig I Lecture 27: Speed (cot.); partig thoughts By Nascarkig - Ow work, CC BY-SA 4.0, https://commos.wikimedia.org/w/idex.php?curid=38671041 Robert H. Sloa (CS) & Rachel Poretsky
More informationGPUMP: a Multiple-Precision Integer Library for GPUs
GPUMP: a Multiple-Precisio Iteger Library for GPUs Kaiyog Zhao ad Xiaowe Chu Departmet of Computer Sciece, Hog Kog Baptist Uiversity Hog Kog, P. R. Chia Email: {kyzhao, chxw}@comp.hkbu.edu.hk Abstract
More informationCOSC 1P03. Ch 7 Recursion. Introduction to Data Structures 8.1
COSC 1P03 Ch 7 Recursio Itroductio to Data Structures 8.1 COSC 1P03 Recursio Recursio I Mathematics factorial Fiboacci umbers defie ifiite set with fiite defiitio I Computer Sciece sytax rules fiite defiitio,
More informationSpeeding-up dynamic programming in sequence alignment
Departmet of Computer Sciece Aarhus Uiversity Demark Speedig-up dyamic programmig i sequece aligmet Master s Thesis Dug My Hoa - 443 December, Supervisor: Christia Nørgaard Storm Pederse Implemetatio code
More informationEvaluation scheme for Tracking in AMI
A M I C o m m u i c a t i o A U G M E N T E D M U L T I - P A R T Y I N T E R A C T I O N http://www.amiproject.org/ Evaluatio scheme for Trackig i AMI S. Schreiber a D. Gatica-Perez b AMI WP4 Trackig:
More informationLoad balanced Parallel Prime Number Generator with Sieve of Eratosthenes on Cluster Computers *
Load balaced Parallel Prime umber Geerator with Sieve of Eratosthees o luster omputers * Soowook Hwag*, Kyusik hug**, ad Dogseug Kim* *Departmet of Electrical Egieerig Korea Uiversity Seoul, -, Rep. of
More informationDefinitions. Error. A wrong decision made during software development
Debuggig Defiitios Error A wrog decisio made durig software developmet Defiitios 2 Error A wrog decisio made durig software developmet Defect bug sometimes meas this The term Fault is also used Property
More informationWhat are we going to learn? CSC Data Structures Analysis of Algorithms. Overview. Algorithm, and Inputs
What are we goig to lear? CSC316-003 Data Structures Aalysis of Algorithms Computer Sciece North Carolia State Uiversity Need to say that some algorithms are better tha others Criteria for evaluatio Structure
More informationConsider the following population data for the state of California. Year Population
Assigmets for Bradie Fall 2016 for Chapter 5 Assigmet sheet for Sectios 5.1, 5.3, 5.5, 5.6, 5.7, 5.8 Read Pages 341-349 Exercises for Sectio 5.1 Lagrage Iterpolatio #1, #4, #7, #13, #14 For #1 use MATLAB
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 13 Control and Sequencing: Hardwired and Microprogrammed Control
EE 459/500 HDL Based Digital Desig with Programmable Logic Lecture 13 Cotrol ad Sequecig: Hardwired ad Microprogrammed Cotrol Refereces: Chapter s 4,5 from textbook Chapter 7 of M.M. Mao ad C.R. Kime,
More informationExtending The Sleuth Kit and its Underlying Model for Pooled Storage File System Forensic Analysis
Extedig The Sleuth Kit ad its Uderlyig Model for Pooled File System Foresic Aalysis Frauhofer Istitute for Commuicatio, Iformatio Processig ad Ergoomics Ja-Niclas Hilgert* Marti Lambertz Daiel Plohma ja-iclas.hilgert@fkie.frauhofer.de
More informationCIS 121 Data Structures and Algorithms with Java Spring Stacks, Queues, and Heaps Monday, February 18 / Tuesday, February 19
CIS Data Structures ad Algorithms with Java Sprig 09 Stacks, Queues, ad Heaps Moday, February 8 / Tuesday, February 9 Stacks ad Queues Recall the stack ad queue ADTs (abstract data types from lecture.
More informationCopyright 2016 Ramez Elmasri and Shamkant B. Navathe
Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe CHAPTER 26 Ehaced Data Models: Itroductio to Active, Temporal, Spatial, Multimedia, ad Deductive Databases Copyright 2016 Ramez Elmasri ad Shamkat B.
More informationAdaptive Graph Partitioning Wireless Protocol S. L. Ng 1, P. M. Geethakumari 1, S. Zhou 2, and W. J. Dewar 1 1
Adaptive Graph Partitioig Wireless Protocol S. L. Ng 1, P. M. Geethakumari 1, S. Zhou 2, ad W. J. Dewar 1 1 School of Electrical Egieerig Uiversity of New South Wales, Australia 2 Divisio of Radiophysics
More informationICS Regent. Communications Modules. Module Operation. RS-232, RS-422 and RS-485 (T3150A) PD-6002
ICS Reget Commuicatios Modules RS-232, RS-422 ad RS-485 (T3150A) Issue 1, March, 06 Commuicatios modules provide a serial commuicatios iterface betwee the cotroller ad exteral equipmet. Commuicatios modules
More informationCMSC22200 Computer Architecture Lecture 9: Out-of-Order, SIMD, VLIW. Prof. Yanjing Li University of Chicago
CMSC22200 Computer Architecture Lecture 9: Out-of-Order, SIMD, VLIW Prof. Yajig Li Uiversity of Chicago Admiistrative Stuff Lab2 due toight Exam I: covers lectures 1-9 Ope book, ope otes, close device
More informationA collection of open-sourced RISC-V processors
Riscy Processors A collectio of ope-sourced RISC-V processors Ady Wright, Sizhuo Zhag, Thomas Bourgeat, Murali Vijayaraghava, Jamey Hicks, Arvid Computatio Structures Group, CSAIL, MIT 4 th RISC-V Workshop
More informationBig-O Analysis. Asymptotics
Big-O Aalysis 1 Defiitio: Suppose that f() ad g() are oegative fuctios of. The we say that f() is O(g()) provided that there are costats C > 0 ad N > 0 such that for all > N, f() Cg(). Big-O expresses
More informationUNIVERSITY OF MORATUWA
UNIVERSITY OF MORATUWA FACULTY OF ENGINEERING DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING B.Sc. Egieerig 2010 Itake Semester 7 Examiatio CS4532 CONCURRENT PROGRAMMING Time allowed: 2 Hours September 2014
More informationComputer Architecture. Microcomputer Architecture and Interfacing Colorado School of Mines Professor William Hoff
Computer rchitecture Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff Computer Hardware Orgaizatio Processor Performs all computatios; coordiates data trasfer Iput
More informationPosition and Velocity Estimation by Ultrasonic Sensor
Positio ad Velocity Estimatio by Ultrasoic Sesor N Ramarao 1, A R Subramayam 2, J Chara Raj 2, Lalith B V 2, Varu K R 2 1 (Faculty of EEE, BMSIT & M, INDIA) 2 (Studets of EEE, BMSIT & M, INDIA) Abstract:
More informationExact Minimum Lower Bound Algorithm for Traveling Salesman Problem
Exact Miimum Lower Boud Algorithm for Travelig Salesma Problem Mohamed Eleiche GeoTiba Systems mohamed.eleiche@gmail.com Abstract The miimum-travel-cost algorithm is a dyamic programmig algorithm to compute
More informationCache-Optimal Methods for Bit-Reversals
Proceedigs of the ACM/IEEE Supercomputig Coferece, November 1999, Portlad, Orego, U.S.A. Cache-Optimal Methods for Bit-Reversals Zhao Zhag ad Xiaodog Zhag Departmet of Computer Sciece College of William
More informationFundamentals of. Chapter 1. Microprocessor and Microcontroller. Dr. Farid Farahmand. Updated: Tuesday, January 16, 2018
Fudametals of Chapter 1 Microprocessor ad Microcotroller Dr. Farid Farahmad Updated: Tuesday, Jauary 16, 2018 Evolutio First came trasistors Itegrated circuits SSI (Small-Scale Itegratio) to ULSI Very
More informationEvaluation of Distributed and Replicated HLR for Location Management in PCS Network
JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 9, 85-0 (2003) Evaluatio of Distributed ad Replicated HLR for Locatio Maagemet i PCS Network Departmet of Computer Sciece ad Iformatio Egieerig Natioal Chiao
More informationPerformance Plus Software Parameter Definitions
Performace Plus+ Software Parameter Defiitios/ Performace Plus Software Parameter Defiitios Chapma Techical Note-TG-5 paramete.doc ev-0-03 Performace Plus+ Software Parameter Defiitios/2 Backgroud ad Defiitios
More informationAPPLICATION NOTE PACE1750AE BUILT-IN FUNCTIONS
APPLICATION NOTE PACE175AE BUILT-IN UNCTIONS About This Note This applicatio brief is iteded to explai ad demostrate the use of the special fuctios that are built ito the PACE175AE processor. These powerful
More informationChapter 3 DB-Gateways
Prof. Dr.-Ig. Stefa Deßloch AG Heterogee Iformatiossysteme Geb. 36, Raum 329 Tel. 0631/205 3275 dessloch@iformatik.ui-kl.de Chapter 3 DB-Gateways Outlie Couplig DBMS ad programmig laguages approaches requiremets
More informationCA InterTest for CICS r8.5
PRODUCT SHEET: CA INTERTEST FOR CICS CA IterTest for CICS r8.5 CA IterTest for CICS provides testig ad debuggig of IBM CICS Trasactio Server for z/os applicatios writte i COBOL, PL/I, Assembler ad Laguage
More informationCreating Test Harnesses and Starter Applications
03 6000 ch02 11/18/03 8:54 AM Page 27 Creatig Test Haresses ad Starter Applicatios Applicatio Types You Ca Create with Visual C++ Visual C++.NET comes with a package of wizards that geerate startig code
More informationReliable Transmission. Spring 2018 CS 438 Staff - University of Illinois 1
Reliable Trasmissio Sprig 2018 CS 438 Staff - Uiversity of Illiois 1 Reliable Trasmissio Hello! My computer s ame is Alice. Alice Bob Hello! Alice. Sprig 2018 CS 438 Staff - Uiversity of Illiois 2 Reliable
More informationCluster Computing Spring 2004 Paul A. Farrell
Cluster Computig Sprig 004 3/18/004 Parallel Programmig Overview Task Parallelism OS support for task parallelism Parameter Studies Domai Decompositio Sequece Matchig Work Assigmet Static schedulig Divide
More informationExamples and Applications of Binary Search
Toy Gog ITEE Uiersity of Queeslad I the secod lecture last week we studied the biary search algorithm that soles the problem of determiig if a particular alue appears i a sorted list of iteger or ot. We
More informationPseudocode ( 1.1) Analysis of Algorithms. Primitive Operations. Pseudocode Details. Running Time ( 1.1) Estimating performance
Aalysis of Algorithms Iput Algorithm Output A algorithm is a step-by-step procedure for solvig a problem i a fiite amout of time. Pseudocode ( 1.1) High-level descriptio of a algorithm More structured
More information