CS2410 Computer Architecture. Flynn s Taxonomy

Transcription

1 CS2410 Computer Architecture Dept. of Computer Sciece Uiversity of Pittsburgh 1 Fly s Taxoomy SISD Sigle istructio stream Sigle data stream (SIMD) Sigle istructio stream Multiple data stream MISD Multiple istructio stream Sigle data stream (MIMD) Multiple istructio stream Multiple data stream 2

2 What is Computer Architecture? ( 1.3) Applicatio pull Operatig systems Compiler Applicatios, e.g., games Software layers architect Techology push Istructio Set Architecture Processor Orgaizatio VLSI Implemetatio Semicoductor techologies Architecture Microarchitecture Physical hardware Models to overcome Istructio Level Parallelism (ILP) limitatios: Data-level parallelism (DLP) Thread-level parallelism (TLP) Request-level parallelism (RLP) 3 Treds i Techology( 1.4) Itegrated circuit techology Trasistor desity: +35%/year (feature size decreases) Die size: %/year Itegratio overall: %/year DRAM capacity: %/year (growth is slowig) (memory usage doubles every year) Flash capacity: %/year 15-20X cheaper/bit tha DRAM Magetic disk techology: +40%/year 15-25X cheaper/bit the Flash ad X cheaper/bit tha DRAM Clock rate stopped icreasig but supply voltage is decreasig 4

3 Badwidth ad Latecy Latecy lags badwidth i the last 30 years Badwidth or throughput Total work doe i a give time 10,000-25,000X improvemet for processors X improvemet for memory ad disks Latecy or respose time Time betwee start ad completio of a evet 30-80X improvemet for processors 6-8X improvemet for memory ad disks 5 Feature size Trasistors ad wires Miimum size of trasistor or wire 10 micros i 1971 to 22 m i 2012 (16 m i 2014) Trasistor performace scales liearly Wire delay does ot improve with feature size! Itegratio desity scales quadratically Relative maufacturig cost per compoet Moore s ote (1965) Number of compoets per itegrated circuit 6

4 Switches Buildig block for digital logic NAND, NOR, NOT, Techology advaces have provided desigers with switches that are Faster; Lower power; More reliable (e.g., vacuum tube vs. trasistor); ad Smaller. Nao-scale techologies will ot cotiue promisig the same good properties 7 History of switches Called relay ; Mark I (1944) Bell lab. (1947); Kilby s first IC (1957) Vacuum tubes; ENIAC (1946, 18k tubes) Solid-state MOS devices 8

5 Power ad Eergy ( 1.5) Need to get power i ad out (thermal implicatios) Dyamic eergy (to switch trasistors) Eergy is proportioal to Voltage 2 Power is proportioal to (Voltage 2 x Frequecy) Dyamic Frequecy Scalig (reduces power ot eergy) voltage scalig Static power is proportioal to the voltage Memory power modes ad turig off cores 9 Computer Egieerig Methodology Evaluate Existig Systems for Bottleecks Implemet Next Geeratio System Techology treds Simulate New Desigs ad Orgaizatios 10

6 Itegrated Circuits s( 1.6) Dies per Wafer * Wafer _ diam 2 Die Area 2 * Wafer _ diam 2 * Die area Die yield wafer yield * Where N = process complexity factor = (40m, 2010) 1 Defect _ per _ uit _ area * Die _ area N IC Die Testig Fial Test Packagig Yield Die Die per Wafer Wafer * Die Yield 11 Depedability ( 1.7) Fault: failure of a compoet Error: maifestatio of a fault Faults may or may ot lead to system failure Normal operatio MTTF MTTR MTTF time Restoratio (repair) Failure MTBF Reliability measure: mea time to failure (MTTF) Service iterruptio Repair efficiecy: mea time to repair (MTTR) Mea time betwee failures MTBF = MTTF + MTTR Availability = MTTF / MTBF Improvig Availability Icrease MTTF: fault avoidace, fault tolerace, fault forecastig Reduce MTTR: improved tools ad processes for diagosis ad repair 12

7 Performace ( 1.8) Applicatio Programmig Laguage Compiler ISA Datapath Cotrol Fuctio Uits Trasistors Wires Pis Aswers per moth Operatios per secod (millios) of Istructios per secod: MIPS (millios) of (FP) operatios per secod: MFLOP/s Megabytes per secod Cycles per secod (clock rate) 13 Measurig Performace Time to ru the task (latecy) Executio time, respose time, CPU time, Tasks per day, hour, week, sec, s, Throughput, badwidth Performace measuremet Tools Hardware prototypes :, delay, area, power estimatio Simulatio (may levels, ISA, RT, Gate, Circuit, ) Bechmarks (Kerels, toy programs, sythetic), Traces, Mixes Aalytical modelig ad Queuig Theory 14

8 Bechmarks SPEC: Stadard Performace Evaluatio Corporatio PARSEC: Priceto Applicatio Repository for Shared- Memory Computers MediaBech: Multimedia ad embedded applicatios Trasactio processig- TPC-C, SPECjbb Embedded Microprocessor Bechmark Cosortium EEMBC: Networkig, telecom, digital cameras, cellular phoes,... Staford parallel bechmarks: For parallel architecture ad shared memory multiprocessors NAS: For massively parallel processor systems Rodiia: for GPU applicatios 15 How to Summarize Performace Arithmetic mea (weighted arithmetic mea) Ti ex: tracks executio time: or i1 i1 W i T i Harmoic mea (weighted harmoic mea) of rates ex: track MFLOPS: i 1 1 Rate i Normalized executio time is hady for scalig performace (e.g., X times faster tha Petium 4) 1 executio _ ratio Geometric mea ==> i i where the executio ratio is relative to a referece machie 16

9 Performace Evaluatio Good products created whe we have: Good bechmarks Good ways to summarize performace For better or worse, bechmarks shape a field. Give that sales is a fuctio, i part, of performace relative to competitio, compaies ivest i improvig performace summary If bechmarks/summary are iadequate, the choose betwee improvig product for real programs vs. improvig product to get more sales ===> Sales almost always wis! Reproducibility is importat (should provide details of experimets) Executio time ad power are the mai measure of computer performace! 17 Amdahl's Law ( 1.9) Speedup due to some ehacemet E: ExTimewithoutE Speedupoverall ExTime withe Performace Performace withe withoute Suppose that ehacemet E accelerates a fractio of the task by a factor S, ad the remaider of the task is uaffected ExTime ExTime withe withoute 1 fractio ehaced fractio S ehaced Example: Floatig poit istructios ca be improved to ru 2X; but oly 10% of actual istructios are FP. What is the overall speedup? 18

10 Computig CPU time Average Cycles per Istructio (CPI) = j CPI 1 j F j CPI Where j is the umber of cycles eeded to execute istructios of type j, ad is the percetage (fractio) of istructios that are of type j. F j Example: Base Machie (Reg / Reg) Op Freq Cycles CPI j *F j (% Time) ALU 50% 1.5 (33%) Load 20% 2.4 (27%) Store 10% 2.2 (13%) Brach 20% 2.4 (27%) 1.5 Typical Mix Istructios Per Cycle (IPC) = 1 /CPI 19 CPU time Cycle time CPI j 1 j I j Where I j is the umber of istructios of type j, ad Cycle time is the iverse of the clock rate. CPU time = total # of istructios x CPI x Cycle time Example: For some programs, Machie A has a clock cycle time of 10 s. ad a CPI of 2.0 Machie B has a clock cycle time of 20 s. ad a CPI of 1.2 What machie is faster for this program, ad by how much? 20

11 Aspects of CPU Performace CPU _ time Secods program Istructios program Cycles Istructios Secods Cycle Program Ist Cout CPI Clock Rate X Compiler X X Ist. Set. X X Orgaizatio X X Techology X 21 A example: Improvig CPI usig caches 30% 70% CPU cache memory 10.sec 100.sec What is the improvemet (speedup) i memory access time? Cachig works because of the priciple of locality: Locality foud i memory access istructios Temporal locality: if a item is refereced, it will ted to be refereced agai soo Spatial locality: if a item is refereced, items whose addresses are close by ted to be refereced soo 90/10 locality rule A program executes about 90% of its istructios i 10% of its code We will look at how this priciple is exploited i various microarchitecture techiques 22