Custom Computing. wl

Transcription

1 Custom Computing theory and practice of customising designs one of the fastest growing technologies impact on ASIC, CPU, many-core, GPU, multi-scale dataflow wide range of architectures and applications data-centre/supercomputers with user-customisable accelerators message routers, mobile robots, LCD TVs, car audio systems invent processors with your own instruction set! based mainly on customisable implementation technology e.g. Field-Programmable gate Arrays (FPGAs) also called reconfigurable computing, FPGA-based computing we focus on concepts, abstractions, design methods requirement: willing to learn new ideas, languages, tools not afraid of C/Java/functional programs, maths, hardware wl

2 Course coverage topics custom computing technology overview design parametrisation and optimisation system-on-chip architecture and design 18 lectures, 8 tutorials (flexible), 1 assessed exercise course material EEE students: may need access via EEE machines preparation for projects and research many received project prizes or distinctions summer projects for non-msc students wl

3 Why custom computing? FPGAs: customisable hardware resources data centres for cloud computing mobile handsets, Internet of Things (IoT), edge computing acceleration of demanding workloads big data, finance, genomics, weather/climate modelling, integrated solution: often with interface to memory, sensors target multiple platforms: need to promote design re-use design approach: generalisation + customisation often start with design instance: f 0 generalise f 0 to become a template f(x), such that f(x 0 ) = f 0 where x is a parameter and x 0 is a specific value for x customise f with values for x to support tradeoff in speed, size generalise f 0 f(x) customise x=x 3 x=x 1 x=x 2 x=x 0 f 1 f 2 f 3 wl

4 Benefits of customisation improvements in accuracy: as needed, not necessarily 8, 32, 64, 128 bits throughput: rate of producing results latency: time between first input and first output reconfiguration time: speed of adapting to changes size: area, volume, weight energy and power consumption: mobile and remote applications development time: design and validation cost: minimise fabrication, post-delivery fixes, enhancements need to prioritise design objectives e.g. smallest design at a given speed consuming given energy opportunities for customisation application-oriented, e.g. run-time conditions implementation-oriented, e.g. technology used wl

5 Implementation technology application-specific integrated circuit (ASIC) high performance, low part cost: cheap if producing large volume high risk, high development cost, slow time-to-market costly (Moore s Second Law) to develop, build and test, inflexible Field-Programmable Gate Array (FPGA) low risk, fast time-to-market, low development cost, high part cost post-delivery improvement: fix bugs, update functions customisable at run time: adapt to environment changes prototype for ASIC enable internet routing custom computing systems stand-alone PCIe / Infiniband system-on-chip: instruction processor + FPGA wl

6 Flexibility Technology comparison FPGAs General-Purpose Processors Digital Signal Processors Special-Purpose Processors ASICs Efficiency, Performance (adapted from K. Fan, HPCA 09) wl

7 Where are FPGAs? Consumer applications Digital Camera & Editing STB, DVR & VTR Home Networking Home Computing PDP & HDTV LCD Projectors Automotive Handheld Automotive Diagnostics (source: Xilinx Inc.) wl

8 New: accelerators for data centre servers Smart NIC (Network Interface Controller) compute accelerator: local / remote infrastructure accelerator: network / storage Source: Microsoft flexibility of Software Defined Network + speed of hardware wl

9 Accelerate clouds: Microsoft + Amazon aws.amazon.com/ec2/instance-types/f1/ wl

10 Why Intel bought Altera IP: Intellectual Property wl Source: Intel

11 Drones + IoT + Aerotenna: Octagonal Pilot on Chip Source: Intel ASSP: Application-Specific Standard Part SAM: Serviceable Available Market wl

12 Particle Physics: Large Hadron Collider real-time analysis of particle collision combine data from various detectors (source: Xilinx Inc.) (source: G. Hall) Opto-to-electrical conversion Digitise & sync data Find hit clusters Optical ribbon cable input Opto-RX, 12 way 3 x Delay FPGA (ADC clk timing) Virtex II, 2M gate FPGA performs signal processing wl

13 Customisation: pre-fab and post-fab fabrication: manufacturing the chip Xilinx UltraScale FPGA: 16nm, Intel i7-i770t: 22nm costly: very small geometry, ultra-clean room application-specific integrated circuit (ASIC) greatest customisation at pre-fabrication, but could be inflexible high performance, low part cost: cheap if producing large volume high risk, high development cost, slow time-to-market costly (in money and time) to develop and test: Moore s Law field-programmable gate array (FPGA) post-fabrication, post-delivery, even run-time customisation hardware speed, software flexibility most basic, fine-grained unit of programmability need larger function blocks for efficiency wl

14 Design metrics NRE (non-recurring engineering) cost one-time cost of designing system total cost: total cost = NRE cost + unit cost * number of units size, performance, power flexibility make changes to the hardware with low NRE cost time-to-prototype, time-to-market maintainability correctness, safety, robustness Source: J. Wong wl

15 Cost FPGA/ASIC crossover points FPGA Cost Advantage FPGA FPGA Cost Advantage Cost Advantage ASIC Cost ASIC Advantage Cost Advantage Production Volume Source: S.S.S.P. Rao wl

16 FPGA vs ASIC FPGA faster time-to-market no layout, masks or other manufacturing steps are needed no upfront NRE costs simpler design cycle software tools for routing, placement, and timing more predictable project cycle field re-programmability ASIC full custom capability for design since device is manufactured to design specs lower unit costs for very high volume smaller form factor device is made to design specs higher raw internal clock speeds Source: J. Wong wl

17 Design flows HDL: Hardware Description Language DFT: Design For Test Source: J. Wong wl

18 Early FPGA architecture Logic Block Connection Block Switch Block Routing Track (Horizontal) { Routing Channel (Vertical) Source: S. Wilton TILE wl

19 Basic logic gate: lookup table Inputs Reconfigurable logic Bit-Stream Function of each lookup table can be configured by shifting in bit-stream. Source: S. Wilton wl

20 Basic logic gate: lookup table Inputs Reconfigurable logic D Q Function of each lookup table can be configured by shifting in bit-stream. By-passable register at output. Source: S. Wilton wl

21 Reconfigurable logic Connect logic blocks using fixed metal tracks and programmable switches Source: S. Wilton wl

22 Reconfigurable logic Connect logic blocks using fixed metal tracks and programmable switches Everything can be built using finegrained logic; why need anything else? Source: S. Wilton wl

23 Implementing systems in an FPGA FPGA vendors embed fixed blocks to improve speed and density: Embedded Memories (blocks of 2K-18K) But every user must pay for them, whether used or not Source: S. Wilton wl

24 Implementing systems in an FPGA FPGA vendors embed fixed blocks to improve speed and density: Embedded Memories (blocks of 2K-18K) Hard Blocks, eg multiplier But every user must pay for them, whether used or not Source: S. Wilton wl

25 Implementing systems in an FPGA FPGA vendors embed fixed blocks to improve speed and density: Embedded Memories (blocks of 2K-18K) Hard Blocks, eg multiplier High-Speed I/Os But every user must pay for them, whether used or not Source: S. Wilton wl

26 Example: Xilinx Virtex CLB tile CLB tile is composed of: switch matrix Configurable Logic Block and associated general routing resources IMUX and OMUX LONG HEX SINGLE LONG HEX SINGLE SWITCH MATRIX CARRY LONG HEX SINGLE CARRY TRISTATE BUSSES all CLB inputs have access to interconnect on all 4 sides fast local feedback within CLB and direct connects to east and west CLBs: support wide functions of up to 19 inputs within a single CLB DIRECT CONNECT LONG HEX SINGLE SLICE CARRY Local Feedback CLB SLICE CARRY DIRECT CONNECT Source: Xilinx Inc. wl

27 Simplified CLB structure CLB Slice 0 Slice 1 PRE LUT Carry D Q CE CLR PRE LUT Carry D Q CE CLR LUT Carry PRE D Q CE LUT Carry PRE D Q CE CLR CLR two slices in each CLB two BUFTs associated with each CLB, accessible by all 8 CLB outputs carry Logic runs vertically upwards, to speed up carry propagation Source: Xilinx Inc. wl

28 A B C D Look-Up Tables combinatorial logic is stored in Look-Up Tables (LUTs) in a CLB capacity is limited by number of inputs, not complexity delay through CLB is constant Combinatorial Logic Z A B C D Z wl

29 Stratix IVGX 230: mid-size device DSP Blocks (coarse grain) Adaptive Logic Modules (fine grain) RAM Blocks (M9K & M144K) High Speed Serial Interfaces: (source: V. Betz) eg connect multiple FPGAs wl

30 Stratix IV Overview Feature Stratix III (65 nm) Stratix IV (40 nm) Logic Elements 340k 680k RAM bits 16 Mb + 4 Mb 33 Mb Mb 18x18 multipliers General I/O High-speed serial links 0 48 transmit Gb/s Hard PCIe blocks 0 4 Clock generation 12 PLL(x10) 12 PLL(x10) + 32 serial recovered serial transmit Clock distribution 16 Global + 88 Quadrant PCLK 16 Global + 88 Quadrant PCLK (from V. Betz) wl

31 Current and future: System-on-Chip I/O Ring and Interface Circuitry Embedded Processor Fixed IP Block Fixed IP Block Processor eg ARM - functionality specified using software On-Chip Memory Reconfigurable Logic I/O Ring and Interface Circuitry Programmable Logic - circuit can be specified / modified after fabrication, possibly at run time - maybe slower than fixed IP block Source: S. Wilton Fixed Intellectual Property Block - functionality fixed at design time - little post-fab flexibility wl

32 Summary custom computing: theory and practice of customisation from data centres/cloud computing to mobile appliances customisable off-the-shelf implementation technology e.g. FPGAs, coarse-grained/hybrid processors, custom instructions factors favouring field-programmability rise in FPGA capability: many exciting applications rise in integrated circuit fabrication cost: zero for FPGA users! customisation: facilitate product evolution and prototyping custom computing tools + applications at Imperial College financial analysis/trading, multimedia processing, medical imaging network firewall, data compression/encryption, mobile robots bio-informatics, machine learning, bio-inspired/self-aware systems see: wl