Structure of Computer Systems

Transcription

1 Structure of Computer Systems

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3 Structure of Computer Systems Baruch Zoltan Francisc Technical University of Cluj-Napoca Computer Science Department U. T. PRES Cluj-Napoca, 2002

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5 CONTENTS PREFACE... xiii 1.INTRODUCTION TAXONOMIES OF COMPUTER ARCHITECTURES OVERVIEW OF COMPUTER ARCHITECTURES Multiprocessors Multicomputers Multi-multiprocessors Data Flow Architectures Array Processors Pipelined Vector Processors Systolic Arrays Hybrid Architectures Artificial Neural Networks Fuzzy Logic Processors PERFORMANCE AND QUALITY MEASUREMENTS Execution time CPU Performance MIPS MFLOPS Other performance measurements Benchmark programs Comparing and Summarizing Performance The Evolution of Benchmark Programs CPU CPU Quality factors QUANTITATIVE PRINCIPLES OF COMPUTER DESIGN... 27

6 vi Structure of Computer Systems Amdahl s Law Locality of Reference PROBLEMS DESIGN REPRESENTATION AND METHODOLOGY SYSTEM REPRESENTATION LEVELS OF DESCRIPTION DESIGN PROCESS System-Level Synthesis High-Level Synthesis Register-Transfer Level Synthesis Logic-Level Synthesis Technology Mapping VHDL HARDWARE DESCRIPTION LANGUAGE Hardware Description Languages Introduction to VHDL VHDL Styles of Description The Time Model in VHDL Simulation of a Model ARITHMETIC-LOGIC UNIT ADDITION Full Adder Ripple Carry Adder Carry Lookahead Adder Carry Select Adder Carry Save Adder Serial Adder Binary-Coded Decimal Number Addition MULTIPLICATION Shift-and-Add Multiplication Booth s Technique Wallace Tree Shifting Over Zeros and Ones Array Multiplier DIVISION Restoring Division Nonrestoring Division SRT Division Other Fast Division Methods Array Divider Signed Division FLOATING-POINT NUMBERS Floating-Point Representation Principles... 85

7 Contents vii IEEE 754 Floating-Point Standard Floating-Point Operations Floating-Point Addition and Subtraction Floating-Point Multiplication and Division Precision Considerations PROBLEMS MEMORY SYSTEMS MEMORY HIERARCHY MEMORY TYPES MEMORY PERFORMANCE MEASURES SEMICONDUCTOR MAIN MEMORY Memory Cell and Memory Unit Memory Organization Memory Design Example of a Commercial Memory Circuit Performance Parameters of DRAM Memories Technologies for DRAM Memories Categories of DRAM Memories FPM DRAM EDO DRAM BEDO DRAM SDRAM HSDRAM ESDRAM Virtual Channel Memory FCRAM DDR SDRAM DDR II SDRAM RDRAM and DRDRAM IRAM Memory Modules INTERLEAVED MEMORY ASSOCIATIVE MEMORY CACHE MEMORY Principle of Cache Memory Cache Memory Organization Cache Memory Operation Address Mapping Associative Mapping Direct Mapping Set-Associative Mapping Replacement Policies Random Replacement Least Frequently Used

8 viii Structure of Computer Systems Least Recently Used (LRU) Cache Memory Types Cache Memory Performance Cache Memory Coherence VIRTUAL MEMORY Principle of Virtual Memory Address Translation Paging Segmentation Paging and Segmentation Memory Allocation Non-preemptive Allocation Preemptive Allocation Replacement Policies Memory Management in the Intel Architecture Memory Management Overview Segmentation Paging PROBLEMS PIPELINING PIPELINE STRUCTURE PIPELINE PERFORMANCE MEASURES PIPELINE TYPES INSTRUCTION PIPELINES Principle of Instruction Pipelines The Fetching Problem The Bottleneck Problem The Structural Hazard Problem The Data Hazard Problem Data Dependencies Tomasulo s Method Scoreboard Method The Control Hazard Problem Branch Instructions Branch Prediction Delayed Branching Multiple Prefetching The Intel Architecture Processors Pipeline Fetch/Decode Unit Instruction Pool Dispatch/Execute Unit Retirement Unit Bus Interface Unit Throughput Improvements of an Instruction Pipeline

9 Contents ix Superscalar Processing Superpipeline Processing Very Long Instruction Word Explicitly Parallel Instruction Computing Comparison of Throughput Improvement Methods ARITHMETIC PIPELINES Principle of Arithmetic Pipelines Design of an Arithmetic Pipeline Arithmetic Pipelines with Feedback Pipelined Multipliers Systolic Arrays PIPELINE CONTROL Scheduling Scheduling Static Pipelines Scheduling Dynamic Pipelines PROBLEMS RISC ARCHITECTURES INTRODUCTION CAUSES FOR INCREASED ARCHITECTURAL COMPLEXITY ADVANTAGES OF RISC ARCHITECTURES THE USE OF A LARGE NUMBER OF REGISTERS CHARACTERISTICS OF RISC ARCHITECTURES COMPARISON BETWEEN RISC AND CISC ARCHITECTURES APPLICATIONS OF RISC PROCESSORS MIPS Introduction MIPS R MIPS R MIPS R MIPS R MIPS R MIPS R4300i MIPS R MIPS R4600, R4650 and R MIPS R MIPS-III Architecture Hardware Details Software Details Floating-Point Unit Cache Memories Memory Management Exceptions MIPS R8000 and R Introduction

10 x Structure of Computer Systems Hardware Details Software Details Floating-Point Unit Cache Memories Memory Management MIPS R Overview Increased 3D Graphics Performance Multi-Processing Support Secondary Cache Memory Support Flexible Clocking Mechanism Summary SPARC Introduction HyperSPARC SuperSPARC MicroSPARC and MicroSPARC-II SPARClite UltraSPARC-I UltraSPARC-II UltraSPARC-IIi Overview Block Diagram Prefetch and Dispatch Unit Integer Execution Unit Floating-point Unit I/O Memory Management Unit Memory Controller Unit Load-Store Unit Data and Instruction Cache Memories External Cache Unit Graphics Unit The Visual Instruction Set UltraSPARC-III MAJC Summary ALPHA Introduction Alpha and 21064A Overview Block Diagram Instruction Fetch/Decode Unit Integer Execution Unit Floating-Point Execution Unit Address Unit

11 Contents xi Branch Unit Cache Memory Software Details Memory Management Alpha 21066, 21066A and Alpha and 21164PC Overview Block Diagram Instruction Fetch/Decode and Branch Unit Integer Execution Unit Floating-Point Execution Unit Memory Address Translation Unit Cache Control and Bus Interface Unit Cache Memories Serial Read-Only Memory Interface Alpha Overview Block Diagram Instruction Fetch, Issue, and Retire Unit Integer Execution Unit Floating-Point Execution Unit Cache Memories Memory Reference Unit External Cache Memory and System Interface Unit SROM Interface Summary POWERPC Introduction PowerPC Overview Block Diagram Instruction Unit Execution Units Cache Memory Memory Management Software Details Exceptions PowerPC PowerPC 603 and 603e PowerPC 604 and 604e PowerPC 740 and Overview Block Diagram Instruction Unit Completion Unit

12 xii Structure of Computer Systems Integer Units Floating-Point Unit Load/Store Unit System Register Unit Memory Management Units On-Chip Cache Memories L2 Cache Memory Bus Interface Unit PowerPC Overview AltiVec Vector Permute Unit AltiVec Vector Arithmetic-Logic Unit PowerPC 850 and Overview Block Diagram The PowerPC Core System Interface Unit PCMCIA Controller Communications Processor Module Differences between the MPC850 and MPC860 processors Summary PROBLEMS BIBLIOGRAPHY INDEX