Learning Outcomes. Spiral 2-9. Typical Logic Gate TRI-STATE GATES

Transcription

1 2-9.1 Learning Outcomes Spiral 2-9 Tri-State Gates Memories DMA I understand how a tri-state works and the rules for using them to share a bus I understand how SRAM and DRAM cells perform reads and writes I understand the pros and cons of SRAM and DRAM I understand how modern memories optimize sequential access I know what a DMA engine is and why it is used I understand the difference between big- and littleendian byte ordering and the problems that might arise when transferring between different orderings Typical Logic Gate Gates can output two values: 0 & 1 Logic 1 (Vdd = 3V or 5V), or Logic 0 (Vss = GND) But they are ALWAYS!!! Analogy: a sink faucet 2 possibilities: Hot ( 1 ) or Cold ( 0 ) In a real circuit, inputs cause a pathway from output to VDD VSS +3V +3V Hot Water = Cold Water = (Strapped together so always one type of water coming out) Inputs TRI-STAT GATS Inputs PMOS Output Inputs PMOS Output Vdd NMOS NMOS Vss

2 Output Connections Can we connect the output of two logic gates together?! Possible (static, low-resistance pathway from Vdd to GND) We call this situation bus Src 1 Src 2 Src 3 Vdd Vss Vdd Vss Inputs Inputs Src 1 Src Tri-State Buffers Normal digital gates can output two values: 0 & 1 1. Logic 0 = 0 volts 2. Logic 1 = 5 volts Tristate buffers can output a third value: 3. = = "Floating" (no connection to any voltage source infinite resistance) Analogy: a sink faucet 3 possibilities: 1.) Hot water, 2.) Cold water, 3.) NO water Inputs Hot Water = Logic 1 Cold Water = Logic 0 PMOS NMOS NO Water = +3V Output Tri-State Buffers Tri-State Buffers Tri-state buffers have an extra input When disabled, output is said to be at high impedance (a.k.a. Z) High Impedance is equivalent to no connection (i.e. floating output) or an infinite resistance It's like a brick wall between the output and any connection to source When enabled, normal buffer Tri-State Buffer In Out = In nable=1 In Out = nable=0 n In Out We use tri-state buffers to share one output amongst several sources Rule: Only at a time Src 1 N1 Src 2 N2 Src 3 D Q D-FF CLK Q N3

3 Tri-State Buffers We use tri-state buffers to share one output amongst several sources When 1 buffer enabled, its output overpowers the Z s (no connection) from the other gates Select source 1 to pass its data output of 0 overpowers the Z transmitter receivers Bidirectional Bus ach device can send (though ) or receive 0 1 Z 0 D Q D-FF CLK Q Z Disabled buffers output Z Tri-State Implementation To implement we simply add a pair of inner transistors that can BOTH be turned off This would isolate the output from any Vdd or GND connection Tri-State Implementation To implement we simply add a pair of inner transistors that can BOTH be turned off This would isolate the output from any Vdd or GND connection

4 Tri-State Implementation If 1 = 0 then the upper tri-state will isolate the output from any Vdd/GND connection If 2 = 1 then the lower tri-state acts as a normal inverter If both 1=0, 2=0 then the output is floating (Z = high impedance) TRANSMISSION GAT & PASS TRANSISTORS Why NMOS Pass Weak 1s We've said NMOS are: Pass a strong 0 but a weak 1 Let's explore why In the first case one side is tied to GND and thus is the ( side is the source) Vgs = Vdd and transistor will stay on no matter what the drain voltage is (eventually Vd will equal 0) In the second case one side is tied to Vdd and thus the other terminal is the (source is the lower voltage terminal) As the source node charges up eventually it will reach but at that point Vgs = Recall to stay on the transistor must have. So the transistor will turn off and not allow the source to charge all the way to Vdd Why PMOS Pass Weak 0s We've said PMOS are: Pass a strong 1 but a weak 0 For similar reasons as on the previous slide when we try to pass a 0 through a PMOS transistor the transistor will turn off when This prevents the PMOS from passing a strong 0 Vdd S A=0 G D V out GND D A=0 G S V out

5 Transmission Gates Well if one is good at passing 0's and one is good at passing 1's why not use A Transmission gate puts a PMOS and NMOS transistors in Depending on the input voltage at the either the NMOS or PMOS can pull the drain up/down to that voltage Use inputs at each gate to ensure only one transistor is on Transmission Gates We can even connect the source to some other signal rather than a constant voltage In the example to the right, if A = 1 (A' = 0) then This gate produces when A=1 ( ) when A= Transmission Gate Symbols The CMOS TG operates as a bidirectional switch between nodes A and B, which is controlled by signal C More Transmission Gates By making complementary cases of transmission gates we can build some useful structures What is this structure? C A B C Different representations (symbols) of the CMOS TGs

6 More Transmission Gates What is this structure? MMORY The Memory Wall Problem: The Memory Wall Processor speeds have been increasing than memory access speeds (Memory technology targets density rather than speed) Large memories yield large address decode and access times Main memory is physically located on separate chips and inter-chip signals have much higher propagation delay than intra-chip signals MMORY TCHNOLOGIS 55%/year Processor-Memory Performance Gap 7%/year Hennessy and Patterson, Computer Architecture A Quantitative Approach (2003) lsevier Science

7 Improving Memory Performance Possibilities for improvement Technology Can we improve our transistor-level design to create faster RAMs Can we integrate memories on the same chip as our processing logic Architectural Can we organize memory in a more efficient manner (this is our focus) DRAM & SRAM Memory Technology Static RAM (SRAM) Will retain values (as long as ) Stored bit is remembered (driven and regenerated by circuitry) Dynamic RAM (DRAM) Will lose values if not Stored bit is remembered and needs to be regenerated by external circuitry Memory Array Logical View = 1D array of rows (words) Already this is 2D because each word is 32-bits (i.e. 32 columns) Physical View = 2D array of rows and columns ach row may contain 1000 s of columns (bits) though we have to access at least 8- (and often 16-, 32-, or 64-) bits at a time C8004DB2 0x000c 89AB97CD AB4982F AB 1D Logical View (ach row is a single word = 32-bits) 0x0008 0x0004 0x x x x D Physical View (e.g. a row is 1KB = 8Kb)

8 Mx8 Memory Array Layout and Column Start with array of cells that can each store 1-bit 1 MB = 8 Mbit = 2 23 total cells This can be broken into a 2D array of cells ( ) ach row connects to a WL = which selects that row ach column connects to a BL = for read/write data 8K Bit Lines BL[0] BL[8191] WL[0] 1K Word Lines WL[1023] For 1MB we need address bits 10 upper address bits can select one of the 1024 rows Suppose we always want to read/write an 8-bits (byte), then we will group each set of 8-bits into 1024 byte columns (1024*8=8K) 10 address bits will select the Addr. A[ ] -bits Addr. Decoder WL[0] 2 10 word lines WL[1023] 8K Bit Lines BL[0] BL[8191] Col. Addr. Amplifiers & Column Mux A[ ] -bits Data in/out [7:0] Periphery Logic Memory Technologies decoders selects one row based on the input address number Bit lines are bidirectional lines for reading (output) or writing (input) Column multiplexers use the address bits to select the right set of 8-bits from the 8K bit lines Addr. A[19:10] 10-bits Addr. Decoder WL[0] 2 10 word lines WL[1023] Addr. A[9:0] 10-bits 8K Bit Lines BL[0] BL[8191] Amplifiers & Column Mux Data in/out [7:0] Memory technologies share the same layout but differ in their cell implementation Static RAM (SRAM) Will retain values indefinitely (as long as power is on) When read, the stored bit is driven onto the bit lines Dynamic RAM (DRAM) Will lose values if not refreshed periodically When read, the stored bit pulls the bit line voltage up or down slightly and needs to be 8K Bit Lines BL[0] BL[8191] WL[0] Addr. Addr. Decoder WL[1023] Addr. Amplifiers & Column Mux Data in/out

9 SRAM DRAM ach memory cell requires transistors ach cell consists of a is made from cross connected inverters which have active connections to PWR and GND. Thus, the signal is and as long as power is supplied BL[0] D/Q SRAM Core nable Bit is stored on a capacitor and requires only transistor and a WL BL Transistor acting as a switch WL Capacitor SRAM core implementation DRAM DRAM Bit is stored on a capacitor and requires only 1 transistor Write WL=1 connects the capacitor to the BL which is driven to 1 or 0 and capacitor based on the BL value WL BL 1 Transistor acting as a switch Bit is stored on a capacitor and requires only 1 transistor Write WL=1 connects the capacitor to the BL which is driven to 1 or 0 and charges/discharges capacitor based on the BL value With WL=0 transistor is closed and value stored on the capacitor WL BL 0 Transistor is now off trapping charge on capacitor Capacitor maintains 5V charge

10 DRAM DRAM Issues Bit is stored on a capacitor and requires only 1 transistor Write WL=1 connects the capacitor to the BL which is driven to 1 or 0 and charges/discharges capacitor based on the BL value Read BL is precharged to 2.5 V WL=1 connects the capacitor to the BL allowing charge on capacitor to change the voltage on the BL WL Sense Amp. BL 2.7 V 2.5 V 2.3 V 1 Transistor acting as a switch Capacitor charge (or lack of charge) changes the BL voltage slightly Bitline is precharged to 2.5V and then capacitor charge slightly raises or lowers BL voltage Sense amp drives voltage the rest of the way to 5V or 0V Charge is when capacitor value is Need to write whatever is. Current Charge slowly the cap. Value must be periodically WL BL Transistor acting as a switch Capacitor SRAM vs. DRAM Summary SRAM because bit lines are actively driven by the D-Latch, simpler interface due to lack of refresh for each cell which means less memory per chip Used for where speed/latency is key DRAM because passive value (charge on cap.) drives BL due to refresh cycles means much greater density of cells and thus large memories Used for memory where density is key MMORY ARCHITCTURS

11 Implications of Memory Technology Legacy DRAM Timing Memory latency of a single access using current DRAM technology will be slow We must improve bandwidth Idea 1: Access than just a word at a time Technology: DO, SDRAM, etc. Idea 2: Increase number of accesses serviced Technology: Can have only a single access in-flight at once Memory controller must send row and column address portions for each access active holds the row open for reading/writing active selects the column to read/write t RC t RAC t RC = Cycle Time ( ) = Time before next access can start t RAC =Access Time ( ) = Time until data is valid Column Legacy DRAM (Must present new /Column address for each access) Decoder /RAS /CAS Timing Generator Column Muxes Data in / out Memory Array Fast Page Mode DRAM Timing DO DRAM Timing Can provide multiple column addresses with only one row address Similar to FPM but overlaps data i with column address i+1 /RAS /CAS Timing Generator Memory Array /RAS /CAS Timing Generator Memory Array Reg. Decoder Reg. Decoder Column Column Muxes Column Column Muxes Fast Page Mode (Future address that fall in same row can pull data from the latched row) Data in / out DO (xtended Data Out) Column address i+1 is sent while data i is being transferred on the bus Data in / out

12 Synchronous DRAM Timing DDR SDRAM Timing Registers the column address and automatically increments it, accessing n sequential data words in n successive clocks called n= or usually) /RAS /CAS Timing Generator CLK Memory Array Double data rate access data every clock cycle /RAS /CAS Timing Generator CLK Memory Array CLK /RAS /CAS Reg. Decoder Reg. Decoder MC Bus Data Bus Column Data i Data i+1 Data i+2 Data i+3 Column Reg/Cntr Column Latch/Register Column Muxes Column Reg/Cntr Column Latch/Register Column Muxes SDRAM (Synchronous DRAM) Addition of clock signal. Will get up to n consecutive words in the next n clocks after column address is sent Data in / out DDR SDRAM (Double-Data Rate SDRAM) Addition of clock signal. Will get up to 2n consecutive words in the next n clocks after column address is sent Data in / out Banking Bank Access Timing Divide memory into banks duplicating row/column decoder and other peripheral logic to create independent memory arrays that can access data in parallel uses a portion of the address to determine which bank to access Consecutive accesses to banks can be and hide the time to access the row and select the column Consecutive accesses within (to different rows) exposes the access latency Bank 0 Bank 1 / Column Bank 2 Bank 3 Bank Bank 0 Bank Bank 0 Data CLK MC Bus Data Bus 1 Col 1 2a Col 2a 2b Col 2b Delay due to bank conflict Data Data 1 Data 2a Data 2b Access 1 maps to bank 1 while access 2a maps to bank 2 allowing parallel access. However, access 2b immediately follows and maps to bank 2 causing a delay.

13 Programming Considerations For memory configuration given earlier, accesses to the same bank but different row occur on an 32KB boundary Now consider a matrix multiply of 8K x 8K integer matrices (i.e. 32KB x 32KB) In code below 0x while 0x Unused Rank Bank Col. Unused A31,A30 A29 A28 A15 A14,A13 A12 A3 A2..A0 0x x x m1 m int m1[8192][8192], m2[8192][8192], result[8192][8192]; int i,j,k;... for(i=0; i < 8192; i++){ for(j=0; j < 8192; j++){ result[i][j]=0; for(k=0; k < 8192; k++){ result[i][j] += matrix1[i][k] * matrix2[k][j]; } } } DMA & NDIAN-NSS Direct Memory Access (DMA) Data Transfer w/o DMA Large buffers of data often need to be copied between: (video data, network traffic, etc.) (OS space to user app. space) DMA devices are small hardware devices that copy data from a source to destination freeing the processor to do CPU I/O Device (USB) DMA System Bus I/O Bridge I/O Bus Memory I/O Device (Network) Without DMA, processor would have to move data using a loop Move 16Kwords pointed to by ($s1) to ($s2) li $t0,16384 AGAIN: lw $t1,0($s1) sw $t1,0($s2) addi $s1,$s1,4 addi $s2,$s2,4 subi $t0,$t0,1 bne $t0,$zero,again Processor wastes valuable execution time moving data CPU I/O Device (USB) System Bus I/O Bridge I/O Bus Memory I/O Device (Network)

14 Data Transfer w/ DMA DMA ngines Processor sets values in DMA control registers Control & Status (Start, Stop, Interrupt on Completion, etc.) DMA becomes (controls system bus to generate reads and writes) while processor is free to execute other code Small problem: Hopefully, data & code needed by the CPU will reside in CPU I/O Device (USB) DMA System Bus I/O Bridge I/O Bus DMA Control Registers Memory I/O Device (Network) Systems usually have multiple DMA engines/channels ach can be configured to be started/controlled by the processor or by certain I/O peripherals Network or other peripherals can initiate DMA s on their behalf Bus arbiter assigns control of the bus Usually winning requestor has control of the bus until it relinquishes it (turns off its request signal) Bus Masters Internal System Bus Slave devices Requests / Grants Processor Core DMA Channel 0 Bus Arbiter DMA Channel 1 DMA Channel 2 DMA Channel 3 Memory Peripheral Peripheral ndian-ness Big-endian vs. Little-endian ndian-ness refers to the two alternate methods of in a larger unit (word, long, etc.) Big-ndian PPC, Sparc MS byte is put at the starting address Little-ndian used by Intel processors / PCI bus LS byte is put at the starting address The longword value: 0 x can be stored differently 0x x x x x x x x03 12 Big-ndian Little-ndian es increasing downward Big-endian makes sense if you view your memory as starting at the top-left and addresses increasing as you go down C Little-endian makes sense if you view your memory as starting at the bottom-right and addresses increasing as you go up C es increasing upward Byte 0 Byte 1 Byte 2 Byte 3 Byte 3 Byte 2 Byte 1 Byte 0

15 Big-endian vs. Little-endian Issues arise when transferring data between different systems Byte-wise copy of data from big-endian system to little-endian system Major issue in networks (little-endian computer => big-endian computer) and even within a single computer (System memory => Peripheral (PCI) device) es increasing downward Big-ndian C Copy byte 0 to byte 0, byte 1 to byte 1, etc. 0 in big-endian system is now different that 0 in little-endian system Little-ndian C es increasing upward Sequential s BACKUP Byte 0 Byte 1 Byte 2 Byte 3 addr Byte 3 Byte 2 Byte 1 Byte Sequential Review Sequential Review We've seen how to build basic combinational gates but what about sequential circuits We can build the bistables and latches we've seen at the gate level with direct CMOS substitutions Replace each NOR or AND gate with it's CMOS transistor level equivalent We can also take advantage of our circuit level understanding of transistors, capacitance, and sizing to build the bistables and latches in other (possibly more efficient) ways The simplest sequential cell is just a feedback loop of inverters Problem how do we change the value, Q?

16 An SR-Latch An SR-Latch We can use pass transistors to pull the output Q or Q' to a new value Note: φ is the CLK signals Vdd Vdd Consider the case when Q(t=0)=0 and we then apply the set input After a short time the pass transistor connected to S and the pull down transistor connected from Q to GND will be in linear mode and form a voltage divider Some analysis will show us that we must make (W/L) M6 > (W/L) M3 by some appropriate factor to get Q to switch Vdd Vdd R Φ M5 Q M2 M1 M4 Q M3 Φ M6 S R Φ Q=1 =0 V Q (t) =? Φ = 0->1 M6 S=1 GND GND GND M3 GND