Hierarchical Exact Symbolic Analysis of Large Analog Integrated Circuits By Symbolic Stamps

Transcription

1 Hierarchical Exact Symbolic Analysis of Large Analog Integrated ircuits By Symbolic Stamps Hui Xu, Guoyong Shi and Xiaopeng Li School of Microelectronics, Shanghai Jiao Tong Univ. Shanghai, hina

2 ontents Motivation and Background The Idea of Symbolic Stamp Implementation Experimental Results onclusion

3 Motivation

4 Small ase an be handled by existing exact symbolic analysis method VDD M8 M5 M7 Bias In- M1 P M In Out X Y Rz c L M3 M4 M

5 Large ase annot be handled by existing exact symbolic analysis method

6 Possible Application Graphical Sensitivity Analysis [16] Date [16] D. Ma, G. Shi, and A. Lee, A design platform for analog device size sensitivity analysis and visualization, in Proc. Asia Pacific onference on ircuits and Systems (APAS), Malaysia, Dec. 1 6

7 Motivation: Exact Analysis Many circuit characteristics (sensitivity, poles, zeros) require an exact symbolic expression of H(s). Exact symbolic analysis of large analog circuits ( ~5 MOSFETs) is not easy. Sensitivity Netlist Symbolic analysis engine H(s; p 1, p,...) Pole/Zero Optimization

8 Symbolic Analysis ons Pros

9 Representative Methods Algebraic Methods Determinant Decision Diagram [15] 1 R V s R R v v = to Matrix Algorithm Data R R 1 is vs Struct Graph-based Methods Graph Pair Decision Diagram [16] 1 R 1 1/R V s - V o to Graph Vs S Vc Algorithm Data Struct [15].-J. Shi and X.-D. Tan, anonical symbolic analysis of large analog circuits with determinant decision diagrams, IEEE Trans. on omputer-aided Design, vol. 19, no. 1, pp. 1-18, Jan.,. [16] G. Shi, W. hen and.-j. Shi, A Graph Reduction Approach to Symbolic ircuit Analysis, in Proc. Asia and South-Pacific Design Automation onference (ASPDA), Yokohama, Japan, pp. 197-, Jan.,

10 From Binary Tree to BDD Binary Tree f ( x, x, x) = xxx xxx xxx xxx [14] R. E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Trans. omput., vol. -37, pp , Aug.,

11 Reduced Ordered BDD anonical and ompact! Order: x1 > x > x f ( x, x, x) = xxx xxx xxx xxx f ( x, x, x ) = x x x x x x x [14] R. E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Trans. omput., vol. -37, pp , Aug.,

12 Determinant Decision Diagram Represent a determinant by BDD Treat Laplace Expansion as binary decisions 1 edge a a b c d e det( A) = f g h i j = adgj adhi aefj bcgj cbih edge d c g f b j i e h

13 Minor Sharing [5] g i d e f g h i j h a b c d e f g h i j b a d c c d f j g f b j i e e g h i j b f g h i j h 1 [5] G. Shi, A simple implementation of determinant decision diagram, in Proc. International onf. on omputer-aided Design (IAD), San Jose, A, USA, Nov. 1.

14 Graph Pair Reduction Diagram Represent the transfer function by BDD Treat Spanning-Tree Enumeration as binary decisions 1 R V s - V o R - x R

15 Graph Pair Sharing [16] 1 Vs 1/R S Vc 1 R 1 Vs Vs x R Vc R R R 1 R R - R 1 [16] G. Shi, W. hen, and.-j. R. Shi, A graph reduction approach to symbolic circuit analysis, in Proc. Asia South-Pacific Design Automation onference (ASPDA), Yokohama, Japan, Jan. 7, pp

16 Hash Mechanisms DDD By Hashing Minors Minor 1 Minor Minor 3 d e f g h i j b f g h i j g i h j GPDD By Hashing subgraphs Graph Pair 1 Graph Pair Graph Pair 3 R R R 1 R

17 Idea of Symbolic Stamp

18 Symbolic Stamp VDD M8 M5 M7 Bias In- M1 P M In Out X Y Rz c L M3 M4 M6 All MOSFETs use the same small-signal model! ircuits are naturally hierarchical!

19 Assembling Symbolic Stamps p p 1 p 1 A p p B p 1 n1 n n3 n4 n1 y y A A 11 1 B B A B A B n y y n3 y y n4 y y y y y y DDD Routine

20 Symbolic Stamp omputation i 1 i G = 1/R V 1 V - - y y y G G y1 y G G 11 1 = = y 11 y y 1 y 1 G G - 1 Four-root GPDD for R symbolic stamp

21 Why GPDD for symbolic stamp i 1 i G = 1/R V 1 V - GPDD Direct Link DDD n1 n n3 n4 n1 y y A A 11 1 B B A B A B n y y n3 y y n4 y y y y y y Indirect Link G S

22 Hierarchical Structure H(s) freq HYBRIDSIM Simulator MNA Matrix (DDD) Sub-circuit 1 Symbolic Stamp (Multi-root GPDD) Sub-circuit Symbolic Stamp (Multi-root GPDD) Sub-circuit 3 Symbolic Stamp (Multi-root GPDD) DEVIE DEVIE DEVIE

23 Experimental Results

24 Implementation Flow Will be integrated into our program in the future Netlist.Op (Now use HSPIE) Small Signal Model Extraction New Netlist Analog Design GUI H(s) freq H(; s p r ) Symbolic analysis engine

25 Platform Environment Programming Language and tools: Test cases are running on an AMD Athlon64.GHz processor with GB memory HSPIE 7 is used for D operating point analysis

26 Benchmark 1 A rail-to-rail Miller MOSFET amplifier containing 4 transistors

27 Benchmark A MOSFET operational amplifier containing 44 transistors [6] [6] T. Mconaghy and G. G. E. Gielen, Globally reliable variation-aware sizing of analog integrated circuits via response surfaces and structural homotopy, IEEE Trans. on omputer-aided Design of Integrated ircuits and Systems, vol. 8, no. 11, pp , Nov

28 Test Settings Partition Strategy MOSFET as a sub-circuit Maximize the sharing Small-signal Model SPIE LEVEL 3 [3] [3] A. Vladimirescu and S. Liu, The simulation of MOS integrated circuits using SPIE, EES Department, University of alifornia, Berkeley, Tech. Rep. UB/ERL M8/7,

29 Performance Summary Op-amp ircuit #Device (T) #Symb for GPDD #Symb for DDD MNA Matrix Size GPDD (vertices) DDD (vertices) Time (sec.) Memory (MB) ase x , ase x , Remarks Both DDD-based (newly implemented [5] ) and GPDD-based nonhierarchical simulator [16] cannot handle these two circuits. [16] G. Shi, W. hen, and.-j. R. Shi, A graph reduction approach to symbolic circuit analysis, in Proc. Asia South-Pacific Design Automation onference (ASPDA), Yokohama, Japan, Jan. 7, pp [5] G. Shi, A simple implementation of determinant decision diagram, in Proc. International onf. on omputer-aided Design (IAD), San Jose, A, USA, Nov

30 onclusion Proposed a symbolic stamp approach to hierarchical analysis Investigated an efficient implementation Improved the capacity for exact analysis More applications for design optimization in the future

31 Thanks Q & A