Real-Time Dynamic Energy Management on MPSoCs

Transcription

1 Real-Time Dynamic Energy Management on MPSoCs Tohru Ishihara Graduate School of Informatics, Kyoto University 2013/03/27 University of Bristol on Energy-Aware COmputing (EACO) Workshop 1

2 Background Low Power / Low Energy Growth of portable electronics market Peak Performance Growth of real-time applications Scalability and adaptability Reducing the average energy without losing the peak performance Real-time DVFS on a multi-core processor 2

3 DVFS Processor Processor can dynamically change its clock frequency Programmers can specify the clock frequency using an I/O instruction The operating voltage is adjusted to the minimum value which guarantees correct operations of the processor Program RAM addi r1,r2,#1 switch to 100MHz Beqz r1,#-128 code decode Power status reg. data Data RAM Power Supply DC-DC converter VCO clock voltage T. Ishihara and H. Yasuura, Voltage Scheduling Problem for Dynamically Variable Voltage Processor, in Proc. of ISLPED 98, pp , Aug.,

4 DVFS Pros and Cons Pros Quadratic reduction of energy consumption Cons Low performance at low operating voltage Large overhead of DC-DC converter t TRAN E TRAN 2C V V IMAX (1 ) C V This prevents real-time control of DVFS processors DD1 DD2 V 2 2 DD1 DD2 Typically 0.9 T. Burd and R. Brodersen, Design Issues for Dynamic Voltage Scaling, ISLPED C=100μF I MAX =1A V DD1 =1.0 V DD2 =0.68 t TRAN =64μs, E TRAN =4.6μJ 4

5 Multi-Performance Processor (1/2) PEs have the same ISA Differ in their clock speeds and energy consumptions A single PE is activated at a time (exclusive) Dedicated Bus PE1 High Speed PE2 Middle PE3 Low Energy Internal register values are transferred through a dedicated bus or a stack located in a data RAM before switching PEs Not an ILP processor nor a multi-core processor I-cache Program RAM Data RAM memory Cache ways activated can be specified by program T. Ishihara, et al. AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications, Proc. of IEEE Symposium on Application Specific Processors, pp.83-88, July,

6 Multi-Performance Processor (2/2) Inter MPU cores: multiple MPU cores run concurrently Intra MPU core: a single PE core runs alternatively PE core PE core PE core MPU cores L1-cache No data migration is needed when a PE-core switches L2 cache No bus arbitration is needed No multi-port RAM is needed 6

7 Overview of Prototype Based on Media embedded Processor (MeP) originally developed by Toshiba Designed with commercial 90nm process technology 7

8 Synthesis Flow Characterize cells using different voltages 1.0V, 0.75V, 0.72V, 0.7V, 0.68V, 0.55V, 0.52V, 0.5V Find clock frequency of H-PE 200MHz with 1.0V Find bus clock frequency 66MHz which is a quotient of 200MHz Find clock speed and V DD of L-PE 66MHz@0.52V which minimizes the energy of L-PE Find clock speed and V DD of M-PE 133MHz@0.68V which minimizes the energy of M-PE 8

9 Comparison with DVFS (1/2) Ours 15 GP registers are transferred through stack 16 SP registers are transferred through dedicated bus The other registers like pipeline registers are flushed Commercial DVFS processor Dedicated Bus Transition time 1μs Energy overhead 13nJ Level converter Level converter L-PE 67MHz 0.52V M-PE 133MHz 0.68V H-PE 200MHz 1.00V Level converter Level converter Stack (scratchpad memory) Processor RTOS Transition time AMD Mobile K6 [1] PowerNow! 200 μsec StrongARM SA-2 [2] Embedded Linux 150 μsec Transmeta Crusoe [3] LongRun > 20 μsec ~10 μj energy overhead is involved [1] AMD, AMD PowerNow! Technology Dynamically Manages Power and Performance [2] Compaq ipaq H3600 hardware design specification ver.0.2f, [3] M. Fleischmann, Reducing x86 operating power through LongRun IEEE 12 th Hot Chips Symposium, August 15,

10 Comparison with DVFS (2/2) Extract a critical path from our 1.0V design Measure the delay of the path using HSPICE for different operating voltages Performance of low voltage operation is not very good DVFS Processor 35% energy reduction!! Our Processor 31% energy reduction!! 10

11 MPP Pros and Cons Pros Low transition overhead Two orders of magnitude less than that of DVS Higher performance at low operating voltage Each PE core is optimized for the target supply voltage Cons Large area overhead Limited number of clock speeds Memory H-PE M-PE DC-DC DC-DC Need multiple voltage sources 11

12 Power Results of MPEG2 encode Original 1.0V/200MHz 0.68V/133MHz 0.52V/67MHz Stack is placed in the data scratchpad memory HW configuration is fixed before entering the main routine 12

13 Energy and Execution Time 2x energy scalability 13

14 Application of DVFS Processor Motivation Most tasks complete much earlier than their WCET Approach (for periodical tasks only) Divide a 1-frame video encoding task into 33 slices Exploit slack time of previous slices in the current slice Application 66.67ms Frame1 Frame2 Frame15 Slice 1 Slice 2 Slice ms WCET TS1 TS2 TS3 TS33 0.5ms for transition slices S. Lee and T. Sakurai, Run-time voltage hopping for low-power real-time systems, in Proc. Asia South Pacific Design Automation Conference., Jan. 2000, pp

15 Experiments Overheads 26μs 164nJ DC-DC & VCO H-PE DVFS VDD F DVFS Processor 34mW@200MHz 18mW@133MHz T. Burd and R. Brodersen, Design Issues for Dynamic Voltage Scaling, ISLPED MPP (ours) Overheads 1μs,13nJ Shared local-memory M-PE 14mW@133MHz Normalized Energy Orig ḊVFSMPP [ms] Average execution time for each slice 15

16 Layout Image of MPU-core1 Designed with commercial 90nm CMOS technology ISPM DSPM D-SPM 0.62mm % I-SPM 0.40mm 2 9.5% Selective-Way Cache H-PE Level shifters M-PE I-Cache 0.74mm % High-end PE 0.19mm 2 4.5% Middle-end PE 0.21mm 2 5.0% Others 2.07mm % Total 4.23mm 2 100% 16

17 Summary Small overhead compared with DVFS Transition time: 100x smaller Transition Energy: 1000x smaller More energy efficient at low voltage Clock frequency: 30% more efficient Large area overhead ~25% area overhead 17

18 WIP and Future Work Goal : Reducing average energy with keeping the peak performance Optimization at every design hierarchy Cell optimization for near-threshold voltage Pipeline optimization for low-voltage Simultaneous optimization of V DD and V th Architecture optimization How many big/little cores? How big and how little? How to switch the cores? By RTOS or autonomously without RTOS? 18