3D Memory Formed of Unrepairable Memory Dice and Spare Layer

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1 3D Memory Formed of Unrepairable Memory Dice and Spare Layer Donghyun Han, Hayoug Lee, Seungtaek Lee, Minho Moon and Sungho Kang, Senior Member, IEEE Dept. Electrical and Electronics Engineering Yonsei University Seoul, Korea {tommyhan95; yseehy214; tegi98; and Abstract With the development of memory manufacturing technology, the density of memory die has been increased and more data can be stored in a small area than before. However, due to the complexity of the manufacturing process, faults in memory have increased. And it leads to poor yield and quality of memory. To improve yield and quality of the memory, the importance of memory test and repair is growing to maintain memory productivity. This paper presents solutions for test and repair in pre-bond. In the pre-bond, proposed method makes a new 3D stacked memory by using unrepairable memory dice which cannot be repaired with existing spare memories. Discard the bank with the largest number of faults in the unrepairable memory die and repair the remaining banks. The memory dice and a spare layer which made of the known good die or unrepairable memory die are stacked to create a 3D memory. A bank of the spare layer is mapped to discarded bank of unrepairable memory die to operate as one normal working memory die. The proposed method can lead to high yields of 3D stacked memory. Keywords memory repair, redundancy analysis, ATE, prebond repair, 3D memory, test and repair, yield improvement I. INTRODUCTION With advances in manufacturing technology, the size of memory cells has been gradually decreased, and capacity and density in 2D memory cells have been increased. As 2D memory technology reaches its limit in memory integration, the 3D stacking memory technology using through silicon vias (TSVs) has been suggested as an alternative. As a result, the development of memory chips has been evolved into the 3D embedded on-chip memory. High bandwidth, low power consumption, and reduced length of interconnection to allow less delay are enabled by the connection between memory layers using TSVs [1]-[2]. However, the development of such production techniques has increased the possibility of faulty cells in the memory. Quality and productivity of memory have been dropped due to faulty cells. Maintaining high quality and productivity has become the most important challenge in memory mass-production. As a result, effective test and repair methods for memory have been required [3]- [5]. There are two types of test and repair processes in 3D This research was supported by the MOTIE (Ministry of Trade, Industry & Energy ( ) and KSRC (Korea Semiconductor Research Consortium) support program for developing future semiconductor devices D. Han, H. Lee, S. Lee and M. Moon are with the Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul , South Korea ( {tommyhan95; yseehy214; tegi98; S. Kang (corresponding author) is associated with the Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seodaemoon-Gu Yonsei-Ro 50, Seoul , Korea. ( shkang@yonsei.ac.kr). stacked memory. First, there is a pre-bond test and a repair process. The pre-bond test and repair processes proceed before the 2D memories made on the wafer are stacked in 3D memory. Pre-bond testing is done through the automatic test equipment (ATE). The ATE finds faulty cells on memory dice and creates repair solutions by analyzing fault data. The memory dice are repaired by the solution which uses spare cells for pre-bond repair. In this process, memory dice are classified as repairable memory dice or unrepairable memory dice. The memory that can be repaired with spare cells which can be used in the pre-bond repair process is called known good die (KGD). KGDs are stacked to make 3D memory [6]. The post-bond test and repair process is performed using the ATE and built-in self-repair (BISR) after the memory layers are stacked. The BISR located on the base die consists of a built-in self-test (BIST) module and a built-in redundancy analysis (BIRA) module. The addresses of the faulty cells are identified through the test patterns created by the BIST module. The addresses of the faulty cells are collected by BIRA and it uses this data to generate the repair solution. The solution is generated by an analyzer designed according to a given algorithm. And the faulty cells are repaired according to the solution. Unlike the post-bond process, which allows a variety of spare memory structures, most of the pre-bond process uses 2D spare architecture. Many algorithms have been studied for efficient use of a 2D spare architecture consisting of spare rows and spare columns [7]-[9]. Representative examples include comprehensive real-time exhaustive search test and analysis (CREASTA), which finds possible solutions quickly with parallel sub-analyzers [8], and Branch algorithm that use Branch analyzers to achieve fast analysis time, optimal repair rate, and low hardware overhead [9]. However, unlike 2D spare architecture, the proposed scheme is to repair the faulty cells found in the pre-bond through the spare layer after stacking. In this paper, a new scheme for pre-bond test and repair processes are proposed. This scheme consists of the hardware structure using a spare layer and a method of selecting a memory die to be used. Through this scheme, it is possible to improve the yield of 3D memory by making stacked memories using memory dice that are not previously available. This paper is organized as follows. Section 2 discusses the background information to help understand of this paper. Section 3 describes in detail of the proposed scheme. Experimental results are analyzed in Section 4. Conclusions of this paper are given in section 5. XXX-X-XXXX-XXXX-X/XX/$XX.00 20XX IEEE

(a) Fig. 1. Example of 3D memory with proposed scheme. II. BACKGROUNDS A. 3D Memory Architectrue The 3D memory consists of the base die and memory dice.

The memory dice and the base die are connected by TSVs, which send the addresses and data needed for memory operation.

There are three ways to stack 3D memory: wafer-to-wafer (W2W), die-to-wafer (D2W), and die-to-die(d2d).

2 (a) Fig. 1. Example of 3D memory with proposed scheme. II. BACKGROUNDS A. 3D Memory Architectrue The 3D memory consists of the base die and memory dice. The base die contains the logic circuits necessary for memory operation. The memory dice are stacked vertically on the base die. The memory dice and the base die are connected by TSVs, which send the addresses and data needed for memory operation. After the memory die is produced on the wafer, it is determined whether it is a repairable memory die or an unrepairable memory die in an ongoing pre-bond test. There are three ways to stack 3D memory: wafer-to-wafer (W2W), die-to-wafer (D2W), and die-to-die(d2d). The W2W method is a method in which wafers are piled directly on each other, which is inefficient because there are restrictions on the use of pre-bond test results. However, the D2W or D2D method is efficient because it can be stacked using only repairable dice as a result of the pre-bond test. As a result, the yield of the 3D stacked memory is affected by the stacking method [10]. After stacking, the post-bond test finds additional faults in the memory. Based on the test result, it is judged by using the RA algorithm whether the 3D memory is available through the repair. B. Classification of Faults Most of the memory that is produced adopts the 2D spare architecture. The 2D spare architecture has a spare row line and a spare column line, and follows the line replacement policy. Since resources for memory repair are limited, algorithms have been studied to efficiently replace faulty cells using spare lines. For this study, the faults are divided into three types. They are single fault, spare line fault, and must-repair fault. 1) Single fault: A single fault does not share row or column address with other faults. 2) Spare line fault: The number of faults in the same row is greater than one but less than or equal to Cs, or the number of faults in the same column is greater than one but less than or equal to Rs. These faults can be repaired by both row and column spares. (b) Fig. 2. Examples of repairable judgement after fault collection. (a) In conventional memory die selecting method. (b) In proposed memory die selecting method 3) Must-repair fault: Faults that are subject to a must-re pair condition are that the number of faults in the same row exceeds Cs, or the number of faults in the same column exceeds Rs. They cannot be repaired by row spare and column spare, respectively. III. PROPOSED SCHEME The memory die selecting method and the hardware structure are presented through the test and repair process, and in-memory process of the incoming memory cell addresses will be explained. In the proposed scheme, there are two kinds of memory stacked to make 3D stacked memory. The first, unrepairable memory dice, which cannot be repaired by spare cells for the pre-bond repair process. If a bank with the most faults in the unrepairable memory is discarded, there are some memories that can be repaired among them. Unrepairable memories that meet the above conditions are used in this scheme and called selected memory dice. Second, KGD or selected memory die is used as a spare layer. The spare layer only needs to have more banks than the number of memory layers of the 3D stacked memory. Unused banks of memory layers are replaced by muxing the banks of the spare layer. The fuse structure on the base die exists to implement the mapping information that the bank of the spare memory and the bank of the memory layer. Fig. 1. is an example of a 4-layer 3D stacked memory with the proposed scheme applied. Each memory layer consists of four banks, and unused bank areas are marked in red. It is indicated that this area has been replaced

3 are accumulated in the bank 0. In the picture, it is marked with red area. If the repairability is judged again, there is one line fault and one single fault and it is possible to repair. ATE repairs the memory die using the repair solution that was created. In the past, the memory that was discarded became a memory that operates normally except for one bank. The selected memory dice thus formed are stacked with the spare layer, which is repaired in the first judgment process or became a memory that operates normally except for one bank, to form a 3D memory. In order for the unrepairable memory die to be used as a spare layer, the number of banks to be operated on the memory die must be same or more than the number of layers in 3D memory. The information of the discarded bank on each memory die and the bank information of the spare memory to replace the discarded bank are stored in fuse structure located on the base die, respectively. Fig. 3. Judging process for the incoming memory cell address in the proposed scheme. by the banks of the spare layer. This mapping data is recorded in the fuse structure which is located on the base die in addition to the logic circuit for memory operation. A. Test and Repair Processes Most of the memories in the pre-bond test process use ATE. At ATE, the test pattern is applied to the memory dice, and based on this, the addresses of the faulty memory cells are received. By checking several bits from the MSB in each of the row and column addresses of the faulty memory cell, it is possible to check which bank has the faulty cell located. At ATE, the bank and bank-by-bank count of the failed memory cell are processed along with the existing test procedure. After the fault collection, the ATE determines the repairability of the memory die based on the algorithm and the collection data. First, the repairable KGD is judged and repaired with the spare cells prepared for pre-bond repair. Here, it is determined again whether the memories are determined to be unrepairable or not. Using the information counted during the fault collection process, it discards the bank with the most faults per memory die. The repair algorithm is applied to the memory that one bank is discarded for determine repairability. When the memory dies determined to be repairable, they are repaired according to the solution made. In this paper, these memory dice are called selected memory dice. Fig. 2. (a) shows the first judgment process. As a result of fault collection, this memory with two line faults and one single fault is not repairable. In the existing pre-bond test process, the above memory is discarded. In fig. 2. (b), the second judgment process is shown. This memory die was judged unrepairable in the first judgement situation. However, after removing one of the memory banks, it can be repaired. Since it is a memory die using four banks, it is possible to check the bank information in which the fault cells are located by checking the MSB of each row and column of the faulty cell address. As a result of the fault collection, the largest number of faults B. In-memory Process of the Incoming Address While the 3D memory transferred to the user is operating, a read/write operation is performed on the memory cells. 3D memory made in proposed scheme must judge whether the incoming address should be forwarded to the memory layer or to the spare layer. In fig. 3., the judging process of the proposed scheme which determines whether the incoming address is replaced or not is shown. The memory receives read/write operation and address information for operation and information to be written in the write operation. Address is internally decoded in memory and represented as layers, rows, and columns. The decoded address information is transmitted to the fuse structure to determine whether the address corresponds to the replaced bank or not. If it is replaced, the address is changed to fused address and the memory cell of the replaced bank operates. If not, the decoded address is transferred directly to the memory die for operation. In fig. 4. mapping data which is implemented by fuse structure of fig. 1. is shown. On the left side of matching data in fig. 1. is the address of the discarded bank on the memory dice, and on the right side of matching data figure is the address of the bank to be used in the spare layer instead of the discarded bank. Since it discards one bank for each memory layer, it is the information of memory layer 0 to 3 from the top. Fig. 4. (a), the memory cell of memory layer 1 is requested. Since four bank memory die is used in fig. 1., the MSB of the row and column are checked to see which bank the address is located in. The MSB of the incoming row address is 1, and the MSB of the column address is 0. As a result of the comparison with the mapping data, the corresponding bank was replaced by bank 1 of the spare layer. The spare layer is operated and the MSB of the row and column at the incoming address is changed by fusing. Other addresses than the MSB are not touched so that addresses can be mapped in the replaced bank. In fig. 4. (b), the address for memory die 3 came in. As a result of comparing the MSB of the row and the column with the data of the fourth row of the mapping data, the decoded address is transferred to the memory die as it is because the bank is not replaced. Through the above process, each layer does not have one bank, but the user recognizes and uses it as normal memory dice and it works like other 3D memory.

(a) (b) Fig. 4. Internal fusing process of memory cell address. (a) Address changed by fuse structure. (b) Address does not correspond to the discarded bank. IV.

4 (a) (b) Fig. 4. Internal fusing process of memory cell address. (a) Address changed by fuse structure. (b) Address does not correspond to the discarded bank. IV. EXPERIOMENTAL RESULTS The experiment assumed 10,000 3D stacked memories. One memory is stacked in four layers with 1,024 x 1,024 bit memory dice. If use the suggestion idea, five layers including the spare layer have been set up. In the experiment, the yield of the entire memory is measured by varying the number of faults present in one memory die in the pre-bond situation. The faults are randomly distributed, using the Polar- Eisenberg distribution in this process. The Polar-Eisenberg distribution is a widely used fault model for measuring integrated circuit yield [11]-[12]. The experiment assumes that each memory die has one and two spare columns and spare rows for pre-bond, respectively. In each case, a case where a general pre-bond repair was performed, a proposed idea was applied to 4 banks, and a case where the proposed idea was applied to 16 banks have experimented. The number of faults in the memory die varied from 1 to 10. Table 1 shows the experimental results. The yields of the existing structures without the proposed idea are shown in the first and fourth lines of the table. It can be seen that the lowest yield is obtained in each assumed case. If the memory die consists of 4 banks, it is shown in the second and fifth lines. The point where the existing structure and yield are 100% is the same, but it can be confirmed that the yield of other situations is higher. If Rs and Cs are each 1, larger than the number of faults per memory die is 7, the yield is same with the existing structure. This is because, in case of 4 bank, spare layer must be formed of KGD. The KGD is needed to make the proposed structure. If a number of faults are more than 8, KGD no longer exists. If the memory die consists of 16 banks, it will appear in lines 3 and 6 of the table. When Rs and Cs are each 1, the yield is the higher than 4 bank case. Because if 16 banks, unrepairable memory dice can be used for the spare layer as well as KGDs. However, when the number of faults per memory die is 6, the yield is lower than 4 banks memory die. This is because, when the number of banks of the memory die increases, the area per one bank becomes smaller, and the number of faults disappearing when one bank is not used is decreased on average. In this case, the absolute number of memories without one bank of the 4 bank case is much larger than that of the 16 bank case. From the experiments, it is confirmed that the yields are much higher than the conventional method. In addition, When the number of banks is larger than the number of memory layers, it can be used as a spare layer and a higher yield is obtained. V. CONCULSION In this paper, a scheme for creating 3D memory using memory dies that were previously unavailable through a simple additional structure is proposed and its method for TABLE I. REPAIR RATES IN VARIOUS SITUATIONS

5 operation is proposed. In the test process, the banks of the faulty cells are checked to find a repairable memory by removing one bank. These memories are stacked together with a spare memory which is made of KGD or selected memory die to construct a 3D memory. The address of the removed bank and its replacement bank data is implemented by the fuse structure on the base die. After checking that the address entered in the operation process is located in the replaced bank, if it is replaced, the address is newly routed in the memory so as to operate as normal memory. Experimental results show that the yield is much higher than that of conventional memory in any case. REFERENCES [1] W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, et al., Demystifying 3-D ICs: The pros and cons of going vertical, IEEE Design Test Comput., vol. 22, no. 6, pp , Nov./Dec [2] Y. Xie, Processor architecture design using 3D integration technology, in Proc. Int. Conf. VLSI Design, 201 0, pp [3] H. H. S. Lee and K. Chakrabarty, Test challenges for 3D integrated circuits, IEEE Design Test Comput., vol. 26, no. 5, pp , Sep./Dec [4] B. Noia and K. Chakrabarty Testing and design-for-testability techniques for 3D integrated circuits, in Proc. Asian Test Symp., 2011, pp [5] S.-K. Lu, C.-W. Wu, and J.-F. Li, On test and repair of 3D random access memory, in Proc. IEEE Asia South Pacific Design Autom. Conf., pp , Jan./Feb [6] C. Dislis and I. P. Jalowiecki, Economics modeling for the determination of optimal known good die strategies, in Proc. IEEE Multi-Chip Module Conf., pp. 8 13, Jan./Feb [7] C. Oh, S. Kim, and J. Yang, BIRA With Optimal Repair Rate Using Fault-Free Memory Region for Area Reduction, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 12, pp , Dec [8] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, A built-in self repair analyzer (CRESTA) for embedded DRAMs, in Proc. Int. Test Conf., Oct. 2000, pp [9] W. Jeong, J. Lee, T. Han, K. Lee, and S. Kang, An advanced BIRA for memories with an optimal repair rate and fast analysis speed using a branch analyzer, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 12, pp , Dec [10] C.-W. Wu, S.-K. Lu and J.-F. Li, On test and repair of 3D random access memory, in Proc. IEEE Asia and South Pacific Design Automation Conference., Jan./Feb. 2012, pp [11] C. H. Stapper, On a composite model to the IC yield problem, IEEE J. Solid-State Circuits, vol. 10, no. 6, pp , Dec [12] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, A simulator for evaluating redundancy analysis algorithm of repairable embedded memories, in Proc. 8th IEEE Int. On-Line Testing Workshop, Jul. 2002, pp

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