Use of Symbolic Performance Models in Layout-Inclusive Synthesis of RF Low-Noise Amplifiers

Transcription

1 Use of Symbolic Performance Models in Layout-Inclusive Synthesis of RF Low-Noise Amplifiers Mukesh Ranjan, Amitava Bhaduri, Ranga Vemuri University of Cincinnati, Cincinnati, Ohio, USA. Wim Verhaegen, Georges Gielen Katholieke Universiteit Leuven, Leuven, Belgium. Bhaskar Mukherjee, Andrea Pacelli State University of New York, Stony Brook, USA.

2 Outline Introduction & Motivation Proposed Circuit Synthesis Approach Layout Generation & Extraction Post-Processing Symbolic Performance Modeling Inclusion of Layout Effects Experimental Results Conclusions 2

3 Analog/RF Circuit Synthesis Circuit Topology Search Range for each circuit parameter Cost Function Optimization Engine Algos : Simulated Annealing, Genetic Algorithms etc. Sizes : Values of circuit parameters, like W, L, R, C etc. Optimization Engine Cost Cost Function Evaluator Numerical Simulator : Berkeley SPICE, HSpice, Spectre, Eldo, variants of Spice etc. Sizes Performance Estimates Control Block : Different Analyses, like, DC, AC, Transient, Distortion, Noise etc. Numerical Simulator Simulation Results Performance Evaluator Performance Models : Methods to use simulation results & generate numerical values of performance parameters Control Block Performance Models Performance Estimates : Circuit characteristics like, S-parameters, CMRR, Open-loop Gain, Phase Margin etc. HD2, HD3, IM3, IIP3 3

4 Motivation Traditional Circuit Synthesis Computationally expensive performance estimation due to numerical simulator Parasitics unaware / partially aware, leads to failure of synthesized circuit after layout. Our method Performance estimation using Symbolic Performance Models (SPMs). Layout-Inclusion in Synthesis Loop using Module Specification Language (MSL). Quasi-static extraction of on-chip inductances and interconnects. Rule based extraction of active devices and parasitic capacitances. 4

5 Proposed Circuit Synthesis Approach

6 Definitions Layout-Inclusive Synthesis Layout generation & extraction done in synthesis loop Also known as Layout-in-Loop approach Symbolic Performance Models Symbolic equations in terms of circuit parameters Built using transfer functions obtained by symbolic analysis. Represent the characteristics of analog circuit SPMs used for repetitive performance estimation 6

7 Proposed Approach Optimization Engine SPM Evaluation Layout Instantiation Numerical Analysis 3-Way Extraction Post- Processing MSL System SPM Generation 7

8 Layout Generation and Extraction

9 Layout Generation: MSL System Parameterized Module Library (specified in MSL) New Module Definition (specified in the Module Specification Language) MSL Compilation & Code Generation New Parameterized Layout (as editable C++ code) Layout Editor Adaptation & Compilation Parameterized Layout Generator Routing Layer Map Layout Elaboration Parameter Values Physical Layout 9

10 Illustration of 3-Way Extraction d1 d2 g1 b1 g2 b2 s1 Extraction 1 s2 d3 n2 n4 g3 s3 b3 n1 s2 n5 r1 vdd r2 g1 s1 d1 b1 g2 d2 b2 s2 n2 n4 gnd Extraction 2 n1 n5 d3 g3 b3 s3 Merged netlist Extraction 3 gnd 10

11 Post-Processing of Extracted Netlist

12 Netlist Sorting & Compaction Netlist extracted by VPEC VRL segments for each net-segment & via. Nets jumbled up, no definite order for extracted segments. Need to be arranged according to nets for proper extraction of parasitic values Explosion in number of circuit. Creates a problem due to size limitation on symbolic analysis. The more the number of segment more difficult it is to create a general inclusion model. Voltages sources unwanted; hence removed. Several elements in series merged Power nodes & terminal nodes of modules are preserved. Stored as graph for easy generation of extracted netlist and correct extraction of parasitic values for plugging into the SPMs 12

13 Symbolic Performance Modeling

14 Framework Input, Output & Power Nodes Generic Parasitic Models Inclusive Circuit Topology Small-Signal Models Combination of Nodes Node Information Generator Expansion Module Expanded Circuit List of Performance Parameters Symbolic Model Builder Symbolic Analysis Engine Performance Models Compilation Symbolic Transfer Functions Compiled Library of Symbolic Performance Models 14

15 Symbolic Analysis Core of SPM generation is Symbolic Analysis Symbolic Analysis: Formal technique to obtain transfer functions. Transfer Function in term of: symbolic circuit parameters independent variables like frequency Element Coefficient Diagrams (ECDs) Represent the transfer functions. Fast to evaluate Easy to store in the s-polynomial format Require low memory No approximation 15

16 Element Coefficient Diagrams Evaluate ECD (SSV) v1 = 1; v6_0 = -1*v1; v10_0 = 1*v6_0; v9_0 = -SSV.gm_m1 * v10_0; v8_0 = 1*v9_0; v9_1 = SSV.cgd_m1 * v10_0; v8_1 = 1*v9_1; v5_0 = 1*v6_0; v4_0 = -SSV.g_rds_m1*v5_0 + -SSV.g_rd *v5_0; v3_0 = -1*v4_0; v4_1 = -SSV.cgd m1*v5_0 + -SSV.cbd m1*v5_0; v3_1 = -1*v4_1; numer_0 = - input * v8_0; numer_1 = - input * v8_1; denom_0 = 1*v3 0; denom_1 = 1*v3 1; end Evaluate ECD Compiled denom numer denom_0 denom_1 numer_0 numer_1 v3 1-1 v8 - input 1 v3_0 1-1 v3_1 1-1 v8_0 input 1 v8_1 input 1 v4 -g_rds_m1 -s*cgd_m1 -s*cbd_m1 g_rd v3 v9 -g_m1 s*cgd_m1 v10 -g_rds_m1 v4_0 -g_rd -cgd_m1 v5_0 v4_1 -cbd_m1 v9_0 -g_m1 v10_0 v9_1 cgd_m1 Determinant Decision Diagram (DDD) -1-1 v6 v1 1 Element- Coefficient Diagram (ECD) -1-1 v6_0 v1 1 16

17 SPM for Noise Figure Similar to technique proposed by Tan et. al. Noise Figure = Total Output Noise/ Part of the Output Noise due to the Source resistance All noise sources are independent of each other Total output noise is the sum of noise at the output from each individual noise source Each noise source considered as sinusoidal current generator with rms value equal to rms value of noise current source Contribution of each noise source obtained as a transfer function and then combined. 17

18 SPM for Distortion Modules Volterra Series based method proposed by Wambacq et. al. Non-Linear Circuit elements described as a truncated Taylor Series Circuit is decomposed into a number of circuits, each of which model the behavior at a frequency which is a linear combination of input frequencies. Each non-linearity is modeled by a non-linear current source and a linearized element Linear Transfer functions are generated for each circuit and stored as ECDs SPM is a function which combines the linear transfer functions and non-linearity coeffcients 18

19 Inclusion of Layout Effects

20 Why Include Layout Effects in SPMs? Circuit topology input to SPM generator modified to include layouts effects. Sizes Layout Instantiation Performance Parameters Symbolic Performance Evaluator Compiled Symbolic Performance Models Symbolic Performance Model Generator Physical Layout Extraction Parasites Inclusive Netlist Parasitic Values a) Set of parasites may vary between iterations b) Number of fingers in a transistor may vary between iterations. SPMs should capture these variations, i.e., should be valid for entire design space 20

21 VPEC: Extraction Technique A1 A1 A2 Vertical & horizontal segment connector (V,L) A2 The interconnect structures are of small electrical length, hence in the frequency range of 1-4 GHz, PEEC model is considered. 21

22 Illustration of Parasitic Inclusion Five possible cases for a 3-Terminal net and its complete parasitic model in the center, which is included in the circuit topology used to generate the SPMs. Based on good channel routing & complete extraction of PEEC Model 22

23 Experimental Results 23

24 Benchmark Setup vdd M0.W = M1.W; Enables merging drain of M0 with source of M1; Reduces internal noise of cascode transistor M1 & facilitates input matching. Vdd vdd! V0 + Vdc=3.3V gnd c=10pf C1 r=50 PORT0 R1 R0 M2 L1 L2 M0 M1. L0 C0 r=50 PORT1 M0.W = 0.1 * M1.W (M0 forms a current mirror with M1); Minimizes power consumption in bias circuit. Large input blocking capacitance is off-chip; Fixed at 10pF. SA-based optimizer explores search space for design variables: M1.W, L0, L1, L2, R0, R1 and C0. TSMC 0.18µ technology; All simulations run on SunBlade1000 with 2GB RAM. 24

25 Synthesis Results & Accuracy 20 Synthesis Results & Accuracy Value (db) Gain NF H2 H3 Attributes Constraints Obtained Verified Attribute Constraints Obtained Verified Error Gain > % NF > % H2 < H3 < Frequency = 2.1 GHz 25

26 Time Results Time (seconds) SPM Generation Time ECD Gen. ECD Compile Misc Total SPM Gen Total Number of ECDs = 49 A0= 1 NF = 8 H2 = 9 H3 = 31 Per Iteration Time Time (seconds) Layout Gen. Layout Ext. Perf. Estimation Total Iteration Total Synthesis Time ~13 hours # of Iterations ~

27 Conclusions 27

28 Contributions Conclusions Use of SPMs in Layout-Inclusive RF LNA Synthesis Compilation of ECDs for faster evaluation Use of MSL for layout generation and evaluation Parasitic Inclusion techniques for high frequency effects Future Work Development of SPMs for Intermodulation Model equations for non-linearity coefficients 28