A look at interrupts Dispatch_Tasks ( )

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Sybil Horton
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1 SHOWS WHERE S FIT IN A look at interrupts Dispatch_Tasks ( ) What are interrupts and why are they needed in an embedded system? Equally as important how are these ideas handled on the Blackfin Assignment 2 Assignment 1 Coffeepot on interrupts Current Code Init_Coffeepot( ) While (device_not ) { UpdateSimulator software update } check device is ; // And you always know when that // will happen at a certain place in // you code so the simulation // unlikely to find real le timing errors New code Init_Coffeepot( ); Stop_CoreTimer_Interrupt( ); SetUp_CoreTimer_Interrupts( hardware update); Start_CoreTimer_Interrupt( ); While (device_not ) { // Hidden background interrupt service routine // The more realistically makes the coffeepot // update out of synchronism with your software // More like real like } check ; +3 / 5V The standard instruction cycle of a microprocessor (ENCM369) * CAUSES INSTR PHASE 1 FROM PROGRAM INSTR PHASE 4 RESULT * INSTR PHASE 2 DECODE AND Y VALUES INSTR PHASE 3 EXECUTE +3 / 5V RC time constant 200 ms on 68K GROUND

2 The standard instruction cycle * EXECUTING YOUR PROGRAM UNTIL POWER IS REMOVED INSTR PHASE 1 FROM PROGRAM INSTR PHASE 4 RESULT INSTR PHASE 2 DECODE AND Y VALUES INSTR PHASE 3 EXECUTE The standard instruction cycle with external device having important data * INSTR PHASE 1 FROM PROGRAM INSTR PHASE 4 RESULT This is the data Control signal Thanks has received data INSTR PHASE 2 DECODE AND Y VALUES INSTR PHASE 3 EXECUTE Control signal I have data for you The standard instruction cycle with external device having important data * FETCH WRITE-BACK This is the data DECODE EXECUTE Control signal Thanks has received data Control signal I have data for you device The wait till approach of reading data from external device In decode phase read control register value In execute phase check 1 -- keep waiting (fetch-decode-execute-writeback instruction cycle) until the control value changes from 0 (device not ) to 1 (device ) When 1 go to a dferent part of your program code to read the data e.g. call ReadData( ) Then your program must send an acknowledge back to device that the data has been read. e.g. call AcknowledgeReadData( ). The device can then go and get more values for you. PROBLEM: You have no time to do anything else other than wait Not a problem waiting for this device is the only thing you want to do with the processor

3 Wait till approach Very problematic many devices * WAITS TOO LONG INSTR PHASE 1 FROM PROGRAM INSTR PHASE 4 RESULT INSTR PHASE 2 DECODE AND Y VALUES INSTR PHASE 3 EXECUTE 16- The Poll approach of getting data Not much waiting but a lot of doing read control register value of device go to a dferent part of the code to read the data (ReadData1( ) ) after reading the data send an acknowledge signal back to device 1 (AcknowledgeReadData1( ) ) -- 0 go and read the control value of device 2 don t worry about device 1 for some time read control register value of device go to a dferent part of the code to read the data (ReadData2() ) after reading the data send an acknowledge signal back to device 2 (AcknowledgeReadData2( ) ) -- 0 go and read the control value of device 3 don t worry about device 2 and 3 for some time ETC PROBLEM: What happens, while you are handling device 2, device 1 has time sensitive information that will disappear device 1 is not serviced immediately Interrupt Approach basic idea Extra phase in instruction cycle * Acknowledge Request done NO PHASE ANY- TIME PHASE 1 FROM NORMAL (NOT ) PROGRAM PHASE 4 ANSWER BECOMES REQUEST PHASE 2 DECODE AND Y VALUES PHASE 3 EXECUTE data These issues MUST be solved using interrupts on ANY real up 1. What device hardware can only provide a quick I am signal? 2. What more than one hardware device wants to send an interrupt request? 3. What the programmer wants to ignore low priority interrupt requests? 4. What certain interrupt requests are too important to ignore?

4 What hardware device can only provide a quick I am signal? Add interrupt (capture) latch to processor (Capture Request) What the programmer wants to ignore a low priority interrupt? Add (Ignore) Interrupt Mask (Capture) e.g. IGNORE INTERRUP IF FIO_MASK_A BIT is 0 (Lab. 1) Interrupt Mask Ignore FAST CHANGING Signal send (1) and then becomes 0 BECOMES REQUEST LINE What certain hardware interrupts are too important to ignore? NMI bypass the IGNORE Interrupt Mask Non-Maskable Interrupts NMI (Capture) Interrupt Mask Ignore What more than one hardware wants to send an interrupt? NMI Pending interrupts (still to be done (Capture) Interrupt Mask Ignore BECOMES REQUEST LINE BECOMES REQUEST LINE

Blackfin MASKS and Latches Same hardware in concept as previous slides Have discussed Normal, Hardware Loop, Jump, Conditional Jump Call, RTS

0 and 2 uttcos Normal linear flow causes PC to increment to be able to fetch next next instruction Subroutine call flow PC increments, but is then

Instruction Pointer register Fetch instruction at memory location PC then increment the PC to point at the next instruction PC = PC+2 or for bigger

5 Blackfin MASKS and Latches Same hardware in concept as previous slides Have discussed Normal, Hardware Loop, Jump, Conditional Jump Call, RTS Program flow before Unpredictable and planned interrupts Using idle low power mode in Lab. 0 and 2 uttcos Normal linear flow causes PC to increment to be able to fetch next next instruction Subroutine call flow PC increments, but is then stored (link register) and PC forced to Jump to new instruction at start of subroutine function PC = PC + 2 uses program counter PC as an Instruction Pointer register Fetch instruction at memory location PC then increment the PC to point at the next instruction PC = PC+2 or for bigger instr PC = PC + 4; CALL ES RETS = PC + 4 (FFA03C78) PC set to 0xFFA01E24 So instruction 0xFFA01E24 done next This instruction is NOT fetched (until end of subroutine) This instruction is now fetched HAVE JUMPED TO SUBROUTINE

Interrupt dferent -- Occurs ANYTIME, ANYWHERE Must Jump to NOW, not later! How can the up do this? What must happen to PC? Interrupt occurs HERE (green arrow) Must Jump to NOW but how?

L = instruction Remember what instruction you were about to execute so up can do that instruction after finishing the Hardware Interrupt could occur anytime, anywhere in C++ or ASM or library code

at the next instruction PC = PC+2 PC = PC + 4; How make this happen? RETI is register used to remember the instruction stopped by interrupt RETI = PC (0xFFA01E44) PC must get set to what?

6 Interrupt dferent -- Occurs ANYTIME, ANYWHERE Must Jump to NOW, not later! How can the up do this? What must happen to PC? Interrupt occurs HERE (green arrow) Must Jump to NOW but how? First step is obvious PC has 0xFFA01E44 in it up just about to fetch P0.L = instruction Remember what instruction you were about to execute so up can do that instruction after finishing the Hardware Interrupt could occur anytime, anywhere in C++ or ASM or library code (or while up sitting at a breakpoint being debugged (Lab 0, 2, 3, 4) ) Use program counter PC as an Instruction Pointer register Fetch instruction at memory location PC then increment the PC to point at the next instruction PC = PC+2 PC = PC + 4; How make this happen? RETI is register used to remember the instruction stopped by interrupt RETI = PC (0xFFA01E44) PC must get set to what????? value to make interrupt service routine run for this interrupt? Interrupt occurs HERE Must Jump to but how First step is obvious Remember what instruction you were about to execute RETI = PC (0xFFA01E44) PC =????? Some how like magic we must have the up set PC = start of Timer 0xFFA01EC0 then processor will start executing Timer code Solution Blackfin has Lookup table of what value to put into PC for each interrupt than can occur Look-up table for the start of every interrupt routine is stored in EVR table Event vector register table (see BF533 reference sheet) To Vector is a verb Meaning to lead or direct to Obvious Post-Lab Quiz 3 question to set EVR Event (e.g interrupts) Table EVT6 Entry for CORE-TIMER interrupt

there is an interrupt of this sort EXCEPTION VDSP / CCES Emulator puts in a breakpoint so for us, as developers, the program stops.

7 Why do all these event addresses in the EVR ( jump) table start the same? The don t know what to do exception service routine (ESR) IDLE This is the assembly code While (wait till some happens) instruction This is the address of the the processor does not know what to do there is an interrupt of this sort EXCEPTION VDSP / CCES Emulator puts in a breakpoint so for us, as developers, the program stops. In real le processor can t stop, just goes into an infinite loop until watchdog timer resets the processor Don t know what to do Exception This exception hangs the processor Keeps doing same instruction (doing nothing) which is safer than doing something The developer should have provided a better ESR had known what to do Solution Lookup table of what value to put into PC for each type of interrupt that occurs Question the start of the is in the event table How did it get there? Problem solved by using WATCHG TIMER Event (e.g interrupts) Table

The start address of the got into the event table HOW?

Latches SetUp_EVT Also we can understand what the raise( ) C++ function does This is a special C++

making the processor think that a hardware interrupt has happened Event table information can be

8 The start address of the got into the event table HOW? Tell (register) the processor how to handle each interrupt service routine Blackfin MASKS and Latches SetUp_EVT Also we can understand what the raise( ) C++ function does This is a special C++ instruction to allow us to test Raise( ) use software to put a 1 into the interrupt latch register making the processor think that a hardware interrupt has happened Event table information can be found in the Blackfin Hardware Manual and Blackfin Reference Sheet What happens the device does take away its I m signal during an interrupt? (Capture)

These registers control other interrupt capability IMASK the interrupt control register for the whole processor SIC-

for other interrupt activity Details of the Core Event Table used by IMASK controller when responding to request Shows

Tackled today Three ways of handling hardware requests for service Wait till the device signals then process the data

9 These registers control other interrupt capability IMASK the interrupt control register for the whole processor SIC- IMASK the interrupt control register for the processor peripherals IMASK over-rides SIC_IMASK These figures are useful for other interrupt activity Details of the Core Event Table used by IMASK controller when responding to request Shows how the entries in the SIC_IMASK are normally mapped (multiplexed) to entries in IMASK Can be changed you need to Tackled today Three ways of handling hardware requests for service Wait till the device signals then process the data If device 1 process its data Else If device 2 process its data POLL Interrupt start processing the data from a specic device NOW!

WATCHDOG TIMER ISR DEVELOPMENT TDD APPROACH

WATCHDOG TIMER ISR DEVELOPMENT TDD APPROACH Through the use of user stories You can use a very similar approach when testing your CORE_TIMER ISR during Assignment 2 When developing the coffeepot Water