Digital Control of Electric Drives
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1 Digital Control of Electric Drives Computer System Structure Interrupt System Computer Programmer s Model Czech Technical University in Prague Faculty of Electrical Engineering Ver.1.00 J. Zdenek 2017
2 Procedure Call (Asynchronous) Hardware Call Interrupt Request Interrupt Controller BE1M14DEP Digital Control of Electric Drives - 2 2
3 Procedure Call (Asynchronous) Hardware Call Check list No.6 Asynchronous actions Interrupt system Hardware procedure call Predefined target address Interrupt vector Interrupt vector table Asynchronous interrupt request Interrupt controller Interrupt request inputs Interrupt event CPU interrupt request CPU interrupt acknowledge BE1M14DEP Digital Control of Electric Drives - 2 3
4 Procedure Call (Asynchronous) Hardware Call Check list No.7 Asynchronous actions cont'd Instruction is uninterruptable Interrupt latency Interrupt priority Static interrupt priority Dynamic interrupt priority Software interrupt priority Interrupt types Maskable interrupt Nonmaskable interrupt Trap (software interrupt) Event driven program BE1M14DEP Digital Control of Electric Drives - 2 4
5 Procedure Call (Asynchronous) Hardware Call Check list No.8 Asynchronous actions cont'd Interrupt service routine - ISR Interrupt return address Interrupt return instruction Asynchronous event Background (level) Lowest program level Shared resources Accumulator Processor status word - PSW Flag register Program context (save/restore) BE1M14DEP Digital Control of Electric Drives - 2 5
6 Procedure Call (Asynchronous) Hardware Call BE1M14DEP Digital Control of Electric Drives - 2 6
7 Procedure Call (Asynchronous) Hardware Call BE1M14DEP Digital Control of Electric Drives - 2 7
8 Shared Resources between ISR and Interrupted Program BE1M14DEP Digital Control of Electric Drives - 2 8
9 Interrupt Request (Hardware Procedure Call) BE1M14DEP Digital Control of Electric Drives - 2 9
10 Interrupt Request Pending - 1 BE1M14DEP Digital Control of Electric Drives
11 Complete Current Instruction - 2 BE1M14DEP Digital Control of Electric Drives
12 Save (Push) Return Address on Stack - 3 BE1M14DEP Digital Control of Electric Drives
13 Take ISR Address Out of Interrupt Vector Table - 4 BE1M14DEP Digital Control of Electric Drives
14 Start Interrupt Service Routine (ISR) - 5 BE1M14DEP Digital Control of Electric Drives
15 Save Context on Stack - 6 BE1M14DEP Digital Control of Electric Drives
16 Execute Interrupt Service Routine (ISR) Body - 7 BE1M14DEP Digital Control of Electric Drives
17 Restore Context (from Stack) - 8 BE1M14DEP Digital Control of Electric Drives
18 Restore Return Address (from Stack) - 9 BE1M14DEP Digital Control of Electric Drives
19 Continue Operation of Interrupted Program - 10 BE1M14DEP Digital Control of Electric Drives
20 Event Driven Program Principle - Summary Interrupt request service summary Finish current background instruction (instruction is uninterruptable) Push Return Address to stack (i.e. address in program counter) Get ISR Address from Interrupt Vector Table Start ISR routine Clear Interrupt Request Flag (depends on processor type) Save context to stack Run ISR body Restore context from stack Execute Return instruction Pop Return Address from stack (Pop it to program counter) Continue background program read next instruction from address in PC BE1M14DEP Digital Control of Electric Drives
21 Interrupt System Types Single level - non-priority interrupt system Multi level priority interrupt system Nonmaskable Trap Maskable Fixed priority system Flexible priority system BE1M14DEP Digital Control of Electric Drives
22 Interrupt Controller Principle Interrupt Enable Interrupt Flag Interrupt Request Maskable Interrupt Enable/Disable BE1M14DEP Digital Control of Electric Drives
23 Programmer s Model of Computer Check list No.9 Programmer s model ALU arithmetic logic unit PC program counter SP stack pointer PSW processor status word Accumulator Universal register address space Program memory address space Data memory address space Stack address space Input/output space Interrupt vector table space BE1M14DEP Digital Control of Electric Drives
24 Programmer s Model of Computer BE1M14DEP Digital Control of Electric Drives
25 PIC18F Family Program Memory PROGRAM COUNTER PROGRAM MEMORY SP STACK POINTER Top of Stack -TOS 5 PC STACK AF4h h h h RESET HIGH PRIORITY LOW PRIORITY RESET VECTOR HIGH PRIORITY INTERRUPT VECTOR LOW PRIORITY INTERRUPT VECTOR INTERRUPT VECTOR TABLE TOS REGISTERS TOSU 01h 8 TOSH 8Ah 8 TOSL F4h 8 TABLE READ IMPLEMENTED MEMORY (FLASH) 01FFF8h 01FFFFh CONFIG. WORDs PROGRAM MEMORY ADDRESS SPACE Read as 0 1FFFFFh 16 BE1M14DEP Digital Control of Electric Drives
26 PIC18F Family Data Memory BE1M14DEP Digital Control of Electric Drives
27 PIC18F Family Interrupt System High Priority Enable Priority System On Low Priority Enable Interrupt Priority Interrupt Enable Interrupt Flag (Request) BE1M14DEP Digital Control of Electric Drives
28 CPU Structure versus Operands Check list No.10 CPU systems versus operands Stack oriented ALU, PSW (Flags) stack Accumulator oriented ALU, PSW (Flags), Accumulator Data memory Register oriented ALU,PSW (Flags) Universal (scratchpad) registers Memory oriented ALU, PSW (Flags), data memory BE1M14DEP Digital Control of Electric Drives
29 CPU Structure versus Operands - 1 STACK TOS ALU FLAGS STATUS STACK ORIENTED CPU BE1M14DEP Digital Control of Electric Drives
30 CPU Structure versus Operands - 2 DATA MEMORY ALU FLAGS STATUS ACCUMULATOR ACCUMULATOR ORIENTED CPU BE1M14DEP Digital Control of Electric Drives
31 CPU Structure versus Operands - 3 REGISTERS (INSIDE CPU) ALU FLAGS STATUS REGISTER ORIENTED CPU BE1M14DEP Digital Control of Electric Drives
32 CPU Structure versus Operands - 4 DATA MEMORY ALU FLAGS STATUS MEMORY ORIENTED CPU BE1M14DEP Digital Control of Electric Drives
33 Digital Control of Electric Drives Computer System Structure Interrupt System Computer Programmer s Model END Czech Technical University in Prague Faculty of Electrical Engineering
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