International Journal of Engineering Research & Technology (IJERT) ISSN: Vol. 2 Issue 5, May

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1 Intertage Pipeline VLI Architecture for 2-D DWT Ajinkya. Bankar 1,Bhavika. haha 2, P.K. Kadbe 3 E&TC Department, Pune Univerity 1,2,3 VPCOE Baramati Abtract In thi paper, a cheme for the deign of a high-pd pipeline VLI architecture for the computation of the 2- D dicrete wavelet tranform (DWT) i propd. The main focu in the development of the architecture i on providing a high operating frequency and a mall number of clock cycle along with an efficient hardware utilization by maximizing the inter-tage computational parallelim for the pipeline. The highpd computation i achieved by efficiently ditributing the tak of the computation of multiple decompoition level among the tage of the pipeline and by optimally configuring the data and ynchronizing the operation of pipeline o a to maximize the inter-tage computational parallelim. To validate the propd cheme, an algorithm i deigned and implemented in MATLAB for the 2-D DWT computation. Then the circuit i imulated and implemented in VDL. 1. Introduction With the rapid progre of VLI deign technologie, many procr baed on audio and image ignal proceing have bn developed recently. The two-dimenional dicrete wavelet tranform (2-D DWT) play major role in image/vid compreion tandard. Wavelet decomp the ignal at one level of approximation and detail ignal at the next level. Thu ubequent level can add more detail to the information content. In addition to audio and image compreion, the DWT ha important application in many area, uch a computer graphic, numerical analyi, radar target ditinguihing and o forth. DWT i a computationally very intenive proce and low for many real-time application when implemented in a general purp computing ytem. It i ntial to develope cutom VLI chip for DWT exploiting the underlying data parallelim to achieve high data rate.. Y. Liao et al. [2] have prnted an architecture in which each of the row and columnwie filtering operation are decompd uing the o called lifting operation into a cacade of ub-filtering operation. The cheme lead to a low-complexity architecture with a large latency. C. Cheng et al. [3] have propd an architecture in which a number of parallel FIR filter with a polyphae tructure are ued to improve the proceing pd at the expene of increaed hardware. F. Marino et al. [4] have introduced a two-tage pipeline architecture in which the firt tage perform the tak of the firt decompoition level and the econd one that of all the remaining level, and ha aimed at providing a hort computation time. A the proceing unit employed in thi architecture differ from one another, the complexity of the hardware rurce i high and the deign of the architecture i complicated. A. Benkrid et al. [5] prnt an FPGA architecture for the eparable 2-D Biorthogonal Dicrete Wavelet Tranform (DWT) decompoition. The architecture i baed on the Pyramid Algorithm Analyi, which handle computation along the border efficiently by uing the method of ymmetric extenion. P. McCanny et al. [6] have given, a VLI architecture for performing the ymmetrically extended twodimenional tranform i prnted. Thi architecture conform to the JPEG tandard and i capable of near-optimal performance when dealing with the image boundarie.the architecture alo achieve efficient procr utilization.. Raghunath et al. [7] have prnted an efficient architecture for a multi-rlution ymmetrically extended 2-D 9/7 filter dicrete wavelet tranform procr i prnted. ardware complexity i greatly reduced with improved performance, due to the propd combination of lifting cheme and line baed architecture. I.. Uzun et al. [8] have deigned the non-eparable 2-D dicrete biorthogonal wavelet filter architecture which ha bn derived from modified-recurive-pyramid-algorithm. MRPA baed architecture exploit the downampling of output ubband and perform the firt decompoition level interpered with all other level by mean of only one proceing unit. C. Zhang et al. [9] prnt, a cheme for the deign of a high-pd pipeline VLI architecture for the computation of the 2-D dicrete wavelet tranform (DWT). The main focu in the development of the architecture i on providing a high operating frequency and a mall number of clock cycle along with an efficient hardware utilization. 943

2 In thi paper, a non-eparable pipeline architecture for fat computation of the 2-D DWT with a reaonable low cot for the hardware rurce i propd. eparable approach i a imple way to compute the 2-D DWT. owever, eparable filter being a pecial cla of 2-D filter are not capable to approximate well all arbitrary frequency repone. In thi regard, a noneparable approach of the 2-D computation provide more flexibility. In the non-eparable approach depicted in Fig. 1, the DWT of a 2-D ignal (n 1, n 2 ) i computed by carrying out four eparate 2-D filtering operation uing four 2-D filter: a highpa-highpa () filter G (z 1, z 2 ), a highpa-lowpa (L) filter G L (z 1, z 2 ), a lowpa-highpa (L) filter G L (z 1, z 2 ), and a lowpa- lowpa (LL) filter G LL (z 1, z 2 ).The output ignal of th four filter are then decimated by a factor of two in the horizontal and vertical direction producing, repectively the, L, L and LL component. Fig.1 Computation of 1-Level 2-D DWT baed on Non- eparable approach 2. Formulation for the computation of 2-D DWT The 2-D DWT i an operation through which a 2-D ignal i ucceively decompd in a patial multirlution domain by low- pa and highpa FIR filter along each of the two dimenion. The four FIR filter, denoted a highpa-highpa (), highpa-lowpa (L), lowpa-highpa (L) and lowpa-lowpa (LL) filter, produce, repectively, the, L, L and LL ubband data of the decompd ignal at a given rlution level. The ample of the four ubband of the decompd ignal at each level are decimated by a factor of two in each of the two dimenion. For the operation at the firt level of decompoition, the given 2-D ignal i ued a input, wherea for the operation of the uccding level of decompoition, the decimated LL ubband ignal from the previou rlution level i ued a input. 2.1 Formulation for the Computation of Four ubband Let a 2-D ignal be reprnted by N 0 N 0 matrix (0), with it (m, th element denoted by (0) (m,(0 m, n N 0-1), where N 0 i chn to be 2 J, J being an integer. Let the cfficient of a 2-D FIR filter P (P=, L, L, LL) be reprnted by an L M matrix (P). The (k,i) th cfficient of the filter P i denoted by (P) (k, i)(0 k L-1; 0 i M-1). The decompoition at a given level j=1, 2,,, J can be exprd a- A B C L1 k0 L1 k0 L1 k0 L1 k0 M 1 i0 M 1 i0 M 1 i0 M 1 i0 ( ) ( L) ( L ) ( j1) ( j1) ( j1) ( j1) k,2n i) k,2n i) k,2n i) k,2n i) (1) (2) (3) (4) where A (j), B (j), D (j) and (j), repectively, reprnting the, L, L and LL ubband of the 2-D input ignal at the j th level. 2.2 Formulation for a Four-Channel Filtering Operation In order to facilitate parallel proceing for the 2-D DWT computation, the L M filterig operation nd to be divided into multi-channel operation, each channel proceing one part of the 2-D data. It i n from (4) that the even and odd indexed element are alway operated on the even and odd indexed filter cfficient, repectively. The matrix (j) reprnting the LL ubband at the jth level can, therefore, be divided into four (Nj/2+ L/2) (Nj/2 + M/2) ubmatrice, (j), (j), (j) and (j) oo, wh (m, th (0 m Nj/2 + L/2-1, 0 n Nj/2 +M/2-1) element are given by oo,2 1,2,2n 1) 1,2n 1) (5) taking into conideration the periodic padding ample at the boundary. It i n from (5) that the data at any rlution level are divided into four channel for proceing by firt eparating the even and odd indexed row of (j), and then eparating the even and odd indexed column of the reulting two ub matrice. The 944

3 data in each channel can then be computed by an (L/2 M/2)-tap filtering operation. In order to facilitate uch a 4-channel filtering operation, the filter cfficient, a ued in (4), nd to be decompd appropriately. Accordingly, the matrix (P) nd to be decompd into four (L/2 M/2) ub-matrice, (p), (p), (p) and (p) oo, wh (k,i)th (0 k L/2-1, 0 i M/2-1) element are given by repectively. ( P ) ( ( P) P),2 1,2 (6),2n 1) oo 1,2n 1) By uing (5) and (6) in ( 1-4), any of the four ubband ignal, A (j),b (j), C (j) and (j), at the j th rlution level, can be computed a a um of four convolution uing (L/2 M/2)-tap filter. For example, the LL ubband given by (4) can now be exprd a L/ 21 M / 2 1 k0 i0 L/ 21 M / 2 1 k0 i0 L/ 21 M / 2 1 k0 i0 L/ 21 M / 2 1 k0 i0 oo ( j1) ( j1) ( j1) ( j1) oo ( m k, n i) ( m k, n i) ( m k, n i) ( m k, n i) (7) At any rlution level, the eparation of the ubband proceing correponding to even and odd indexed data a given by (7) i conitent with the requirement of decimation of the data in each dimenion by a factor of two in the DWT computation. It i alo n from (7) that the filtering operation in the four channel are independent and identical, which can be exploited in the deign of an efficient pipeline architecture for the 2- D DWT computation. 3. Pipeline For The 2-D DWT Computation A traightforward mapping of the overall tak of the DWT computation to a pipeline i one-level to onetage mapping, in which the tak of J rlution level are ditributed to J tage of the pipeline. In thi mapping, the amount of hardware rurce ued by a tage hould be one-quarter of that ued by the preceding tage. Thu, the ratio λ of the hardware rurce ued by the lat tage to that ued by the firt tage ha a value of 1/4 J-1. For image of typical ize, thi parameter would aume a very mall value. ence, for a tructure of the pipeline that ue identical filter unit, the number of th filter unit would be very large. Further, ince the number of uch filter unit employed by the tage would decreae exponentially from one tage to the next in the pipeline, it will make their ynchronization very difficult. The olution to uch a difficult ynchronization problem, in general, require more control unit, multiplexer and regiter, which reult in a higher deign complexity. A reaonably large value of λ< 1 would be more attractive for ynchronization. In thi repect, the parameter λ can be n a a meaure of deign difficulty, with a maller value of thi parameter reprnting a greater deign complexity[9]. The parameter λ can be increaed from it value of 1/4 J-1 in the one-level to one- tage pipeline tructure by dividing the large-ize tage into a number of maller tage or merging the mall-ize tage into larger one. owever, dividing a tage of the one-level to one-tage pipeline into multiple tage would require a diviion of the tak aociated with the correponding rlution level into ub-tak, which in turn, would call for a olution of even a more complex problem of ynchronization of the ub-tak aociated with divided tage. On the other hand, merging multiple mall-ize tage of the pipeline into one tage would not create any additional ynchronization problem. A a matter of fact, uch a merger could be ued to reduce the overall number of filter unit of the pipeline. Fig.2 Pipeline tructure with I tage for J-level computation In view of the above dicuion, the ynchronization parameter λ can be increaed by merging a number of tage at tail end of the pipeline. Fig. 2 how the tructure of a pipeline in which the tage I to J of the one-level to one-tage pipeline have bn merged. In thi tructure, the tak of the rlution level from j=1 to j=i - 1 are mapped to tage 1 to I - 1, repectively, wherea th of the rlution level j=i,, J are mapped all together to the I th tage. Note that the total amount of computation performed by tage I i le than one-half of that performed by tage I - 1. Conidering the fact that the number of filter unit employed by each tage of the pipeline i an integer, it i reaonable to have the ratio of the number of filter unit ued by the lat two tage (i.e., tage I - 1 and I) to be 2:1. The value of the parameter λ i now increaed from 1/4 J-1 to 1/4I-1.5. owever, now the rurce employed by tage I would not be fully 945

4 utilized, which would lower the efficiency of the hardware utilization of the pipeline of Fig. 2 Aume that the parameter η reprnt the hardware utilization efficiency defined a the ratio of the rurce ued to that employed by the pipeline [9]. The hardware utilization efficiency η of the pipeline in Fig.2 can be hown to be equal to (1-4 -J )/( I+0.5 ). ince for image of typical ize, 4 -J i negligibly mall compared to one, the expreion for η can be implified a 1/( I+0.5 ). A the number of tage I employed by the pipeline increae, the hardware utilization efficiency increae with the parameter η approaching unity for a maximum efficiency. On the other hand, the difficulty in ynchronizing the tage get wore a the parameter λ decreae with increaing value of I. A variation in the value of I reult in the value of λ and η that are in conflict from the point of view of tage ynchronization and hardware utilization efficiency. Therefore, a value of I nd to be determined that optimize the value of λ and η jointly. Conidering an example of an image of ize , in which cae J=8. Table I give the value of the parameter λ and η for the pipeline tructure with I=2,3 and 4. Table 1 Value of the parameter λ and η Parameter I=2 I=3 I=4 λ 1/2 1/8 1/32 η 89% 96% 99% It i n from thi table that the 2-tage and 3-tage pipeline have acceptable value of λ, wherea the ynchronization of the 4-tage pipeline would be very difficult becaue of it very low value of λ=1/32. On the other hand, the 3-tage and 4-tage pipeline have more deirable value of η in comparion to that for the 2-tage pipeline. Therefore, a 3-tage pipeline with an acceptable value for the ynchronization parameter and high hardware utilization efficiency would be the bet choice of a pipeline 4. Deign Of tage data reulting from the even or odd numbered row and even or odd numbered column of an L M window of an LL- ubband data[9]. An L M window of the raw 2- D input data or that of an LL-ubband data mut be decompd into four ditinct L/2 M/2 ub-window in accordance with the four decompd term given by the right ide of (7). Thi decompoition of the data in an L M window can be accomplihed by deigning for each tage an appropriate data canning unit (DU) baed on the way the raw input or the LL-ubband data i canned. The tage would alo require memory pace (buffer) to tore the raw input data or the LLubband data prior to canning. Fig.3 give the block diagram of the pipeline howing all the component required by the thr tage. Note that the data flow hown in thi figure comprie only the LL ubband data neceary for the operation of the tage Fig.3 Block diagram of the thr-tage architecture 5. Performance Reult The Pipeline algorithm for decompoition of input data i implemented in MATLAB. Fig.5 how input image and reult of 1 t level of decompoition and Fig.6 how 2 nd and Fig.7 how 3 rd level of decompoition. In the propd thr-tage architecture, tage 1 and 2 perform the computation of level 1 and 2, repectively, and tage 3 that of all the remaining level. ince the baic operation of computing each output ample, regardle of the rlution level or the ubband, i the ame, the computation block in the thr tage can differ only in the number of identical proceing unit employed by them depending on the amount of the computation aigned to the tage. A n from (7), an (L M)-tap filtering operation i decompd into four independent (L/2 M/2)-tap filtering operation, each operating on the 2-D L/2 M/2 Input Image 1 t Level of Decompoition Fig.5 Reult of MATLAB Implementation 946

5 2 nd Level of Decompoition Fig.6 Reult of MATLAB Implementation 3 rd Level of Decompoition Fig.7 Reult of MATLAB Implementation tage 1 tage 2 tage 3 Fig.8 Modelim imulation reult of Pipeline Algorithm ame pipeline algorithm i implemented in VDL. For thi purp the filter co-efficient are caled and then they are ued in the deign. Thi digital deign i imulated in Modelim and it reult are hown in Fig.8. For 100Mz of clock ignal,thr tage of pipeline, thr level of decompoition and image ize of 16 16, it require 16395n. 6. Concluion To enhance the inter-tage parallelim, it i mot efficient to map the overall tak of the DWT computation to only thr pipeline tage for performing the computation tak correponding to the decompoition level 1, level 2, and all the remaining level, repectively. Two parameter, one pecifying the ynchronization of the operation of the tage and 947

6 the other reprnting the utilization of the hardware rurce of the pipeline, have bn defined. It ha bn hown that the bet combination for the value of th parameter i achieved when the pipeline i chn to have thr tage. 7. Reference [1]. Mallat, A thry for multirlution ignal decompoition: The wavelet reprntation IEEE Tran. Pattern Anal. Mach. Intell., vol.11, no. 7, pp , Jul.1989 [2]. Y. Liao, M. K. Mandal, and B. F. Cockburn, Efficient architecture for 1-D and 2-D lifting-baed wavelet tranform, IEEE Tran. ignal Proce., vol. 52, no. 5, pp , May [3] C. Cheng and K. K. Parhi, igh-pd VLI implementation of 2-D dicrete wavelet tranform, IEEE Tran. ignal Proce., vol. 56, no.1, pp , Jan [4] F. Marino, Efficient high-pd low-power pipelined architecture for the direct 2- D dicrete wavelet tranform, IEEE Tran. Circuit yt. II, Analog. Digit. ignal Proce., vol. 47, no. 12, pp , Dec [5] A. Benkrid, D. Crooke, and K. Benkrid, Deign and implementation of a generic 2-D orthogonal dicrete wavelet tranform on an FPGA, in Proc. IEEE 9th ymp. Fieldprogramming Cutom Computing Machine (FCCM), Apr. 2001, pp [6] P. McCanny,. Maud, and J. McCanny, Deign and implementation of the ymmetrically extended 2-D wavelet tranform, in Proc. IEEE Int. Conf. Acoutic, pch, ignal Proce.(ICAP), 2002, vol. 3, pp Raghunath and. M. Aziz, igh pd area efficient multi-rlution 2-D 9/7 filter DWT procr, Proc. Int. Conf. Very Large cale Integration (IFIP), Oct. 2006, vol Pp, [7] I.. Uzun and A. Amira, Rapid prototyping-framework for FPGA baed dicrete biorthogonal wavelet tranform implementation, IEE Viion, Image ignal Proce., vol. 153, no. 6, pp , Dec [8] C. Zhang, C. Wang, and M. O. Ahmad, A Pipeline VLI Architecture for Fat Computation of the 2-D Dicrete Wavelet Tranform, IEEE Tran. On Circuit and ytem-i, vol. 59, No. 8, Augut [9] M. Alam,W. Badway, V. Dimitrov and G. Jullien, An Efficient Architecture for a Lifted 2D Biorthogonal DWT, Journal of VLI ignal Proceing 40, , [10] R.C. Gonzalez,R. Wood, Digital Image Proceing,Prentice-all,3rd Edition, [11] Principle of Digital ytem Deign uing VDL, Charle. Roth, Jr. & Lizy Kurian John, 1998 Cengage Learning publication. 948