Laboratory Exercise 6

Transcription

1 Laboratory Exercie 6 Adder, Subtractor, and Multiplier The purpoe of thi exercie i to examine arithmetic circuit that add, ubtract, and multiply number. Each type of circuit will be implemented in two way: firt by writing Verilog code that decribe the required functionality, and econd by making ue of predefined ubcircuit from Altera library of parameterized module (LPM). The reult produced for variou implementation will be compared, both in term of the circuit tructure and it peed of operation. Part I Conider again the four-bit ripple-carry adder circuit that wa ued in lab exercie 2; a diagram of thi circuit i reproduced in Figure 1a. You are to create an 8-bit verion of the adder and include it in the circuit hown in Figure 1b. Your circuit hould be deigned to upport igned number in 2 -complement form, and the Overflow output hould be et to 1 whenever the um produced by the adder doe not provide the correct igned value. Perform the tep hown below. c 3 c 2 c 1 c in FA FA FA FA c out a) Four-bit ripple-carry adder circuit 8 8 Clock R Q R Q A B Q D cout c out + ccin 8 R Q Overflow S b) Eight-bit regitered adder circuit Figure 1. An 8-bit igned adder with regitered input and output. 1

2 1. Make a new Quartu II project and write Verilog code that decribe the circuit in Figure 1b. Ue the circuit tructure in Figure 1a to decribe your adder. 2. Include the required input and output port in your project to implement the adder circuit on the DE2 board. Connect the input A and B to witche SW 15 8 and SW 7, repectively. Ue KEY a an active-low aynchronou reet input, and ue KEY 1 a a manual clock input. Diplay the um output of the adder on the red LEDR 7 light and diplay the overflow output on the green LEDG 8 light. The hexadecimal value of A and B hould be hown on the diplay HEX7-6 and HEX5-4, and the hexadecimal value of S hould appear on HEX Compile your code and ue timing imulation to verify the correct operation of the circuit. Once the imulation work properly, download the circuit onto the DE2 board and tet it by uing different value of A and B. Be ure to check for proper functionality of the Overflow output. 4. Open the Quartu II Compilation Report and examine the reult reported by the Timing Analyzer. What i the maximum operating frequency, fmax, of your circuit? What i the longet path in the circuit in term of delay? Part II Modify your circuit from Part I o that it can perform both addition and ubtraction of eight-bit number. Ue witch SW 16 to pecify whether addition or ubtraction hould be performed. Connect the other witche, light, and diplay a decribed for Part I. 1. Simulate your adder/ubtractor circuit to how that it function properly, and then download it onto the DE2 board and tet it by uing different witch etting. 2. Open the Quartu II Compilation Report and examine the reult reported by the Timing Analyzer. What i the fmax of your circuit? What i the longet path in the circuit in term of delay? Part III Repeat Part I uing the predefined adder circuit called lpm add ub, intead of your ripple-carry adder tructure from Figure 1. The lpm add ub module can be found in Altera library of parameterized module (LPM), which i provided a part of the Quartu II ytem. The procedure for uing thee predefined module in Quartu II project i decribed in the tutorial Uing Library Module in Verilog Deign, which i available on the DE2 Sytem CD and in the Univerity Program ection of Altera web ite. 1. Configure the lpm add ub module o that it perform only addition, to make the functionality comparable to Part I. Store your configuration of the lpm add ub module in the file lpm add8.v. After intantiating thi module in your Verilog code, compile the project and ue the Quartu II Chip Planner tool to examine ome of the detail of the implemented circuit. One way to examine the adder ubcircuit uing the Chip Planner tool i illutrated in Figure 2. In the Quartu II Project Navigator window right-click on the part of your circuit hierarchy that repreent the lpm add8 ubcircuit, and elect the command Locate > Locate in Chip Planner(Floor Plan & Chip Editor). Thi open the Chip Planner window hown in Figure 3. The logic element in the Cyclone II FPGA that are ued to implement the adder are highlighted in blue in the Chip Planner tool. Poition your moue pointer over any of thee logic element and double-click to open the Reource Property Editor window diplayed in Figure 4. In the box labeled Node name you can elect any of the nine logic element that implement the adder module. The Reource Property Editor allow you to examine the content of a logic element and to ee how one logic element i connected other. 2

3 Figure 2. Locating the eight-bit adder in the Chip Planner tool. Figure 3. The highlighted logic element for the eight-bit adder. Uing the tool decribed above, and referencing the Data Sheet information for the Cyclone II FPGA, decribe the eight-bit adder circuit implemented with the lpm add ub module. 3

4 Figure 4. Examining detail in a logic element uing the Reource Property Editor. 2. Open the Quartu II Compilation Report and and compare the fmax of your adder circuit with the one deigned in Part I. Dicu any difference in performance that are oberved. Part IV Repeat Part II uing the predefined adder circuit called lpm add ub, intead of your adder-ubtractor circuit baed on Figure 1. Comment briefly on the circuit tructure obtained uing the LPM module, and compare the fmax of thi circuit to the one from Part II. Decribe how the lpm add ub module implement the Overflow ignal. 4

5 Part V Figure 5a give an example of the traditional paper-and-pencil multiplication P = A B, where A = 12 and B =11. We need to add two ummand that are hifted verion of A to form the product P = 132. Part b of the figure how the ame example uing four-bit binary number. Since each digit in B i either 1 or, the ummand are either hifted verion of A or. Figure 5c how how each ummand can be formed by uing the Boolean AND operation of A with the appropriate bit in B. 1 2 x a) Decimal 1 1 x b) Binary x p 7 p 6 p 5 p 4 p 3 p 2 p 1 p c) Implementation Figure 5. Multiplication of binary number. A four-bit circuit that implement P = A B i illutrated in Figure 6. Becaue of it regular tructure, thi type of multiplier circuit i uually called an array multiplier. The haded area in the circuit correpond to the haded column in Figure 5c. In each row of the multiplier AND gate are ued to produce the ummand, and full adder module are ued to generate the required um. 5

6 b p 7 p 6 p 5 p 4 p 3 p 2 p 1 p Figure 6. An array multiplier circuit. Ue the following tep to implement the array multiplier circuit: 1. Create a new Quartu II project which will be ued to implement the deired circuit on the Altera DE2 board. 2. Generate the required Verilog file, include it in your project, and compile the circuit. 3. Ue functional imulation to verify that your code i correct. 4. Augment your deign to ue witche SW 11 8 to repreent the number A and witche SW 3 to repreent B. The hexadecimal value of A and B are to be diplayed on the 7-egment diplay HEX6 and HEX4, repectively. The reult P = A B i to be diplayed on HEX1 and HEX. 5. Aign the pin on the FPGA to connect to the witche and 7-egment diplay, a indicated in the Uer Manual for the DE2 board. 6. Recompile the circuit and download it into the FPGA chip. 7. Tet the functionality of your deign by toggling the witche and oberving the 7-egment diplay. 6

7 Part VI Extend your multiplier to multiply 8-bit number and produce 6-bit product. Ue witche SW 15 8 to repreent the number A and witche SW 7 to repreent B. The hexadecimal value of A and B are to be diplayed on the 7-egment diplay HEX7 6 and HEX5 4, repectively. The reult P = A B i to be diplayed on HEX3. Add regiter to your circuit to tore the value of A, B, and the product P, uing a imilar tructure a hown for the regitered adder in Figure 1. After uccefully compiling and teting your multiplier circuit, examine the reult produced by the Quartu II Timing Analyzer to determine the fmax of your circuit. What i the longet path in term of delay between regiter? Part VII Change your Verilog code to implement the 8 x 8 multiplier by uing the lpm mult module from the library of parameterized module in the Quartu II ytem. Complete the deign tep above. Compare the reult in term of the number of logic element (LE) needed and the circuit fmax. Part VIII It many application of digital circuit it i ueful to be able to perform ome number of multiplication and then produce a ummation of the reult. For thi part of the exercie you are to deign a circuit that perform the calculation S =(A B)+(C D) The input A, B, C, and D are eight-bit unigned number, and S provide 6-bit reult. Your circuit hould alo provide a carry-out ignal, C out. All of the input and output of the circuit hould be regitered, imilar to the tructure hown in Figure 1b. 1. Create a new Quartu II project which will be ued to implement the deired circuit on the Altera DE2 board. Ue the lpm mult and lpm add ub module to realize the multiplier and adder in your deign. 2. Connect the input A and C to witche SW 15 8 and connect the input B and D to witche SW 7. Ue witch SW 16 to elect between thee two et of input: A, B or C, D. Alo, ue the witch SW 17 a a write enable (WE) input. Setting WE to 1 hould allow data to be loaded into the input regiter when an active clock edge occur, while etting WE to hould prevent loading of thee regiter. 3. Ue KEY a an active-low aynchronou reet input, and ue KEY 1 a a manual clock input. 4. Diplay the hexadecimal value of either A or C, a elected by SW 16, on diplay HEX7-6 and diplay either B or D on HEX5-4. The um S hould be hown on HEX3-, and the C out ignal hould appear on LEDG Compile your code and ue either functional or timing imulation to verify that your circuit work properly. Then download the circuit onto the DE2 board and tet it operation. 6. It i often neceary to enure that a digital circuit i able to meet certain peed requirement, uch a a particular frequency of a ignal applied to a clock input. Such requirement are provided to a CAD ytem in the form of timing contraint. The procedure for uing timing contraint in the Quartu II CAD ytem i decribed in the tutorial Timing Conideration with Verilog-Baed Deign, which i available on the DE2 Sytem CD and in the Univerity Program ection of Altera web ite. For thi exercie we are uing a manual clock that i applied by a puhbutton witch, o no realitic timing requirement exit. But to demontrate the deign iue involved, aume that your circuit i required to operate with a clock frequency of 22 MHz. Enter thi frequency a a timing contraint in the Quartu II oftware, and recompile your project. The Timing Analyzer hould report that it i unable to meet the timing requirement due to the length of variou regiter-to-regiter path in the circuit. Examine the timing analyi report and decribe briefly the timing violation oberved. 7

8 7. One way to increae the peed of operation of a given circuit i to inert regiter into the circuit in a way that horten the length of it longet path. Thi technique i referred to a pipelining a circuit, and the inerted regiter are often called pipeline regiter. Inert pipeline regiter into your deign between the multiplier and the adder. Recompile your project and dicu the reult obtained. Part IX The Quartu II oftware include a predeigned module called altmult add that can perform calculation of the form S =(A B) +(C D). Repeat Part VIII uing thi module intead of the lpm mult and lpm add ub module. Tet your circuit uing both imulation and by downloading the circuit onto the DE2 board. Briefly decribe how the implementation of your circuit differ when uing the altmult add module. Examine it performance both with and without the pipeline regiter dicued in Part VIII. Copyright c 26 Altera Corporation. 8