Lecture 8: More Pipelining

Transcription

1 Overview Lecture 8: More Pipelining David Black-Schaffer EE8 Spring 00 Getting Started with Lab Jut get a ingle pixel calculating at one time Then look into filling your pipeline Multiplier Different option for pipelining: what do you need? Multiplier or put x*x, y*y, and x*y through equentially? Pipelining If it won t fit in one clock cycle you have to divide it up o each tage will fit The control logic mut be deigned with thi in mind Make ure you need it EE8 Lecture 8 - Slide Public Service Announcement Xilinx Programmable World Tueday, May 6th Guet Lecture Monday, April 8th Ryan Donohue on Metatability and Synchronization Wedneday, May 7th Gary Spivey on ASIC & FPGA Deign for Speed The content of thee lecture will be on the Quiz Logitic Lab Prelab due Friday by pm Guet lecture next Monday Synchronization and Metatability Thee are critical for high-peed ytem and anything where you ll be connecting acro clock domain. SHOW UP! (pleae) EE8 Lecture 8 - Slide EE8 Lecture 8 - Slide

2 EE8 Lecture 8 - Slide Eaier FSM or current_tate) begin write_en <= 0; output <= ; next_tate <= `START_STATE; cae(current_tate) `START_STATE: begin write_en <= ; if (button) next_tate <= `WAIT_STATE; end `WAIT_STATE: begin output <= 0; end end Do thi if nothing ele i pecified. Note that the ele i not pecified. What i the next tate? Be careful! Eay way to infer latche! EE8 Lecture 8 - Slide 6 Data Path - << + What do we + do if the + whole If> data output path doen t fit in one clock cycle? Pipelining Example Pipelining Example n * n * n * n n - 6n << n + 6n nn * n * n * n n - 6n << n + 6n n + 6n + If> output n n+??n + 6n + If> output n How long doe thi wire take? How long doe thi wire take? EE8 Lecture 8 - Slide 7 EE8 Lecture 8 - Slide 8

3 EE8 Lecture 8 - Slide 9 Pipelining Example - 6n << n + 6n + 6n + If> output n nn * n * n * n n 6n 6n +??n Not d Input d Input Latency and Throughput Comb. Logic n critical path tage A A A x S A A A x <0n critical path tage EE8 Lecture 8 - Slide 0 A A A Output Output Time Input Output t=0 A t=n A A t=70n A A t=0n A Firt output take longer becaue it ha to go through all the tage but ubequent reult can come out every clock cycle. Time Input S Output t=0 A t=0n A A t=0n A A A t=60n A A t=80n A Key point on Pipelining Increae utilization for operator You can do multiple calculation at once o you can ue everything maximally (ideally) Thi i the point! Store the reult from maller calculation to make the overall calculation fater. Inert the next data item into the datapath before the previou one ha finihed The pipe regiter keep the computation eparate You will have a lot of pipe regiter if you re doing a lot of calculation (I.e., Lab!) What i the effect of the algorithm feeding back on itelf? Do all point have the ame number of iteration? control I the data dependent between pipeline tage? hazard Multiplier CoreGen give you everal pipelining option Which i bet? Depend on your deign Data ize will determine peed and pipelining Deign i an iterative proce o you won t be able to chooe the bet approach at firt (i.e., get tarted early!) EE8 Lecture 8 - Slide EE8 Lecture 8 - Slide

4 Multiplier Iue Multiplier are BIG How can we get away with fewer multiplier? Multiplier may be SLOW How can we utilize them maximally? - << If> output EE8 Lecture 8 - Slide EE8 Lecture 8 - Slide Now we have With a -tage multiplier you ve now got pipeline tage How can you keep the pipeline full? How many thing do you need to calculate at once? What i full? Will you ever get 00% utilization? What i good enough? Add Add Ma * Ma * * Ma Mb * Mb * * Mb Mc * Mc * * Mc - << If> output EE8 Lecture 8 - Slide EE8 Lecture 8 - Slide 6

5 Performance Analyi With the bad data path (, tage multiplier and tage after that; one pixel at a time) Clk Ma Ma EE8 Lecture 8 - Slide 7 Ma Mb Mb Mb Mc Mc Mc In cycle we ued unit out of available: 0% average utilization Add Add Performance Analyi With the bad data path (, tage multiplier and tage after that; multiple pixel at a time) Clk Ma Ma v v v v v v EE8 Lecture 8 - Slide 8 Ma Mb Mb Mb Mc Mc Mc Add We approach 00% utilization if there are no tall or dependencie and we can keep getting new data Add What performance i required? Replication and Pipelining are not trivial to implement make ure you need them I either needed for Lab #? How would you tell? Hint: each Julia image take at mot (6*6*6*7*/0e6) = 0.06 to create. I thi real-time enough for an animation? Other iue? Need to meet timing for the VGA. What do we expect The previou data path i terribly inefficient if you only put one pixel through at a time, but doing multiple pixel at once i very complicated A an alternative you can ue one multiplier and put your x*x, y*y, and x*y through it in a pipelined manner. What the efficiency? I it a good tradeoff for area/peed? Thi analyi i critical! EE8 Lecture 8 - Slide 9 EE8 Lecture 8 - Slide 0

6 Performance Analyi Single multiplier, put x () through firt, then y (), then xy(). Clk 6 7 Ma Mb EE8 Lecture 8 - Slide Mc Add Add In 7 cycle we ue / functional unit = % But we only have multiplier How much pace do we ave? What i mot important? EE8 Lecture 8 - Slide Performance Concluion You need to know your algorithm and what tradeoff you are making What do you care about? Speed? Area? Both. (Power i a function of peed and number of tranitor, i.e., area.) Zooming An arbitrary portion of the creen can be decribed in many way. Here are two: Xmin, Xmax, Ymin, Ymax Require dividing by the number of pixel Xorigin, Yorigin, cale Require a fixed number of pixel Hint for Zooming: Have regiter with the X, Y origin and increment/decrement them with the up/down, left/right button Have a cale regiter which goe up/down with the zooming in/out When converting form 0..6 to -.00 to.00 ue the cale and origin to calculate the new value EE8 Lecture 8 - Slide EE8 Lecture 8 - Slide 6

7 Lecture 6 Key Point Pipelining increae the clock peed but decreae the amount of work per clock Parallelim i eay except for reource conflict Logitic Lab Prelab due Friday by pm URL to Joel Viiting lecturer next Monday content will be on the quiz EE8 Lecture 8 - Slide 7