Laboratory Exercise 6

Transcription

1 Laboratory Exercie 6 Adder, Subtractor, and Multiplier a a The purpoe of thi exercie i to examine arithmetic circuit that add, ubtract, and multiply number. Each b c circuit will be decribed in Verilog and implementedb o on an Altera DE2-erie board. Part I 1 a) Full adder circuit b) Full adder ymbol Conider again the four-bit ripple-carry adder circuit ued in lab exercie 2; it diagram i reproduced in Figure 1. b a c 3 c 2 c 1 b n ut c) Full adder truth table d) Four-bit ripple-carry adder circuit Figure 1: A four-bit ripple carry adder. Thi circuit can be implemented uing a ign in Verilog. For example, the following code fragment add n-bit number A and B to produce output um and carry: wire [n-1:] um; wire carry;... aign {carry, um} = A B; Ue thi contruct to implement a circuit hown in Figure 2. Deign and compile your circuit with uartu II oftware, download it onto a DE2-erie board, and tet it operation a follow: 1. Create a new uartu II project. Select the appropriate target chip that matche the FPGA chip on the Altera DE2-erie board. Implement the deigned circuit on the DE2-erie board. 2. Write Verilog code that decribe the circuit in Figure Connect input A to witche SW 7, and ue KEY a an active-low aynchronou reet and KEY 1 a a manual clock input. The um output hould be diplayed on red LEDR 7 light and the carry-out hould be diplayed on the red LEDR 8 light. 4. Aign the pin on the FPGA to connect to the witche and 7-egment diplay by importing the appropriate pin aignment file. 5. Compile your deign and ue timing imulation to verify the correct operation of the circuit. Once the imulation work properly, download the circuit onto the DE2-erie board and tet it by uing different value of A. Be ure to check that the Overflow output work correctly. 1

2 c 3 c 2 c 1 b n 6. Open the uartu II Compilation Report and examine the reult reported by the Timing Analyzer. What i the maximum operationcfrequency, out 3 f max, of 2 your circuit? 1 What i the longet path in the circuit in term of delay? a) Four-bit ripple-carry adder circuit A 8 Clock R 8 D overflow n 8 R Overflow S Figure b) Eight-bit 2: An eight-bit regitered accumulator adder circuit circuit. Part II Extend the circuit from Part I to be able to both add and ubtract number. To do o, add an add ub input to your circuit. When add ub i 1, your circuit hould ubtract A from S, and add A and S a in Part I otherwie. Part III Figure 3a give an example of paper-and-pencil multiplication P = A B, where A = 11 and B = x x p 7 p 6 p 5 x b b b p 4 b p 3 p 2 p 1 b p a) Decimal b) Binary c) Implementation Figure 3: Multiplication of binary number. We compute P = A B a an addition of ummand. The firt ummand i equal to A time the one digit of B. The econd ummand i A time the ten digit of B, hifted one poition to the left. We add the two ummand to form the product P = 132. Part b of the figure how the ame example uing four-bit binary number. To compute P = A B, we firt form ummand by multiplying A by each digit of B. Since each digit of B i either 1 or, the ummand are either hifted verion of A or. Figure 3c how how each ummand can be formed by uing the Boolean AND operation of A with the appropriate bit of B. 2

3 A four-bit circuit that implement P = A B i illutrated in Figure 4. Becaue of it regular tructure, thi type of multiplier circuit i called an array multiplier. The haded area correpond to the haded column in Figure 3c. In each row of the multiplier AND gate are ued to produce the ummand, and full adder module are ued to generate the required um. b p 7 p 6 p 5 p 4 p 3 p 2 p 1 p Figure 4: An array multiplier circuit. Perform the following tep to implement the array multiplier circuit: 1. Create a new uartu II project to implement the deired circuit on the Altera DE2-erie board. 2. Generate the required Verilog file, include it in your project, and compile the circuit. 3. Ue functional imulation to verify your deign. 4. Augment your deign to ue witche SW 11 8 to repreent the number A and witche SW 3 to repreent B. The hexadecimal value of A and B are to be diplayed on the 7-egment diplay HEX6 and HEX4, repectively. The reult P = A B i to be diplayed on HEX1 and HEX. 5. Aign the pin on the FPGA to connect to the witche and 7-egment diplay by importing the appropriate pin aignment file. 3

4 6. Recompile the circuit and download it into the FPGA chip. 7. Tet the functionality of your circuit by toggling the witche and oberving the 7-egment diplay. Part IV In Part III, an array multiplier wa implemented uing full adder module. At a higher level, a row of full adder function a an n-bit adder and the array multiplier circuit can be repreented a hown in Figure 5. b n-bit Adder b n-bit Adder b b3 n-bit Adder b p 7 p 6 p 5 p 4 p 3 p 2 p 1 p Figure 5: An array multiplier implemented uing n-bit adder. Each n-bit adder add a hifted verion of A for a given row and the partial um of the row above. Abtracting the multiplier circuit a a equence of addition allow u to build larger multiplier. The multiplier hould conit of n-bit adder arranged in a tructure hown in Figure 5. Ue thi approach to implement an 8x8 multiplier circuit with regitered input and output, a hown in Figure 6. 4

5 A 5 B 5 Clock D D Multiplier 1 DR Figure 6: A regitered multiplier circuit. P Perform the following tep: 1. Create a new uartu II project. 2. Write the required Verilog file, include it in your project, and compile the circuit. 3. Ue functional imulation to verify your deign. 4. Augment your deign to ue witche SW 15 8 to repreent the number A and witche SW 7 to repreent B. The hexadecimal value of A and B are to be diplayed on the 7-egment diplay HEX7-6 and HEX5-4, repectively. The reult P = A B i to be diplayed on HEX Aign the pin on the FPGA to connect to the witche and 7-egment diplay. 6. Recompile the circuit and download it into the FPGA chip. 7. Tet the functionality of your deign by toggling the witche and oberving the 7-egment diplay. 8. How large i the circuit in term of the number of logic element? 9. What i the f max for thi circuit? Part V Part IV howed how to implement multiplication A B a a equence of addition, by accumulating the hifted verion of A one row at a time. Another way to implement thi circuit i to perform addition uing an adder tree. An adder tree i a method of adding everal number together in a parallel fahion. Thi idea i illutrated in Figure 7. In the figure, number A, B, C, D, E, F, G, and H are added together in parallel. The addition A B happen imultaneouly with C D, E F and G H. The reult of thee operation are then added in parallel again, until the final um P i computed. 5

6 A B C D E F G H P Figure 7: An example of adding 8 number uing an adder tree. In thi part you are to implement an 8x8 array multiplier that compute P = A B. Ue an adder tree tructure to implement operation hown in Figure 5. Input A and B, a well a the output P hould be regitered a in Part IV. What i the f max for thi circuit? Preparation The recommended preparation for thi laboratory exercie include Verilog code for Part I through V. Copyright c 211 Altera Corporation. 6