Frequency Table Computation on Dataflow Architecture

Transcription

1 Frequency Table Computation on Dataflow Architecture P. Škoda *, V. Sruk **, and B. Medved Rogina * * Ruđer Bošković Intitute, Zagreb, Croatia ** Faculty of Electrical Engineering and Computing, Univerity of Zagreb, Zagreb, Croatia pkoda@irb.hr Abtract Frequency table computation i a key tep in deciion tree learning algorith. In thi paper we preent a novel implementation targeted for dataflow architecture implemented on field programmable gate array (FPGA). Conitent with dataflow model of computation, the kernel view input dataet a ynchronou trea of attribute and cla value. The kernel wa benchmarked uing key function from C4.5 program for deciion tree learning. For large dataet with many attribute over 100,000 ite, and over 60 attribute the realized kernel, clocked at 333 MHz, outperfor the oftware implementation running on CPU clocked at 3.2 GHz. Keyword frequency table, dataflow, field programmable gate array, deciion tree learning I. INTRODUCTION Hitogram computation i one of the fundamental procedure ued in many data mining algorith. It twodimenional extenion frequency table computation i a key part of the attribute election tep in deciion tree learning algorith [1]. Deciion tree learning algorith, a well a all other tool ued in data mining, are faced with ever-growing ize of analyzed dataet. Thi drive effort to parallelize exiting algorith, develop new algorith targeted for parallel and ditributed computer yte, and develop new hardware platfor that provide high computational power [2]. One platform that i now gaining more ground in computing application i field programmable gate array (FPGA). FPGA are digital integrated circuit deigned to be uer-configured after manufacturing [3], [4]. An FPGA comprie an array of configurable logic block, memory block, configurable interconnect, input/output (I/O) block, and variou pecialized arithmetic and communication block. Thee element together allow implementation of cutom computational architecture that can be reconfigured on demand. The computational model that FPGA i mot uitable for i the dataflow model. Majority of computer yte implement a controlflow model of computation. In control-flow, the computation i defined by a equence of operation that are executed in pecified order. In dataflow model, computation i defined by a chain of tranformation applied to a tream of data [5]. The dataflow i decribed patially in form of dataflow graph. Each operation i repreented by a node, and data flow between node i repreented by edge. Dataflow graph naturally map to hardware implementation. Operation are tranlated into hardware block that work concurrently, and edge are tranlated into data link. By dividing the graph into tage eparated by regiter, it i tranformed into a pipelined tructure uitable for implementing on FPGA. In thi paper we preent a novel implementation of frequency table computation targeted for dataflow architecture realized on FPGA. The kernel i developed for integration in C4.5 deciion tree learning program [6], [7]. Frequency table computation i a key tep in deciion tree learning algorith. It reult i ued to calculate dataet plit quality, uually Gini impurity or an entropy baed meaure uch a information gain, which i then ued for attribute tet election [1]. II. RELATED WORK Frequency table computation on FPGA ha been previouly publihed a a part of effort in implementing deciion tree learning algorith. FPGA have been proven to be uitable of implementing data mining algorith, though o far little attention ha been directed to deciion tree learning algorith. Only a few attempt of uing FPGA to accelerate execution of deciion tree learning have been reported [8], [9]. Chryo et al. [9] implement frequency table computation on FPGA a part of HC-CART ytem for learning deciion tree. Frequency table computation i implemented in Frequency Counting module. The module receive attribute-cla label pair. The pair are ued to generate addree for frequency table location which content are then incremented by one. The content of the frequency table are then copied over to other two auxiliary memorie, and ued to generate item frequencie for computing Gini impurity. In their implementation, all attribute-cla label received by the kernel have to be prepared by program running on CPU, and then preloaded to memory attached to FPGA. Input data i tranferred from CPU to FPGA memory many time in the coure of program execution. In our work, the data i tranferred to FPGA memory (LMem) only once, at the beginning of the program. The kernel read the data only from FPGA memory, and the only data tranfer between kernel and CPU i ending the computed frequency table to the CPU. MIPRO 2014/DC-VIS 357

2 TABLE I. FPGA Off-chip RAM (LMem) On-chip RAM (FMem) CPU FPGA bandwidth LMem FPGA bandwidth III. BASIC INFORMATION ON MAXELER VECTIS-LITE FPGA BOARD Xilinx Virtex-6 XCVSX475T 6 GiB (6 1 GiB) DDR2-800 SDRAM ~ 4 MiB Block RAM 2 GB/ 38.4 GB/ max. DATAFLOW ENGINE ARCHITECTURE The Data Flow Engine (DFE) i programmed with one or more kernel and a manager. Kernel implement computation. It define the computational architecture with calar and tream input and output. Manager organize data movement within the DFE. In manager, the kernel are intantiated and link to off-chip RAM (LMem), CPU or other DFE are defined. A. Maxeler Vecti-Lite FPGA platform Maxeler platform i deigned for implementing compute engine uing the dataflow model of computation. The platform comprie an FPGA board, driver, development tool, and API. Dataflow engine i decribed in Java, uing API which provide object and method that can be compiled into hardware tructure. The compiler tranlate the input Java code into VHDL code and create function that implement interface for CPU code [10]. Maxeler Vecti-Lite board wa ued for realization of the DFE on FPGA. The board i a PCIe expanion board which houe an FPGA, and SDRAM. Baic information on the board i hown in Table I. B. Kernel architecture Architecture of the ComputeFreq kernel i hown in TABLE II. FPGA RESOURCE USAGE BY THE DFE Reource Ued Total available Utilization LUT % Flip-flop % DSP block % Block RAM % Fig. 1. The kernel ha two calar input for parameter: tream length (trmlen), and number of ite (ite). Stream length i the number of element read from LMem, which require all memory accee to be made in 96 byte block. Number of ite i the actual number of ite of interet in the tream. The kernel receive two 32 bit unigned integer trea a input one for attribute value (att) and the other for cla value (attcla) of the ite. The input are liced o that the low N A bit are taken from attribute and N C bit from cla value. The liced input are concatenated to form the frequency table index, with. Frequency table i tored in block RAM (BRAM). The BRAM i addreed by the frequency table index formed from attribute and cla value. The value output from the BRAM i incremented by one and written back to the ame location. The BRAM i configured a a ingle port RAM with read-firt ynchronization. The compiler tool automatically inert regiter in appropriate location, which lead to latency inide the loop. To accommodate thi latency, kernel input trea are throttled to allow input of one element every m clock, where m i the length of loop latency. After all element of interet are treamed in, content of the BRAM are treamed out to the CPU through tream output and at the ame time reet to zero. Thi i achieved by uing multiplexer to witch BRAM addre port from table index to value generated by a counter. In the ame manner the BRAM write data port i witched from incremented-by-one value to contant zero. Since there are no loop dependencie in thi intance, the output tream i not throttled. One element i output every ingle clock. At the ame time, any remaining element in the input trea are read un-throttled (one per clock) and ignored. They are all read to enure proper functioning of the DFE. C. Manager A ingle ComputeFreq kernel i intantiated in manager. Stream input att and attcla are linked to LMem, and ue linear memory acce pattern. Stream output i linked to CPU. Scalar input ite and rtmlen are alo linked to CPU. The kernel parameter were et for up to 64 unique attribute and cla value (N A = 6, N C = 6). The manager clock frequency wa et at 100 MHz, while kernel clock frequency wa et at 333 MHz. DFE interface define input for ource addree of data for input trea att and attcla, value for calar input ite and rtmlen, and detination addre for output tream. Figure 1. ComputeFreq kernel architecture for up to 64 unique attribute and cla value (N A = 6, N C = 6). With given parameter, frequency table tore bit word. Loop latency of the yntheized deign i MIPRO 2014/DC-VIS

3 clock, which mean that the DFE can proce up to ite per econd. FPGA reource uage by the DFE i given in Table II. IV. EXPERIMENTAL RESULTS A. Benchmark and tet environment Kernel wa benchmarked by uing code from C4.5 Releae 8 deciion tree learning program [11]. The normal tree building feature from the original program were diabled. Only part required for loading dataet and computing the frequency table were left operational. A function wa added for tranforming dataet into format appropriate for DFE and writing it to LMem. Time meaurement wa added to ComputeFrequencie function. For execution on DFE, the ComputeFrequencie function wa modified to ue function call to the DFE, and copy the received reult into the original frequency table data tructure. From meaured execution time, the function throughput wa computed by: a i Ta, i = (1) t where a i number of attribute, i i number of ite, t a,i i meaured execution time, and T a,i i throughput for dataet with a attribute and i ite. A et of 84 dataet wa generated for the benchmark. All dataet have only nominal attribute with 63 unique attribute value (value from 1 to 63), and 64 unique cla value (from 0 to 63). Number of ite vary exponentially from to ( ) ite, while number of attribute varie exponentially from 1 to 64 ( ). Attribute and cla value are generated randomly uing uniform ditribution. Benchmark program wa compiled uing gcc compiler verion Benchmark were run on worktation with Intel Xeon E CPU running at 3.2 GHz, 16 GiB DDR RAM, under Cento 6.5 Linux OS. The worktation i equipped with Maxeler Vecti-Lite FPGA acceleration board. a, i Number of ite TABLE III MEASURED EXECUTION TIMES ON CPU Number of attribute / Execution time µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ B. ComputeFrequencie CPU benchmark reult Execution time on CPU are given in Table III, and are hown in Fig. 2. For input dataet larger than ite, execution time cale approximately linearly with number of ite. There i a harper increae in execution time viible for dataet with 8 or more attribute, in range for ite for 8 attribute, to ite for 64 attribute. Function throughput, hown in Fig. 3, more viibly illutrate thi decline in performance. Throughput rie with number of ite until a peak i reached at to ite, depending on number of attribute. After thi point it decline and quickly tabilize to a contant value. Contant throughput correpond to linear caling of execution time with number of ite. The larget contant throughput i ite per econd for dataet with 1 attribute, and the lowet i ite per econd for dataet with 64 attribute. Thi decline in performance i mot likely an effect of Figure 2. Execution time on CPU a function of number of ite, meaured for dataet with 1 to 64 attribute Figure 3. Throughput on CPU a function of number of ite, meaured for dataet with 1 to 64 attribute MIPRO 2014/DC-VIS 359

4 Figure 4. Execution time on DFE a function of number of ite, meaured for dataet with 1 to 64 attribute Figure 5. Throughput on DFE a function of number of ite, meaured for dataet with 1 to 64 attribute CPU cache ytem. Smaller et are le affected by cache mie than larger et. In addition, the dataet i tored in attribute major order. Since ComputeFrequencie function work by acceing the ame attribute over different ite, thi lead to conecutive accee to nonconecutive memory location, which are more likely to reult in cache mie. C. ComputeFrequencie DFE benchmark reult Meaured execution time on DFE are given in Table IV, and hown in Fig 4. Execution time cale linearly for dataet with more than ite. While caling i not linear for dataet with fewer ite, there i no performance drop like the one preent when executing on CPU. From throughput reult, hown in Fig 5, it i viible that there i little difference in throughput between dataet with different number of attribute, and that the main factor i number of ite. With and more ite, throughput i fairly contant at ite per econd, which i cloe to the theoretical maximum of Number of ite TABLE IV , , , , , , , , , , , ,75 MEASURED EXECUTION TIMES ON DFE Number of attribute / Execution time ,428 2,675 5,017 8,904 17,06 33,70 µ 1,507 2,771 5,041 9,456 17,74 35,69 µ 1,549 2,904 5,414 10,04 19,37 39,20 µ 1,730 3,481 6,489 12,18 23,96 46,55 µ 2,266 4,372 8,542 16,16 32,56 64,36 3,356 6,573 12,76 24,80 49,13 96,60 5,376 10,66 20,53 41,12 81,87 168,6 9,435 18,47 37,05 73,81 148,9 295,7 17,29 34,88 69,08 138,3 273,5 551,4 33,10 66,27 132,3 264,6 527,5 1,056 64,39 129,2 258,2 517,5 1,034 2, ,2 254,9 510,3 1,020 2,040 4, ite per econd. Lower performance with maller dataet i a conequence of overhead of control and communication with the DFE. Thi overhead i independent from number of ite in the dataet, but cale linearly with number of attribute, ince the ame et of function call ha to be made to proce each attribute. D. Comparion of the reult To compare the reult, ratio of execution time on CPU and time on DFE wa calculated. The ratio i hown in Fig 6. Execution on DFE i in mot cae ignificantly lower than on CPU. Thi i expected ince the DFE run on 333 MHz and work with DDR2 SDRAM clocked at 333 MHz, while CPU run on 3.2 GHz and work with DDR3 SDRAM clocked at 800 MHz. For mall dataet DFE i at wort 20 lower than CPU. However, DFE performance come cloer to the CPU a number of attribute and ite increae. For larget dataet (over ite), DFE i at wort 2.6 lower than CPU. For dataet with 64 attribute, DFE outperfor CPU when number of ite i larger than Bet performance 1.80 fater than CPU i reached when number of ite i larger than Figure 6. Ratio of execution time on CPU and DFE a function of number of ite, meaured for dataet with 1 to 64 attribute 360 MIPRO 2014/DC-VIS

5 V. CONLUSION In thi paper we have preented a novel implementation of frequency table computation on dataflow architecture. The architecture wa realized on FPGA platform. From benchmark reult it i clear that a ingle kernel DFE i outperformed by the CPU in mot circutance, but it doe provide better efficiency when their clock rate are accounted for. The CPU run at 3.2 GHz. It bet performance i ite per econd which give 18.5 clock per item. The DFE run at 333 MHz and it bet performance i at ite per econd which give 5.34 clock per item. Of the 5.34 clock per item, 4 are conequence of the BRAM-addermultiplexer-BRAM loop latency. There are way to deign around the in-loop latency. One approach i by replicating the BRAM-addermultiplexer tructure a many time a needed (in thi cae it 5 time), and demultiplex the input tream to each tructure. Once the input treaming i complete, the final reult i computed by umming the partial reult from each BRAM. Such deign could run with 1.34 clock per ite which would give ite per econd. Thi exceed maximum performance achieved on CPU. In future work, a multi-kernel verion of DFE will be developed which will allow imultaneou proceing of everal attribute. The kernel will be modified to lower the in-loop latency. Thi DFE i planned to be integrated with the C4.5 program a accelerator unit for proceing nominal attribute. Given preented reult, it i expected that the FPGA deign that exploit parallelim will outperform conventional CPU. ACKNOWLEDGMENT The reearch leading to thee reult ha received funding from the European Union Seventh Framework Programme (FP7), under grant agreement no E2LP Embedded Computer Engineering Learning Platform. REFERENCES [1] L. Rokach and O. Maimon, Data Mining with Deciion Tree: Theroy and Application. River Edge, NJ, USA: World Scientific Publihing, [2] A. N. Choudhary, D. Honbo, P. Kumar, B. Oziikyilmaz, S. Mira, and G. Memik, Accelerating data mining workload: current approache and future challenge in ytem architecture deign, Wiley Interdicip. Rev. Data Min. Knowl. Dicov., vol. 1, no. 1, pp , Jan [3] I. Kuon, R. Teier, and J. Roe, FPGA Architecture, Found. Trend Electron. De. Autom., vol. 2, no. 2, pp , [4] Mark L. Chang, Device Architecture, in Reconfigurable Computing: The Theory and Practice of FPGA-baed Computation, S. Hauck and A. DeHon, Ed. Morgan Kaufmann, 2008, pp [5] J. B. Denni, Data Flow Supercomputer, Computer, vol. 13, no. 11, pp , Nov [6] J. R. Quinlan, C4.5: Progra for Machine Learning. San Mateo: Morgan Kaufmann, 1993, p [7] S. Ruggieri, Efficient C4.5, IEEE Tran. Knowl. Data Eng., vol. 14, no. 2, pp , [8] P. Škoda, B. Medved Rogina, and V. Sruk, FPGA implementation of data mining algorith, in MIPRO, 2012 Proceeding of the 35th International Convention, 2012, pp [9] G. Chryo, P. Dagritziko, I. Papaeftathiou, and A. Dolla, HC- CART: A parallel ytem implementation of data mining claification and regreion tree (CART) algorithm on a multi- FPGA ytem, ACM Tran. Archit. Code Optim., vol. 9, no. 4, pp. 1 25, Jan [10] O. Pell and V. Averbukh, Maximum Performance Computing with Dataflow Engine, Comput. Sci. Eng., vol. 14, no. 4, pp , Jul [11] J. R. Quinlan, C4.5 Releae 8, [Online]. Available: [Acceed: 23-Jun- 2013]. MIPRO 2014/DC-VIS 361