Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories

Transcription

1 imulationbased Test Algoithm Geneation and Pot cheduling fo MultiPot Memoies ChiFeng Wu, ChihTsun Huang, KuoLiang Cheng, ChihWea Wang, and ChengWen Wu Depatment of Electical Engineeing ational Tsing Hua Univesity Hsinchu, Taiwan ABTRACT The pape pesents a simulationbased test algoithm geneation and test scheduling methodology fo multipot memoies. The pupose is to minimize the testing time while keeping the test algoithm in a simple and egula fomat fo easy test geneation, fault diagnosis, and builtin selftest (BIT) cicuit implementation. Conventional functional fault models ae used to geneate tests coveing most defects. In addition, multipot specific defects ae coveed using stuctual fault models. Potscheduling is intoduced to take advantage of the inheent paallelism among diffeent pots. Expeimental esults fo commonly used multipot memoies, including dualpot, foupot, and neadwite memoies, have been obtained, showing that efficient test algoithms can be geneated and scheduled to meet diffeent test bandwidth constaints. Moeove, memoies with moe pots benefit moe with espect to testing time.. ITRODUCTIO Multipot memoies ae commonly used components in VLI systems, such as egiste files in micopocessos, stoage fo media o netwok applications. The content of a multipot memoy can be accessed though diffeent pots simultaneously. This featue is especially valuable fo high speed pocessos, media pocessos, and communication pocessos. Howeve, multipot memoies equie moe testing effot since all pots have to be veified. A multipot memoy is usually tested as seveal singlepot memoies, which ae tested sepaately with test algoithms developed fo single pot memoies. This appoach is simple and easy to deploy, but thee ae two majo poblems with it. The fist is the lack of detection fo multipot specific defects that may occu in the memoy. Multipot memoies need to be veified with moe fault models elated to intepot defects. That makes the complexity of multipot fault models significantly highe than the complexity of singlepot fault models. The second is the inefficiency of the test pocedue, because the inheent paallelism of multipot memoies is not fully utilized duing testing. Test scheduling fo a singlepot memoy is tiv Pemission to make digital o had copies of all o pat of this wok fo pesonal o classoom use is ganted without fee povided that copies ae not made o distibuted fo pofit o commecial advantage and that copies bea this notice and the full citation on the fist page. To copy othewise, to epublish, to post on seves o to edistibute to lists, equies pio specific pemission and/o a fee. DAC 2, June 822, 2, Las Vegas, evada, UA. Copyight 2 ACM //6...$5.. ial, i.e., the entie test algoithm is applied to the one and only pot. When thee ae multiple pots, the test algoithm defines tests fo all pots. Cell faults, such as stuckat faults and tansition faults, ae testable though each one of the pots. On the othe hand, an intepot fault is moe difficult to test than a cell fault because the fault activation needs not only a specific addess, opeation, and data patten, but also a specific pot configuation. Test scheduling is impotant when testing multipot memoies because testing time can be significantly educed by pope test scheduling. Functional fault models and tests fo twopot memoies have been poposed in [, 2], The complexity of the tests is O( m ), whee is the size of the memoy, and m is the numbe of pots []. When the addess scambling scheme is known, the testing time can be educed to O(), but with a lage constant facto, e.g., anging fom 8 to 269 fo twopot memoies [2]. tuctual fault models, such as the adjacent bitline shot, has been used in [3 5]. In geneal, functional fault models coves moe defects, but equie longe testing time than stuctual fault models. tuctual fault models ae based on the cicuit stuctue of the memoy, theefoe deiving tests fo them need moe design infomation. Also, test pattens fo stuctual fault models ae usually not as egula as test pattens fo functional fault models. In this pape, we pesent a methodology that adopts both functional fault models and stuctual fault models. The pupose of ou methodology is to minimize the testing time while keeping the test algoithm in a simple and egula fomat of Mach test fo easy test geneation/scheduling, fault diagnosis, and builtin selftest (BIT) cicuit implementation [6 8]. eveal popula RAM fault models, such as stuckat faults, coupling faults, etc., ae used to cove most memoy defects, while stuctual fault models ae used to cove defects specific to multipot memoies. Pot scheduling is intoduced to futhe optimize the testing time. All test algoithms pesented in this pape have been veified with the the fault simulato that we have developed and constantly impoved, called RAME [9]. 2. FAULT MODEL AD DEFIITIO Fault models ae defined to cove defects in memoy cell aays, addess decodes, and ead/wite cicuits. Functional fault models and Mach algoithms ae widely used in the industy fo this pupose []. eveal popula fault models ae intoduced to demonstate ou methodology, including stuckat fault (AF), tansition fault (TF), addess decode fault (AF), stuckopen fault (OF), ead distubance fault (RDF), and coupling fault (CF), fo which we conside state coupling (CFst), invesion coupling (CFin), and idempotent coupling (CFid). Table shows seveal popula Mach algoithms, following the notation of []. Mach tests ae nomally shot and easy to geneate.

2 Table : ome Mach algoithms. ame Algoithm MAT++ m (); * (;); + (;;) Mach X m (); * (;); + (;); m () Mach Y m (); * (;;); + (;;); m () Mach C m (); * (;); * (;); + (;); + (;); m () FaultFee Faulty Addess α Cell α Pot A Addess α Cell α Addess β Cell β Addess α Cell α Pot B Addess β Cell β Addess β Cell β Figue 3: Functional behavio of an intepot bit line shot. tuctual fault models specific to multipot memoies ae intepot bidge o shot faults, including intepot wod line shots and intepot bit line shots. Figue shows a twopot memoy topology example, in which defects esult in a wod line shot and a bit line shot. The bit lines ae simplified as singleended fo easy eading, but we actually conside diffeential pais and all combinations of shots duing fault simulation. Intepot WL shot 3 2 β Intepot BL shot α γ Figue : Example of twopot memoy layout topology. When an intepot wod line shot occus as in Figue, one of the possible esults is shown in Figue 2. Addess 2 of pot B has a multiple access to Cell 2 and Cell 3 when pot A is accessing Cell. The esulting value of a ead to multiple cells depends on the memoy design: possible faulty esults ae the logicand o logico of the two cells. When an intepot bit line shot occus as in Figue, one of all possible esults is shown in Figue 3. Pot A Addess α has a multiple access to Cell α and Cell β, so has pot B Addess β. The esulting value of a ead to multiple cells depends on the memoy design: possible faulty esults ae the logicand o logico of the two cells. ote that Figue. 2 and 3 descibe possible esults because an intepot shot can lead to moe than one faults on the same bit line o wod line. Pot A Pot B Addess Addess 2 FaultFee Cell Cell 2 Addess Addess 2 Addess 3 Faulty Cell Cell 2 Cell 3 Figue 2: Functional behavio of an intepot wod line shot. Availability of the physical infomation detemines the complexity of intepot faults. When the addess scambling scheme is unknown, all possible ways of shot between all addesses have to be consideed. Fom Figue. 2 and 3, when the physical infomation is missing, the complexity of intepot wod and bit line shots ae O( 3 ) and O( 2 ), espectively, if they ae mapped to functional faults, i.e., addess decode faults. On the othe hand, given the addess scambling data, test algo ithms can be developed to detect most likely shots in the cicuit. The complexity is educed to the ode of the numbe of bit lines and wod lines, i.e., O( 2 ) to O(), depending on the aspect atio of the memoy layout. 3. TET TRATEGY A multipot memoy consists of multiple pots that access the same cell aay with thei own ead/wite cicuits and addess decodes. Applying a Mach test (such as Mach C ) on one pot can detect most defects in the memoy, including the cell aay, the pot s ead/wite cicuit and the pot s addess decode. Ou test stategy is to test the cell aay, ead/wite cicuits and addess decodes using functional fault models that have been welldeveloped fo single pot memoies. Intepot specific defects ae coveed using stuctual fault models. The specification of logical addess fields such as wod line select, bitline select, I/O select, etc., ae equied in ode to deive the addess tanslation. An example of addess tanslation is depicted in Figue 4. Logical Addess Physical Addess A B C D ow A wod line select B I/O select C bit line select D bit position in a wod column Figue 4: cambling. Addess A Data wod A bit3 bit2 bit bit 3 We popose a novel test patten that extends Mach algoithms to test stuctual fault models that involving neighboing cells on physical locations. The neighboing cells, called Mach guads, ae shown in Figue 5. Fo each addess, fou eads ae defined on its neighboing cells, denoted as,, E,and W, espectively. When eaching the bounday, a Mach guad can be eithe degaded to a noopeation (OP) o pushedback to the base (B) cell, depending on the implementation pefeence. The OP can be implemented as a dummy ead, i.e., a ead without compaison with the fault fee value. When degaded to a OP, the detection capability is slightly educed but can be ecoveed by pope potscheduling, which is explained in the next section. The expected value of a Mach guad depends on the addess sequence and the data backgound, as shown in Figue 5. When the addess sequence is ascending and the mach element changes the base cell fom to, the expected value fo and ae and, espectively. One o moe of the fou eads can be used in a Mach algoithm to detect memoy faults. Because of the egulaity of Mach tests, the expected value in ( ; ) o ( W ; E ) ae always complementay except on the bounday, theefoe they povide a good and simple mechanism fo checking line shots fo both ADtype and ORtype shots. Mach guads is an extension to conventional Mach tests. A

3 Mach test with guads fo a twopot memoy is illustated in Figue 6. The test algoithm is executed as a nomal MAT++ [] fo pot A. Two test elements of Mach guads, i.e.,( ; ) and ( W ; E ), ae applied to pot B. Fo pope scheduling of the test elements, a OP (shown as ) is used to match the timing. In M, when pot A executes (;), pot B executes ( ; ) using the same addess sequence, i.e., pot B is checking the adjacent cells. When Mach guads ae employed, ( W ; E ) detects wod line shots, while ( ; ) can detect wod line shots and bit line shots. In Figue, fo example, a ead fom α o β can detect the bit line shot, a ead fom γ can also detect the bit line shot, and a ead fom 2 can detect the wod line shot. In geneal, and ae moe vesatile, but W and E ae still useful fo cetain special conditions, such as boundaies. Thei applications will be demonstated late. W B E / Figue 5: Mach guads. / Append additional tests fo multiplepot specific faults, i.e., addess decode faults (AFs) fo each pot and intepot faults. Thee ae possibilities that these tests equie simultaneous opeations on two o moe ead/wite pots. Consequently, the phase consists of thee sections: the section of a singlepot complete test, the section of AFs, and the section of intepot faults, as shown in Figue 7. To detect multipot specific faults, one o moe Mach guads ae inseted, theefoe two o moe pots may be accessed simultaneously in the test sections 2 and 3, as indicated in the figue. Pot Pot m Mach Test ection ection 2 ection 3 inglepot Test Algoithm Multipot AF Test Intepot Test M M M 2 Pot A m () * (;) + (;;) Pot B ( ) ( ; ) ( W ; E ; ) Figue 6: Mach X with Mach guads extension. Pot Pot m inglepot Test Algoithm Multipot AF Test Intepot MPF Test 4. TET ALGORITHM GEERATIO To geneate test algoithms efficiently fo vaious achitectues of multipot memoies, a systematic methodology is poposed based on TAG, a simulationbased test algoithm geneato fo RAM [6]. Test algoithm geneation with pot scheduling is an extension to TAG, named TAGP. On fault simulation fo multipot memoies, seveal assumptions ae made:. Each memoy pot has a peset access pioity. When accessing an addess simultaneously fom moe than one pots, the opeations ae aanged accoding to the ode of access pioities, fom high to low. Fo simplicity, we assign the pot with the highest access pioity as pot, the next as pot 2, and so on. 2. imultaneous wites to an addess fom multiple pots ae consideed as invalid opeations. 3. Fo neadwite memoies, its wite pot and one of the ead pots ae combined into a ead/wite pai duing the opeation of cell fault detection. The wite pot is assigned pot, without loss of geneality. The test geneation methodology povides automatic test geneation by minimizing the testing time and guaantees the fault coveage. The test geneation algoithm consists of thee phases. The pocedue is stated as follows. An example will be given late fo dualpot memoies.. Base algoithm geneation Geneate a single pot complete test, i.e., a % fault coveage test fo all cell aay faults. The test is pefomed by accessing pot, initially. Figue 7: The complete test Pot scheduling and test eduction. 2. Pot scheduling Each test element in the base algoithm has cetain degee of feedom, i.e., thee may be othe elements that can achieve the same fault detection capability. Pot scheduling is to seach possible compaction ways to educe the testing time. Thepocedueisasfollows. Initial test set contains one o moe base algoithms. Fo each test in the test set, select one that contains all test elements in test sections 2 and 3. (c) each fo appopiate positions whee the selected element matches an element in test section. When the selected element is on pot i and i 6=, the matched element in section can be swapped with the test element in pot i only when it is a OP. A compact test is geneated by embedding the selected test element in test section and deleting it fom its oiginal position. All possible compact tests ae geneated and appended to the test set. (d) imulate each and evey test in the test set with RAM E [9], then delete incomplete tests. Complete tests ae soted by thei test length. A theshold value is set fo keeping additional tests that ae not the shotest test. The default theshold value is, i.e., only the tests with the shotest test length ae kept in the test set, othes ae deleted. (e) Repeat steps 2b to 2d using the new test set until no futhe compaction is possible. Repot the shotest test in the test set as the final test.

4 Test section of the base algoithm consists of test elements fo pot. Thee ae cetain degee of feedom fo test elements in othe test sections to be embedded in section since all pots except pot pefom OPs in section. Moeove, the test elements in pot can be swapped with othe pots with OPs, which inceases the degee of feedom fo futhe compaction. As indicated in Figue 7, the test algoithm is compacted afte the scheduling because the detection capability of test elements in vaious test sections ae ovelapped. The pot scheduling steps will be illustated in the following example. 3. Redundancy check Examine the edundancy among the test fo Mach opeations which pefom ead fo only one pot and pefom OP fo all othe pots, called dangling eads. each fo dangling eads and veify thei edundancy by RAME. Delete edundant opeations. Repeat until no futhe edundancy can be found. The detection capability of a dangling ead is likely to be coveed afte pot scheduling, e.g., the ead opeation fo detecting OF though pot can be emoved because of the insetion of Mach guads. Fo a common dualpot memoy, which has two sepaate ead/wite pots, the test geneation is illustated in Figue 8. Fistly, a 2 test is geneated to cove all AF, TF, OF, RDF, and CFs (see test section of Figue 8). A test fo AFs fo each ead/wite pot is geneated as test section 2, and an intepot specific test is geneated as test section 3. Afte the base algoithm is detemined, the potscheduling is pefomed. ffl Read/wite opeations in test section ae not esticted to the specific pot. The opeation can theefoe be swapped between diffeent pots with the same fault coveage. The pot swapping povides the degee of feedom fo the compaction of multiplepot opeations. Fo example, test section 3 can be diectly matched and embedded in test section, as shown in Figue 8. Test section 2 can only be embedded into test section afte the pot swapping of the two consecutive w opeation, esulting in the algoithm in Figue 8(c). Diffeent odes of compaction steps will alte the esult. In geneal, dealing with the test elements of intepot faults fist obtains bette esult than dealing with the test elements of AFs fist, because the constaints of testing AFs ae less stict and can be dealt with afte the compaction of othe tests. Howeve, all possible odeing can be applied to exploe the seach space fo bette esults. hote tests ae consideed as bette ones. ffl Moeove, some tests such as that fo intepot faults have altenatives. Figue 9 shows two equivalent pattens to detect the intepot shots between pot i and pot j. The pattens also have vaieties fo diffeent access diections o diffeent data backgounds. The vaiations incease the degee of feedom to geneate the final test. A possible patten combination fo all intepot shots is shown in Figue 9. The esult of pot scheduling helps deive altenatives depending on the choice of equivalent tests. Again, an optimized test is selected among diffeent altenatives, accoding to the simulation esults of RAME and the test lengths. Afte pot scheduling, some test elements may still have edundancy because cell aay faults may be coveed by Mach guads. The dangling eads ae examined fo edundancy because emoving the opeation and othe OPs will not affect coect timing. As in Figue 8(c) and (d), thee Mach opeations ae tested and two of them ae stipped. Consequently, a algoithm is geneated fo a dualpot memoy. Pot Pot Pot Pot ection 3 ection ection ection 2 ection ection 2 (c) (d) ection 2 ection 3 Figue 8: The complete test; Pot scheduling fo test section 3; (c) Pot scheduling fo test section 2; (d) Redundancy eduction. Pot Pot m Pot i Pot j w w O Figue 9: Test of intepot faults fo multipot memoies. The base algoithm geneation and the pot scheduling ae simple and systematic. In the base algoithm geneation, the taget fault models ae cell aay faults. Multipot addess decode faults and intepot specific faults ae detected in diffeent test sections. The sepaation of the taget faults significantly educes the complexity of automatic test geneation. Once the test is completed, TAGP can be used to compact the algoithm. The systematic methodology of pot scheduling pevents the test geneation fom complicated manual deivations. When including new intepot fault models, only the new test constaints ae equied fo geneating new test sections. RAME and TAG ae both easily extensible fo new fault models. 5. EXPERIMETAL REULT We demonstate the test geneation and pot scheduling esults with seveal commonly used multipot memoies, including dualpot, foupot, and neadwite memoies.

5 5. Dualpot memoies The test geneation fo dualpot memoies is aleady discussed in the pevious section. The final test is shown in Figue 8(d). The test length is. 5.2 Foupot memoies The test geneation methodology fo a dualpot memoy can be genealized fo othe multipot memoies, assuming each pot is a ead/wite pot. Afte pot scheduling, the oveall test algoithm is shown in Figue and the scheduling esult is highlighted. ote that the tailing ead element is emoved as opposed to the dualpot case, because the element becomes edundant afte the additional w elements fo addess decode faults ae inseted. Pot Pot 3 Pot 4 AF Test Intepot Test Figue : % test fo fou ead/witepot memoies. As the numbe of ead/wite pots inceases, the testing time is dominated by the test fo multipot AFs. The complexity of the Mach test fo multipot memoy is T()= whee m is the numbe of pots. ρ (4m+2) fo m = 2; (4m+) fo m > 2; 5.3 neadwite memoies Fo a memoy of one wite pot and seveal sepaate ead pots, the test elements of multipot specific faults ae diffeent fom that fo memoies of seveal ead/wite pots. The wite opeation can only be applied to the witeonly pot. Figue shows two test categoies to detect AFs in nead wite memoies. The use of W and E ae esticted. They can be used only when Mach guads ae pushed back to the base cell on the boundaies. Pot Pot i Pot j Pot k W E W E Pot Pot i Pot j Pot k E E W W Pot l W W E Figue : Test altenatives of addess decode faults fo n eadwite memoies. The wite opeation has to be applied though the wite pot (pot ), as shown in Figue. To detect the AFs of pot, tests of both pot and pot i ae equied. Fo AFs of ead pots, the combination test of pot and pot j, o pot and pot k is needed. Figue shows fou altenative test elements fo AF. The test elements of pot and pot i detects the AFs fo pot and i. The test elements of othe ead pots, togethe with the test elements of () pot, detects the AFs of pot j, k and l. All the thee pattens ae equivalent fo the AFs of the eadonly pots. imilaly, Figue 2 illustates the patten fo the detection of intepot faults between each ead pot and the witeonly pot. Fo the intepot faults between two ead pots, the patten in Figue 2 can be applied, with pope wite opeation of pot. Pot Pot i Pot j Pot k Figue 2: Test altenatives of intepot faults fo the nead wite memoies. Results fo 2eadwite and 6eadwite memoies ae shown in Figues 3 and 4, espectively. The time complexity can be summaized as 8 < T()= : 3 fo < n» 4; 5 fo 4 < n» 8; (+4 (blog nc+)) fo n > 8; whee n = m andm is the total numbe of pots. Pot w Pot 3 Figue 3: % test fo the 2eadwite memoies. M M M2 M3 M4 M5 M6 Pot Pot 3 Pot 4 Pot 5 Pot 6 Pot 7 Test fo pots of distance Test fo pots of distance 2 Test fo pots of distance 3 Figue 4: Pot scheduling of intepot faults fo the nead wite memoies. 6. DICUIO Fo simplicity, the above cases have been discussed fo bitoiented memoies. When test geneation is applied to a wodoiented memoy, the test algoithm consists of multiple data backgounds. The singlepot algoithm is a cocktail Mach test [6]. The test insetion fo addess decode faults and intepot faults ae simila to the pocedue fo bitoiented memoies. ote that fo wodoiented memoies, in addition to addess scambling, the data may also be scambled, as illustated in Figue 4. In this case, (2)

6 the Mach guads ae applied in paallel, theefoe the test is moe efficient than testing bitoiented memoies. Testing time compaison fo seveal commonly used multipot memoies ae listed in Table 2. The testing time ae linea with small constant factos. Thanks to the efficiency of pot scheduling, the testing time is shote than pevious woks, especially fo lage numbe of pots. Cetain hadtodetect cell faults that need specific test elements to detect, e.g., stuckopen o ead distubance, ae easie to detect with pot scheduling. Fo example, to test OF in a singlepot memoies, we need * (;;) o * (;;) in the test algoithm. With pot scheduling and Mach guads, these specific test elements ae no longe needed, since fault effects in the cell aay ae obsevable though othe pots. Ou methodology has a equiement that the addess scambling of the memoy coe must be available. Functional tests do not have this limitation because the scambling data is only used to lowe the complexity, i.e., fom O( m ) to O(), though it is not mandatoy. Howeve, even with the scambling data, the testing time is still vey long, e.g., most of them ae longe than [,2]. When the long testing time is affodable, complex functional tests may have high fault coveage on complex fault models. The investigation of complex fault models ae beyond ou discussion hee, i.e., we only compae ou appoach with ecent woks that adopt stuctual fault models fo multipot specific defects. Results in Table 2 show that TAGP geneates moe efficient tests than pevious woks when thee ae moe pots. Table 2: Testing time compaison (esults in [5] ae estimated fo the best case). Memoy type TAGP esults Zhao et al. [5] Dualpot mpot, m > 2 (4m+) (m 2) neadwite n > 3 fo < n» 4 5 fo 4 < n» 8 (+4 (blognc+)) fo n > 8 (n ) Test bandwidth is a common concen in pactice. To apply paallel testing on a multipot memoy, the need fo test bandwidth inceases popotionally to the pot numbe. When the test pins ae not enough to delive pattens simultaneously to all pots, tadeoffs have to be made between testing time and numbe of test pins by escheduling. Table 3 shows the escheduling esults when available test pins can povide paallel access to pots anging fom 2 to 6. In case only one pot can be accessed, the test will be degaded to testing each pot sepaately and suffes fom fault coveage loss on intepot faults. In Figue 5, we show a foupot escheduling with a limited test bandwidth fo only 2 pots accessed simultaneously. The testing time is inceased fom 7 to 25. Rescheduling can also educe the bandwidth equiements without testing time penalty in cetain cases, e.g., using 4 pots to test a 6pot memoy as shown in Table 3. Pope multiplexing o dispatching has to be aanged fo deliveing test pattens. Pot Pot 3 Pot 4 Table 3: Pot constaints and testing time. Total pots n Test pots P ae especially suitable fo this pupose, since the simplicity and egulaity of test opeations can educe the hadwae ovehead of the BIT cicuit. Moeove, the addess geneato fo Mach guads can be implemented easily, with a + o on the ow/column addesses. 7. COCLUIO A test algoithm geneation and pot scheduling methodology fo multipot memoies is poposed in this pape. The notion of simulationbased test algoithm geneation, Mach guads, and pot scheduling is intoduced and discussed in detail. The esulting tests ae efficient and costeffective. The egulaity and simplicity of TAGP make it especially suitable fo geneating test algoithms fo builtin selftest (BIT) implementations. Pot scheduling povides not only effective patten compaction but also be able to make tadeoffs between test bandwidth and testing time. Ou futue wok includes suppoting moe fault models, diagnosis algoithm geneation, and BIT designs fo multipot memoies. 8. REFERECE [] M. icolaidis, V. Casto Alves, and H. Bede, testing complex couplings in multipot memoies, IEEE Tans. VLI ystems, vol. 3, no., pp. 59 7, Ma [2] A. J. van de Goo. Hamdioui, Fault models and tests fo twopot memoies, in Poc. IEEE VLI Test ymp. (VT), 998, pp [3] T. Matsumua, An efficient test method fo embedded multipot RAM with BIT cicuity, in Poc. IEEE Int. Wokshop on Memoy Technology, Design and Testing (MTDT), 995, pp [4] Y. Wu and. Gupta, Builtin selftest fo multipot RAMs, in Poc. ixth IEEE Asian Test ymp. (AT), 997, pp [5] J. Zhao,. Iinki, M. Pui, and F. Lombadi, Detection of intepot faults in multipot static RAMs, in Poc. IEEE VLI Test ymp. (VT), 2, pp [6] C.F. Wu, C.T. Huang, K.L. Cheng, and C.W. Wu, imulationbased test algoithm geneation fo andom access memoies, in Poc. IEEE VLI Test ymp. (VT), Monteal, Ap. 2, pp [7] C.F. Wu, C.T. Huang, C.W. Wang, K.L. Cheng, and C.W. Wu, Eo catch and analysis fo semiconducto memoies using Mach tests, in Poc. IEEE Int. Conf. ComputeAided Design (ICCAD), an Jose, ov. 2, pp [8] C.T. Huang, J.R. Huang, C.F. Wu, C.W. Wu, and T.Y. Chang, A pogammable BIT coe fo embedded DRAM, IEEE Design & Test of Computes, vol. 6, no., pp. 59 7, Jan.Ma [9] C.F. Wu, C.T. Huang, and C.W. Wu, RAME: a fast memoy fault simulato, in Poc. IEEE Int. ymp. Defect and Fault Toleance in VLI ystems (DFT), Albuqueque, ov. 999, pp [] A. J. van de Goo, Testing emiconducto Memoies: Theoy and Pactice, John Wiley & ons, Chicheste, England, 99. Figue 5: A foupot test escheduling example. Builtin selftest (BIT) is a popula solution fo the test access/bandwidth poblem. The test algoithms geneated by TAG