XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers

Transcription

1 XFVHDL: A Tool fo the Synthesis of Fuzzy Logic Contolles E. Lago, C. J. Jiménez, D. R. López, S. Sánchez-Solano and A. Baiga Instituto de Micoelectónica de Sevilla. Cento Nacional de Micoelectónica, Edificio CICA, Avda. Reina Mecedes sn, Sevilla, SPAIN. Abstact A tool fo the synthesis of fuzzy contolles is pesented in this pape. This tool takes as input the behavioal specification of a contolle and geneates its VHDL desciption accoding to a taget achitectue. The VHDL code can be synthesized by means of two implementation methodologies, ASIC and FPGA. The main advantages of using this appoach ae apid pototyping, and the use of well-known commecial design envionments like Synopsys, Mento Gaphics, o Cadence. 1: Intoduction The two main factos that limit the ealization of an electonic system ae its complexity and its development time. The use of compute aided design envionments including synthesis eases the design pocess and acceleates the intoduction in the maket of the final poduct. Concening the design flow of a fuzzy logic contolle (FLC), two diffeent levels may be consideed. The algoithmic level specifies the functional behavio of the contolle. The objective within this level is to define the shape of the membeship functions, the implication mechanism, and the defuzzification stategy that bette achieve the poposed contol task. At the cicuit level, the designe has to select an efficient contolle achitectue, design the equied building blocks, and veify the tempoal behavio of the system. The use of VHDL as a language to suppot the data stuctues and functions equied fo simulation of fuzzy systems has been intoduced in diffeent efeences [1] [2]. In a pevious pape, the authos pesented a VHDL package which allows fomal desciption and simulation of fuzzy contolles, thus easing the algoithmic design of FLCs [3]. In this occasion ou wok is focused towads the implementation of FLCs as micoelectonic cicuits, making use of the capability of VHDL as input language fo most of the cuently available synthesis. This pape descibes a synthesis tool, Xfvhdl, that tanslates the high level epesentation of a fuzzy contolle in a synthesizable VHDL desciption suitable fo being implemented as a semi-custom application specific integated cicuit (ASIC), o as a field pogammable gate aay (FPGA). In the second case, the tool also povides scipt files to dive the synthesis pocess. 2: Implementation of fuzzy contolles Since fuzzy logic stated to be applied to solve contol poblems, an inceasing numbe of new applications diected to both industial and consume poducts has emeged [4]. Howeve, the use of fuzzy technologies in eal-time contol poblems demands the development of new pocessing stuctues which allow the efficient hadwae implementation of infeence mechanisms [5]. A low-cost high-speed achitectue fo fuzzy contolles was poposed by the authos in [6]. The keys fo achieving these equiements ae the adoption of some estictions in the shape of membeship functions, the use of simplified defuzzification methods, and the use of an active-ule diven infeence mechanism. The block diagam of this achitectue is depicted in Fig. 1, showing the thee typical components of a fuzzy infeence system. Membeship function cicuits (MFCs) at the fuzzifie stage calculate the degees of membeship fo the contolle inputs to the fuzzy sets that epesent the antecedents of the contol ules. Each MFC povides as many pais label-activation degee as ovelapping degee has been fixed fo the system. The infeence stage is composed of an active-ule selection cicuit (a counte-contolled multiplexe aay is used fo this pupose), a multiinput Min cicuit that evaluates the ule activation degee by combining the antecedent activation degees povided by the MFCs, and a ulebase that stoes the paametes which define the ule consequents. Thee ae diffeent options when designing each of the building blocks, with egad to the physical implementation of fuzzy contolles based in the heein descibed

2 Rule-Select Input 1 MFC MUX Input 2 MFC MUX RULE MEMORY c i w i DEFUZZIFIER Output Input 3 MFC MUX Counte MIN Fuzzifie Infeence Defuzzifie Fig. 1: Active-ule achitectue fo fuzzy contolles. achitectue. MFCs can be implemented esoting to eithe a vectoial o aithmetic appoach. Memoy based MFCs (Fig. 2a) allow a definition of unesticted membeship shapes, but aithmetic appoaches (Fig. 2b) povide, in geneal, bette esults in tems of silicon aea. The ule memoy at the infeence stage can be implemented by a RAM, in ode to impove the contolle pogammability, o by means of a ROM o a combinational cicuit to educe the aea consumption. Lastly, diffeent defuzzification stategies can be consideed in the final stage of the contolle [7]. The hadwae ealization of most simplified defuzzification methods (Fuzzy Mean, Weighted Fuzzy Mean, Yage, Cente of Sums) equies one of the fou stuctues depicted in Fig 3. Note that sections enclosed by dotted lines ae common to all the stuctues, enabling the constuction of a multifunctional defuzzification cicuit [6]. The choice among these design options depends on the application domain of the fuzzy contolle and the implementation technique used to build the integated cicuit. RAM implementations of MFCs and the ulebase may be a good altenative fo a geneal pupose pogammable fuzzy contolle. Convesely, the use of ROM o combinational blocks to stoe the knowledge base is bette suited when the contolle specifications ae well established, o when the pogammability is diectly achieved by the implementation technique (as in the case of FPGAs). On the othe hand, the numbe of cicuits can affect the technology to be employed. FPGAs ae a good solution fo fast pototyping, while the cost of a high-volume poduction should suggest the use of semi-custom ASICs. In ode to acceleate the design pocess, it is helpful to have a design envionment which allows the exploation of the design space and eases the automatic synthesis and veification of fuzzy hadwae. L 1 L 2 L 4 L 5 L 1 L 2 L 3 L 5 L 6 L 7 x x 1 x 2 x 3 x 4 x 5 x 6 x 7 Label MEM-0 L 1 L 2 L 3 L 4 Clock Count x ι m ι Not L i -1 MEM-1 Input - X Reg (a) (b) Fig. 2: Implementation of MFCs by vectoial (a), and aithmetic (b) appoaches.

3 p i c i q X i α y i X + X y (a) ŷ = c i (c) ŷ = ( p i + q i ) c i w i X X y c i -1 X -1 X y (b) ŷ = w i c i w i (d) ŷ c 2 i 1 β 2 = i 1 β i Fig. 3: Block diagams fo diffeent defuzzification methods: a) Fuzzy Mean. b) Weighted Fuzzy Mean. c) Yage. d) Cente of Sums with min implication. Whee is the activation degee, c i is the cisp consequent, w i is a weight paamete, p i and q i ae shaping factos, and β -. 3: The Xfvhdl tool Xfvhdl geneates a synthesizable VHDL desciption of a fuzzy contolle fom its high-level epesentation in the XFL language [8]. The XFL specification (Fig. 4) includes infomation about the behavio of the FLC (knowledge base, infeence mechanism and defuzzification method). The design flow of FLCs using Xfvhdl is illustated in Fig 5. Xfvhdl uses a cell libay containing the paameteized VHDL desciption fo the basic building blocks. Thee ae two kind of blocks: data path building blocks (implementing the infeence algoithm) and contol blocks (contolling the memoy witeead opeations, and the signals that contol the opeation scheduling). The code used in the desciption of the cell libay is compatible with the esticted VHDL implementations of Synopsys and Mento Gaphics. The achitectual options and the numbe of bits of pecision ae defined by the use when the Xfvhdl command is un. Xfvhdl poduces as output the following files descibing the FLC: #and min #composition max #defuzzification FuzzyMean type Teo : eal [64] (-1<1) { NN tiangle (-1.5,-1,0) ZZ tiangle (-1,0,1) PP tiangle (0,1,1.5)} type Tdeltae : eal [64] (-1<1) { NN tiangle (-1.5,-1,0) ZZ tiangle (-1,0,1) PP tiangle (0,1,1.5)} type Toutput : eal [64] (0<1) { NG tiangle (-0.5,0,0.25) NP tiangle (0,0.25,0.5) ZZ tiangle (0.25,0.5,0.75) PP tiangle (0.5,0.75,1) PG tiangle (0.75,1,1.5)} system (Teo? eo, Tdeltae? deltae,toutput! output) ulebase { if (eo is NN & deltae is NN) -> output is ZZ if (eo is NN & deltae is ZZ) -> output is NP if (eo is NN & deltae is PP) -> output is NG if (eo is ZZ & deltae is NN) -> output is PP if (eo is ZZ & deltae is ZZ) -> output is ZZ if (eo is ZZ & deltae is PP) -> output is NP if (eo is PP & deltae is NN) -> output is PG if (eo is PP & deltae is ZZ) -> output is PP if (eo is PP & deltae is PP) -> output is ZZ } Fig. 4: XFL desciption of a fuzzy contolle.

4 XFL Fuzzy System desciption Xfvhdl Implementation options VHDL testbench VHDL contolle VHDL packages VHDL memoies desciption VHDL components libay Synthesis scipt file FPGA Synopsys fuzzy.sxnf file. Contolle desciption Routing and timing epot Synthesis Schematic. desciption ASIC Foundy technology libay fuzzy.lca file Xilinx fuzzy.bit file Hadwae cost epot Layout Cicuit layout Fig. 5: Design flow fo the implementation of FLCs using Xfvhdl. Package files: Two VHDL packages ae geneated by Xfvhdl. The constants file includes the declaation of the constants used in the VHDL desciption. Some of these constants ae obtained diectly fom the paametes of the Xfvhdl command. Othes ae obtained by analyzing the XFL desciption. The last set of paametes is calculated fom the othe two. On the othe hand, the entities file contains the declaation of all the blocks that make up the FLC. The instantiation of each block depends on the achitectual options selected. Knowledge base files: The infomation about antecedents, ules and consequents is codified in a set of files. The definitions ae based in tables of values by means of VHDL case sentences, thus enabling logic minimization when these blocks ae implemented as combinational logic. Contolle file: This file contains the stuctual VHDL desciption of the FLC. The contolle is constucted by concatenating a set of basic building blocks accoding to the XFL desciption and the implementation options. TestBench file: In addition to the files equied by the synthesis pocess, a testbench file is geneated to ease the veification of the FLC. The testbench includes the instantiation of the FLC, a pocess to geneate a peiodical clock signal, and anothe pocess that povides the initial eset signal and the inputs used in the simulation of the FLC. The files geneated by Xfvhdl can be used as the stating point fo automatic synthesis which povide diffeent implementation techniques fo integated cicuits. One of the pimay decisions in the design pocess is the selection of the taget implementation style. This selection depends on specifications o is based on economical equiements. Late design steps ae stongly affected by this choice. Fig. 5 shows the two implementation methodologies maked by dotted lines. The next section descibes the ealization of seveal pototypes of ASICs and FPGAs, espectively. In the last case, a scipt file povided by Xfvhdl can dive the synthesis when Synopsys is the selected tool and Xilinx the objective technology. Xfvhdl can be executed inteactively o fom the Xfuzzy gaphical envionment [8]. Fig 6 shows the command line and some Xfvhdl window with its command options. Thee ae moe options, not shown, to guide the Synopsys synthesis step.

5 Fig. 6: Xfvhdl gaphical use inteface showing its main command options. 4: Implementation examples The ASIC design appoach fo the achitectual component modelling is based on technology mapping citeia. In this sense, FLC implementation equies standad cell and macocell selection. The VHDL files povided by Xfvhdl ae used by the synthesis tool to geneate the schematic desciption of the contolle accoding to the selected foundy libay. This schematic is used by place and outing to obtain the cicuit layout. An impotant aspect in the design of ASICs is to adjust the cicuit to the equied pefomance unde cost and timing constaints. To be able to do this, the designe needs an efficient tool to exploe the design space. This is one of the main featues of Xfvhdl since its stating point is a highlevel behavioal desciption. Fig. 7 shows fou ASIC implementation examples of a fuzzy contolle with vaying design paametes. The contolle equiements ae: two inputs and one output, 7 membeship functions, and Fuzzy Mean defuzzification method (eq. (a) of Fig. 3). The figue shows the layout and silicon aea of fou cicuits (implemented in a 0.7 µm CMOS technology) based on aithmetic o memoy MFCs, with a diffeent numbe of bits fo inputs and membeship gade coding. Xfhvdl allows fo anothe altenative implementation fo fuzzy contolles, based on Xilinx FPGAs. In ode to contol the design steps, Xfvhdl geneates a scipt file fo Synopsys to select the synthesis options. The output of Synopsys is an XNF file (Xilinx Netlist Fomat) named fuzzy.sxnf with the contolle desciption. Optionally it is possible to geneate a epot file containing outing equiement (numbe of CLBs and IOBs) and tempoal constaints. Finally, fuzzy.sxnf is used as the input file fo Xilinx softwae fo mapping and outing the FPGA. Thee files ae obtained as esult: fuzzy.lca, fuzzy.bit and the epot of the implementation ( in file fuzzy.pt ). The last step is to wite the FPGA using the file fuzzy.bit, to obtain the physical implementation of the fuzzy system fom the behavioal XFL desciption. Table 1 shows FPGA implementations of the contolles depicted in Fig. 7. Case D exceeded the 4013PQ160-5 FPGA size. As mentioned above, the output geneated by Xfvhdl consists of a schematic VHDL fo the contolle. 5: Conclusions. Hadwae ealizations of fuzzy contolles can be impoved by using adequate design envionments which speed up the pocesses of design, synthesis and veification of these contolles. A CAD tool focused in the automatic synthesis of fuzzy contolles has been descibed in this pape. The tool is based on the standad hadwae desciption language VHDL. The viability of the poposed method is shown though its pactical application.

6 Aithmetic based MFC Memoy based MFC 4 bits inputs 5 bits membeship gade A) Aea = 5.05 mm 2 B) Aea = 5.83 mm 2 10 bits inputs 11 bits membeship gade C) Aea = mm 2 D) Aea = mm 2 Fig. 7: Examples of the design space evaluation of fuzzy contolles. A B C FPGA 4005PC PC PQ160-5 Numbe of CLBs 162 (82% used) 124 (63% used) 402 (69% used) Numbe of IOBs 16 (26% used) 16 (26% used) 34 (26% used) CLB Flip Flops 116 (29% used) 107 (27% used) 220 (19% used) Table 1: FPGA implementation fo the contolles in Fig 7. 6: Refeences [1] A. Zamfiescu and C. Ussey, VHDL and Fuzzy Logic If- Then Rules, Poc. of Euo-VHDL 92, pp , Hambug. [2] T. Hollstein, S.K. Halgamuge and M. Glesne: Compute- Aided Design of Fuzzy Systems Based on Geneic VHDL Specifications, IEEE Tans. on Fuzzy Systems, vol. 4, no. 4, pp , Nov [3] D. Galán, C.J. Jimenez, A. Baiga and S. Sánchez-Solano: VHDL Package fo Desciption of Fuzzy Logic Contolles, EURO-VHDL 95 Bighton, pp , Sept [4] T. Munakata, Y. Jani, Fuzzy Systems: An Oveview, Communications of the ACM, vol. 37, n. 3, pp , Ma [5] D. L. Hung. Dedicated Digital Fuzzy Hadwae. IEEE Mico, vol. 15, n. 4, pp , Aug [6] C.J. Jiménez, S. Sánchez-Solano and A. Baiga: Hadwae Implementation of a Geneal Pupose Fuzzy Contolle. Poc. 6th Intenational Fuzzy Systems Association Wold Congess (IFSA 95), Sao Paulo, July [7] H. Hellendoon and C. Thomas, Defuzzification in Fuzzy Contolles, Jounal of Intelligent and Fuzzy Systems, vol. 1, pp , [8] D. R. López, S. Sánchez-Solano, A. Baiga: XFL: a fuzzy logic systems language. Poc. sixth IEEE Intenational Confeence on Fuzzy Systems, vol. 3, pp , Bacelona, 1997.