Lecture Topics ECE 341. Lecture # 12. Control Signals. Control Signals for Datapath. Basic Processing Unit. Pipelining

Transcription

1 EE 341 Lectue # 12 Instucto: Zeshan hishti zeshan@ece.pdx.edu Novembe 10, 2014 Potland State Univesity asic Pocessing Unit ontol Signals Hadwied ontol Datapath contol signals Dealing with memoy delay Pipelining asic oncept Pipeline Oganization Lectue Topics Refeences: hapte 5: Section 5.5 and 5.6 (Pages of textbook) hapte 6: Sections 6.1 and 6.2 (Pages of textbook) ontol Signals ontol signals goven the opeation of a pocesso s components ontol cicuity examines the instuction in IR and geneates the contol signals needed to execute the instuction Examples of decisions made by contol signals: Which egistes (if any) ae enabled fo witing? Which input is selected by a multiplexe? What opeation is pefomed by the LU? Some contol signals depend only on instuction type, while othes depend on both the instuction type and cuent pocessing step ontol Signals fo Datapath Need contol signals fo egiste file, multiplexes and LU Inte-stage egistes tansfe data fom one stage to the next in evey cycle => no need fo a contol signal, since these egistes ae always enabled IR ddess IR ddess LU_op Y_select k In Registe File R _select LU Out RZ RF_wite IR R In 2 MuxY RY ddess Imm. Value Mux... Memoy ddess Retun ddess IR Mux 5 ondition signals RM Memoy Data LINK 2 _select

2 ontol Signals fo Memoy Inteface and IR ontol Signals fo Instuction ddess Geneato Extend 2 Immediate IR_enable IR M_select RZ P MuxM P_select P_enable R MuxP P 4 Immediate Value (anch Offset) MuxIN Mux and MuxIN RM MEM_ead MF IN_select Data MEM_wite ddess P-Temp Pocesso Memoy Inteface MuxY (Retun ddess) dde To cache and main memoy Hadwied ontol Geneation of ontol Signals How does the pocesso ensue that the contol signals needed to execute an instuction ae geneated in the coect sequence and at the ight time? Two basic appoaches: (1) Hadwied contol, (ii) Micopogammed contol The contol signals depend on the cuent pocessing step fo an instuction Question:How do we keep tack of the cuent step of an instuction? nswe: use a step counte Question: What othe factos do the contol signals depend on? nswe: ontents of instuction egiste The esult of a computation (o compaison) opeation Extenal input signals, such as inteupt equests Decode sets one of the INSioutputs, based on instuction type One of the outputs is set, based on cuent pocessing step

3 Geneation of ontol Signals (cont.) Datapath ontol Signals Example: onside the fetch stage (stage 1) of the five-stage hadwae Step counte assets the signal T1 ontol cicuity: sets M_select signal to 1 to select P contents as memoy addess activates Mem_Read to initiate a memoy ead opeation activates IR_enable to load the data etuned fom memoy into IR, when MF is asseted setsinc_selectto 0, P_selectto 1 and assets P_enableto incement P by 4 at the end of step T1 Setting of contol signals can be detemined by examining the actions taken in each execution step of evey instuction Example 1:RF_witesignal is set to 1 in step T5 duing an instuction that wites data into the egiste file: RF_wite= T5.(LU + Load + all) whee LU, Loadand all stand fo aithmetic/logic instuctions, load instuctions and suboutine call instuctions espectively RF_wite is a function of both the timing and instuction signals Example 2: The multiplexe _selectis a function of onlythe instuction and does not need to change fom one timing step to the othe _select = Immediate whee Immediatestands fo all instuctions that use an immediate opeand Dealing with Memoy Delay The step counte is usually incemented at the end of evey clock cycle Howeve, a step in which a Mem_Reado Mem_Witeis issued does not end until the MF signal is asseted Step counte should not be incemented until the MF signal is asseted ounte_enable signal contols whethe the step counte is incemented Let WMF be a contol signal that epesents the need to wait fo memoy WMF is activated only in those steps in which the Wait_fo_MF command is issued ounte_enable = NOT(WMF) + MF We must also ensue that P is incemented only once when the instuction fetch step is extended fo moe than one clock cycle P_enable signal contols if the P is incemented o not P_enable = T1.MF + T3.R whee R stands fo all the banch instuctions Pipelining

4 Oveview Taditional Pipelining oncepts So fa, we have assumed that only oneinstuction is being pocessed by the multi-stage hadwae at any point of time How do we decease the execution time of a pogam? One possibility is to use faste cicuits to implement the pocesso This appoach will decease the execution time of each instuction nothe possibility is to aange the pocesso hadwae in such a way that multipleinstuctions can be pocessed at the same time. This appoach is called pipelining Laundy Example Fou loads of laundy need to be washed, died and folded Washe takes 30 minutes D Pipelining does not change the time needed to pefom a single instuction, but it inceases the numbe of instuctions pefomed pe second (instuction completion ate o thoughput) Dye takes 40 minutes Folde takes 20 minutes Taditional Pipelining oncepts (cont.) Taditional Pipelining oncepts (cont.) 6 PM Midnight 6 PM Midnight T Sequential laundy takes 6 hous fo 4 loads If pipelining is used, how long would laundy take? a s k O Pipelined laundy takes 3.5 hous fo 4 loads d D e D

5 Taditional Pipelining oncepts (cont.) Pipelining in a 5-stage Pocesso T a s k O d e 6 PM D Pipelining doesn t educe the time taken by an individual task, it impoves the thoughput of entie wokload Task completion ate limited by slowest pipeline stage Potential speedup = Numbe of pipeline stages Unbalanced lengths of pipeline stages educes speedup to fill pipeline and time to dain it futhe educes speedup lock ycle I j I j+1 I j+2 Fetch Decode ompute Memoy Witeback Fetch Decode ompute Memoy Witeback Fetch Decode ompute Memoy Witeback t any given time, a diffeent instuction is being pocessed by each pipeline stage How do we ensue that each stage has the coect inputs that it needs to pocess a paticula instuction? Infomation needed by an instuction is caied though the pipeline, as the instuction poceeds fom one stage to the next This infomation is held in inte-stage buffes Read the details of each intestage buffe in Section 6.2 Infomation needed to pocess the instuction Pipeline Pefomance Example: pogam consisting of 500 instuctions is executed on a 5-stage pocesso. How many cycles would be equied to complete the pogam, (i) without pipelining, (ii) with pipelining? ssume idealovelap in case of pipelining. Solution: Without pipelining:each instuction will equie 5 cycles. Thee will be no ovelap amongst successive instuctions. Numbe of cycles = 500 * 5 = 2500 With pipelining:each pipeline stage will pocess a diffeent instuction evey cycle. Fist instuction will complete in 5 cycles, then one instuction will complete in evey cycle, due to ideal ovelap. Numbe of cycles = 5 + ((500-1)*1) = 504 Speedup fo ideal pipelining = 2500/504 = 4.96 (o appox. 5)

6 Pipeline Pefomance (cont.) The potential incease in pefomance esulting fom pipelining is popotional to the numbe of pipeline stages Howeve, this incease would be achieved only if all pipeline stages equie the same time to complete, and thee is no inteuption thoughout pogam execution Unfotunately, this is not tue thee ae times when an instuction cannot poceed fom one stage to the next in evey clock cycle I j+2 Pipeline Pefomance (cont.) lock ycle I j I j+1 F D M W F D M W 8 9 F D M W ssume that Instuction I j+1 is stalledin the decode stage fo two exta cycles This will cause I j+2 to be stalled in the fetch stage, until I j+1 poceeds New instuctions cannot ente the pipeline until I j+2 poceeds past the fetch stage afte cycle 5 => execution time inceases by two cycles