The Processor: Improving Performance Data Hazards

Transcription

1 The Pocesso: Impoving Pefomance Data Hazads Monday 12 Octobe 15 Many slides adapted fom: and Design, Patteson & Hennessy 5th Edition, 2014, MK and fom Pof. May Jane Iwin, PSU

2 Summay Pevious Class Pipeline Today: Reducing pipeline data hazads Fowading Stalls 2

3 Can Pipelining Get Us Into Touble? Pipeline Hazads - Situations that pevent stating the next instuction in the next cycle stuctual hazads: attempt to use the same esouce by two diffeent instuctions at the same time data hazads: Deciding on contol action depends on pevious instuction An instuction s souce opeand(s) ae poduced by a pio instuction still in the pipeline contol hazads: attempt to make a decision about pogam contol flow befoe the condition has been evaluated by a pevious instuction banch and jump instuctions, exceptions Can usually esolve hazads by waiting (stall) pipeline contol must detect the hazad and take action to esolve hazads 3

4 Review: Registe Usage Can Cause Data Hazads Read befoe wite data hazad Value of $ / add $1, sub $4,$1,$5 and $6,$1,$7 o $8,$1,$9 xo $4,$1,$5 4

5 One Way to Fix a Data Hazad - Stall I n s t. add $1, stall Can fix data hazad by waiting stall but impacts CPI O d e stall sub $4,$1,$5 and $6,$1,$7 5

6 Anothe Way to Fix a Data Hazad - Fowading One Way to Fix a Data Hazad - Stall I n s t. add $1, sub $4,$1,$5 Fix data hazads by fowading esults as soon as they ae available to whee they ae needed O d e and $6,$1,$7 o $8,$1,$9 xo $4,$1,$5 6

7 Data Fowading (aka Bypassing) Take the esult fom the ealiest point that it exists in any of the pipeline state egistes and fowad it to the functional units (e.g., the ) that need it that cycle Fo functional unit: the inputs can come fom any pipeline egiste athe than just fom ID/EX by adding multiplexos to the inputs of the connecting the Rd wite data in EX/MEM o MEM/WB to eithe (o both) of the EX s stage Rs and Rt mux inputs adding the pope contol hadwae to contol the new muxes Othe functional units may need simila fowading logic (e.g., the DM) With fowading can achieve a CPI of 1 even in the pesence of data dependencies 7

8 Fowading Paths 8

9 Fowading Illustation I n s t. add $1, sub $4,$1,$5 O d e and $6,$7,$1 EX fowading MEM fowading 9

10 Fowading - Anothe Complication! Anothe potential data hazad can occu when thee is a conflict between the esult of the WB stage instuction and the MEM stage instuction which should be fowaded? I n s t. O d e add $1,$1,$2 add $1,$1,$3 add $1,$1,$4 10

11 Datapath with Fowading and Contol 11

12 Memoy-to-Memoy Copies Fo loads immediately followed by stoes (memoy-tomemoy copies) can avoid a stall by adding fowading hadwae fom the MEM/WB egiste to the data memoy input. Would need to add a Fowad Unit and a mux to the MEM stage I n s t. O d e lw $1,4($2) sw $1,4($3) 12

13 Fowading with Load-use Data Hazads I n s t. O d e lw $1,4($2) stall sub $4,$1,$5 sub and $4,$1,$5 $6,$1,$7 and o $6,$1,$7 $8,$1,$9 xo $8,$1,$9 $4,$1,$5 xo $4,$1,$5 IM Reg DM 13

14 Code Scheduling to Avoid Stalls Reode code to avoid use of load esult in the next instuction C code fo A = B + E; C = B + F; stall stall lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 13 cycles lw $t1, 0($t0) lw $t2, 4($t0) lw $t4, 8($t0) add $t3, $t1, $t2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 11 cycles 14

15 How to Stall the Pipeline Foce contol values in ID/EX egiste to 0 EX, MEM and WB do nop (no-opeation) Pevent update of PC and IF/ID egiste Using instuction is decoded again Following instuction is fetched again 1-cycle stall allows MEM to ead data fo lw Can subsequently fowad to EX stage 15

16 Stall/Bubble in the Pipeline Stall inseted hee 16

17 Stall/Bubble in the Pipeline O, moe accuately 17

18 Datapath with Hazad Detection 18

19 Stalls and Pefomance The BIG Pictue Stalls educe pefomance But ae equied to get coect esults Compile can aange code to avoid hazads and stalls Requies knowledge of the pipeline stuctue 19

20 Conclusion All moden day pocessos use pipelining fo pefomance a CPI of 1 and faste CC Pipeline clock ate limited by slowest pipeline stage designing a balanced pipeline is impotant Must detect and esolve hazads Stuctual hazads esolved by designing the pipeline coectly Data hazads Stall (impacts CPI) Fowad (equies hadwae suppot) 20

21 Next Class Reducing pipeline contol hazads Exceptions and Inteupts 21

22 The Pocesso: Impoving Pefomance Data Hazads Monday 12 Octobe 15 Many slides adapted fom: and Design, Patteson & Hennessy 5th Edition, 2014, MK and fom Pof. May Jane Iwin, PSU