Hexagonal Pixel Grid Modeling for Edge Detection and Design of Cellular Architecture for Binary Image Skeletonization

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1 Hexagonal Pixel Grid Modeling for Edge Detection and Design of Cellular Architecture for Binary Image Seletonization M. Senthilnayai, S. Veni, and K.A. Narayanan Kutty Abstract-- Digital images can be represented by rectangular pixel grid model. Yet an alternate model paradigm using a hexagonal pixel grid can be used to discretize and process images which are more suitable for computer vision modeling. The merits of using hexagonal lattice are superior symmetry, definite neighborhood and fewer samples are needed compared to a rectangular lattice. This paper elucidates the sub sampling procedure needed to obtain the hexagonally sampled image from the conventional rectangularly sampled image. Two image processing operations namely edge detection and image seletonization were done on hexagonal lattice and also rectangular lattice for comparison. The algorithm used for the edge detection of sub sampled images is based on CLAP (Cellular logic Array Processor) algorithm. Image Seletonization was done using iterative thinning method which is better suited for VLSI Implementation. The paper further deals with the design and implementation of a Cellular Processor Array (CPA) that executes binary image seletonization on a hexagonal lattice. The implementation shows better results compared to the existing methods. Index Terms Cellular Processor Array, Cellular Logic Array Processor, Edge diction, Hexagonal grid, Image seletonization. Nomenclature I. INTRODUCTION To represent images or objects in a digital computer, they must be discretized. Rectangular pixel grid model is normally used to represent images in digital domain. However an alternate paradigm using a hexagonal pixel grid can also are used to digitize and process images [2]. The primary motivation behind using a hexagonal grid is that the retina of the eye closely resembles a hexagonal grid space. Numerous other advantages have been associated with hexagonal grid M. Senthilnayai is a lecturer in the Department of Electronics and Communication Engineering, Amrita school of Engineering, Ettimadai, coimbatore, Tamilnadu, India. ( senthi_@yahoo.co.in). S. Veni is an Assistant Professor in the Department of Electronics and Communication Engineering, Amrita school of Engineering, Ettimadai, coimbatore, Tamilnadu, India. ( s_veni@ettimadai.amrita..edu). Dr. K. A. Narayanan Kutty is a Professor in the Department of Electronics and Communication Engineering, Amrita school of Engineering, Ettimadai,coimbatore,Tamilnadu,India. (e- mail:a_narayananutty@ettimadai.amrita..edu) /6/$2. 26 IEEE representation namely symmetry, well-behaved connectivity, improved angular resolution, storage savings, speed, circular 7-pel shape, and pixels have nearly circular shape. Thus by modeling and processing images on such a grid space, one can mimic the natural behaviour to realize computer vision. Despite the fact that there exists several merits with the hexagonal acquisition and display systems, such devices are not readily available which could be due to reasons lie economy, convenience and performance of the rectangular counterpart. Many image processing operations lie seletonizing, thinning, dilation, erosion, opening and closing of the images can be done on a hexagonal lattice. To prove the above statement, we have considered two image processing operations namely edge detection and image seletonization on hexagonal lattice. CLAP algorithm was used to find the edge detection. Iterative thinning method, which is better suited for VLSI implementation had been used for finding the seleton of an image. In the rest of the paper which follows, we have presented an overview of hexagonal sampling and we have elaborated the sub sampling procedure needed to obtain the hexagonally sampled image from the conventional rectangular sampled image. Edge detection done on rectangular and hexagonal sampling grids is presented. Simulation results of the seletonization algorithm done on the rectangular lattice for the purpose of comparison with hexagonal lattice is given. Finally VLSI implementation of cellular processor array for binary image seletonization on a hexagonal lattice is proposed. II. HEXAGONAL SAMPLING Sampling is the process of measuring the value of the image function f (x, y) at discrete intervals in space. Each sample corresponds to a small square area of the image, nown as a pixel. A digital image is a 2-D array of pixels. When sampling an image, we need to consider not only the sampling rate, but also the physical arrangement of samples. A rectangular pattern, in which pixels are aligned horizontally and vertically into rows and columns, is by far the most common one. Unfortunately a rectangular sampling leads to ambiguities in pixel connectivity. It introduce ambiguity in attempts to define neighborhoods, of a given pixel as four-neighbor (above, below, left and right) or as eight-neighbour (which includes the neighbours which only touch at the corners).however in

2 hexagonal sampling, diagonal neighbours are properly connected and the distance traveled in an image does not depends upon a direction. Despite these advantages, a hexagonal pattern is seldom used. It cannot portray accurately the large number of horizontal and vertical features found in many images and in any case, sensors and display hardware do not support hexagonal sampling. From the point of view of the neighbourhood properties of a single pixel, hexagonal grid is more elegant. Each pixel P is surrounded by six neighbours. All the six neighbours belong to the same equivalence class in the sense that they share one edge with its neighbours. Let us consider a typical rectangular pixel grid of resolution 1X2 as shown in Fig.1. Fig. 3. Original image Fig. 4. Rectangularly sampled image Fig. 1. Rectangular Grid Hexagonal grided image can be obtained from the conventional image by alternatively suppressing rows and columns of the existing rectangular grid and sub sampling it. All the other pixels of the rectangular grid which do not have any correspondence with the hexagonal counterparts are suppressed to zero. While processing this sub sampled image the suppressed pixels are not considered in computation. The sub sampled hexagonal grid is shown in Fig. 2. Fig.. Hexagonally sampled image From the above figures, it is clear that the hexagonal grids have pixels which are offset by half pixel width on the alternate rows when compared with the conventional rectangular grids. This arrangement maes the hexagonal grided image more suitable for representing circular images since it gives more pleasing visual appearance. III. EDGE DETECTION Fig. 2. Hexagonal grid The hexagonal grid obtained above by sub sampling the rectangular grided image consists of fewer pixels compared to rectangular sampled image. To compare modeling and processing of images on a hexagonal grid, we sub sample the rectangular image again to get the simulated rectangular grid which has the resolution as that of modeled hexagonal lattice. Original image and it s hexagonally sub sampled image and the rectangularly sub sampled image is given in Fig. 3, 4,. Edges can be defined loosely as locations in an image where there is a sudden variation in the grey level or color of pixels. Edge detection basically deals with finding the boundaries of various regions in the given image. Existing edge detection operators lie sobel, prewitt, canny operators cannot be used for hexagonally sampled image. So in this paper the CLAP algorithm for edge detection is used where various Basis Structures are used to filter the values of interest from the scan window. The Basis structures would be convex polygons that will enclose the pixel in consideration. The 3 X 3 grid itself is one such polygon. Other polygons can be obtained by removing the corner pixels of the 3 X 3 grid in various combinations. The nomenclature of these basis structures is as per [1, 2, 3]. The pixel wise representation of these polygons over the 3 X 3 grid for a rectangularly sampled image can be given as in Fig. 6.

3 A B 1 B 3 B 7 B 9 C 1,3 C 1,7 C 1, C 3,7 C 3,9 C 7,9 D 1,3,7 D 1,3,9 D 1,7,9 D 3,7,9 E 1,3,7,9 Fig. 6. The Basis Structures over the 3x3 Rectangular grid From the Fig. 6, the basis structure for the rectangularly sampled image is E 1,3,7,9. Similarly the Basis structures for a Hexagonal Lattice as the possible convex polygons that enclose the central pixel in the 7-neighbourhood hexagonal lattice as shown in Fig Fig. 8. Neighborhood of the pixel in the Rectangular grid A B1 B2 B3 B4 B B6 C1,3 C1,4 C1, C2,4 C2, C2,6 C3, C3,6 C4,6 D1,3, D2,4,6 Fig. 7. The Basis Structures over the 7-neighbourhood Hexagonal lattice Among the basis structures for the hexagonal sampled image, D 1,3,,, D 2,4,6, C 1,4, C 2,, C 3,6 are the basis structures. Fig. 9. Neighborhood of the pixel in the Hexagonal grid From the implementation of edge detection algorithm described above for both rectangular and hexagonal lattice, it is clear that curves have more visual appeal in the hexagonal representation than in its rectangular counterpart. If we have an overall loo at the pictures we can see that the image over the hexagonal grid has more clarity and visual appeal as the edges are smooth and clear than that over the rectangular grid which may be due to definite neighborhood and symmetry of hexagonal lattice. The original image and its edge detected versions for both the hexagonal and rectangular sampling are given below in Fig.1 and 11. A. General Procedure The given digital image is scanned by the X window. On each move, the X sub image covered by the scan window is checed for the basis structure given in Cellular Logic Array Processing algorithm. The values in this polygon are examined to see whether the gray-distance, say D, that is the difference between the maximum gray value G max and the minimum grayvalue G min, is less than or equal to a threshold value, say T. If D is less than or equal to T, then the central cell is assigned the value ; otherwise the original value contained in the central cell is left as it is. This procedure is continued till the entire image is scanned. The overall effect is that the boundaries of various regions in the given image, that appear to be uniform, are retained and their interior parts are erased thus giving as the edge detected version of the original image. The neighbourhood pixels to be considered for the rectangular and hexagonal sampled images are given in Fig. 8 and 9 respectively. Fig. 1. Original image and its edge detected version in a sub sampled rectangular grid and a sub sampled hexagonal grid

4 processing cell. Altogether the above aspects mae the iterative thinning methods [] better suited for VLSI implementation in terms of logic complexity and area efficiency. Fig. 11. Original image and its edge detected version in a sub sampled rectangular grid and a sub sampled hexagonal grid IV. IMAGE SKELETONIZATION The seleton of a binary image is an important representation for the shape analysis and is useful for many pattern recognition applications. The seleton of an object is a line connecting points midway between the boundaries. A seleton has the same connectedness ("topology") as the original object. A typical seleton is shown in Fig. 13 A. Seletonization on a Rectangular Lattice To compare the seletonization done on a hexagonal lattice, we implemented seletonization algorithm [7] on rectangular lattice. The pseudocode of the algorithm is given below. The algorithm runs in 2 sub-iterations. During each sub-iteration different rules are applied for deciding whether or not a pixel will be deleted. The pseudocode is as follows: I= original image; J=temporary image; K=temporary image J=I; K=I Loop until no pixels are deleted //first sub-iteration For all pixels J(i,j) Delete K(i,j) if all of the following are true: a) 2 <= B(i,j) <= 6 b) A(i,j)=1 c) P2*P4*P6 = d) P4*P6*P8 = end //second sub-iteration For all pixels J(i,j) Delete K(i,j) if all of the following are true: a) 2 <= B(i,j) <= 6 b) A(i,j)=1 c) P2*P4*P8 = d) P2*P6*P8 = end J=K end The outputs of this algorithm on some text images are shown in Fig. 14 and 1. Fig. 13. A typical seleton Extraction of a seleton from a digital image is not generally straightforward. Many algorithms exist to find the seleton of an image. Among them, there are two main approaches for seleton extraction, based either on iterative thinning or distance transform. Although the latter methods are less sensitive to a boundary noise, methods based on iterative thinning have several features which become beneficial when the primary goal is a VLSI implementation. In the majority of distance-transform algorithms the data flow between pixels involves transferring a distance value from PE to PE. In some algorithms it also involves transferring a vector value, pointing at a nearest bacground pixel [4]. This will require at least log 2 N (with the image size N X N) bits for communication between two PE s, whereas in iterative thinning methods this value is invariant to image size. Another disadvantage of distance-based methods is the requirement for bit vector arithmetic operations with log 2 N - bit numbers within each cell (as compared with single-bit operations in iterative algorithms). This leads to increased amount of input/outputs and impractical complexity of the Fig. 14. Image 1 and its Seletonized version on Rectangular Lattice Fig. 1. Image 2 and its seletonized version on rectangular lattice The observation from above process is that, the diagonal lines in the rectangular grid appear as staircases because the rectangular grid each point has only 4 degrees of rotational freedom and thus only two straight lines can be drawn through a given point without any staircase-lie appearance i.e.

5 horizontal and vertical lines. All other lines invariably appear as staircases. (2) (4) when triggered by a removed neighbour. The output of the above algorithm is shown below in Fig. 17 and 18. B. Seletonization on a Hexagonal Lattice The seletonization of the binary image can be found by using the Cellular Processor Array (CPA) [8], which consists of the processing elements, connected in hexagonal grid. Cellular Processor Arrays have attracted significant attention in the last ten years, as they have shown the potential to achieve high performance, small area and low power consumption, as compared to conventional vision systems. Employing processor per pixel approach, CPA s provide a solution for vision systems capable of performing various image processing operations at high speeds. The iterative thinning method presented in this paper overcomes demerit of distance transform method by transferring data only between the nearest neighbours. It is based on hilditch s thinning algorithm [6]. Each processing element shares only two bits of data with its neighbours, which provides sufficient information to achieve seletons with preserved object topology and connectivity. The input binary image consists of bacground pixels (logic 1 ) and object pixels (logic ) on a hexagonal lattice. The neighbourhood for every PE is defined as in Eqn.1: N(P ) = {P } = (1) In other words N(P ) is represented by six pixels nearest to P as shown in Fig. 16. P P 1 P P 2 P 3 Fig. 17. Image 1 and its Seletonized version on Hexagonal Lattice Fig. 18. Image 2 and its Seletonized version on Hexagonal Lattice C. VLSI Implementation One needs to consider the trade-off between speed, area and circuit complexity, while designing a VLSI architecture. The problem with cumbersome interconnections has been eliminated by employing a hexagonal lattice as a processing grid and implementation of an algorithm that requires only local neighbourhood information. The CPA consists of interconnected processing cells arranged in a hexagonal manner. All the PE s in the CPA operate asynchronously, independently from each other. There is only one synchronization signal, used for uploading an image and resetting internal logic for every PE. The Processing Element architecture is given below in Fig. 19. P P 4 Fig. 16. Local hexagonal PE neighbourhood N(P) Input from Neighbour pixels INPUT LATCHES COMBINATIONAL BLOCK OUTPUT LATCHES Output to neighbours pixels Let us define three functions: 1. B = P = 2. A sign( ( P (+ 1)mod 6 (3) = P ) 1) = 3. C ( )mod 6 P P ( 1)mod 6 A = (P + + ) = (4) An object pixel is then considered to be not a seletal point and is removed if all three following conditions are satisfied: 1) 1 < B < 6; (not isolated, internal or endpoint); () 2) A = ; (not a junction); (6) 3) C = 1; (prevention of two-pixel lines vanishing). (7) Each processing element has access to the binary values P and A of all its neighbours and evaluates expressions (2) Start signal CONTROL UNIT Fig. 19. Processing Element The architecture consists of a combinational bloc for calculating the parameters A, B and C given by the equations (2) (4) and to chec whether the pixel belongs to a seletal pixel according to the conditions given by expressions () (7). The processing element gets input from six neighbours (processing element) and process the values and outputs to the next processing element. Each PE shares only two single-bit values with its neighbours: pixel value P and parameter A. The processing element input signals consist of P and A values and activation signals from 6 neighbours as well as a Start signal (global) and pixel input (individual for each PE). The processing element is activated

6 when it receives an activation signal from any of its neighbors. The processing element has been designed using verilog HDL. The synthesis report is as follows. The designed PE occupied 24 IO s, 36 function generators, 18 CLB slices, and 2 D flipflop s or latches as shown in Table 1 below. TABLE I SYNTHESIS REPORT INDICATING DEVICE UTILIZATION Resource Used Available Utilization IOs % Function Generators % CLB Slices % Dffs or Latches % Using the designed processing elements a Cellular Processor Array (CPA) of size X was designed using Verilog HDL. The synthesis report is given in Table 2. TABLE II SYNTHESIS REPORT INDICATING DEVICE UTILIZATION Resource Used Available Utilization IOs % Function Generators % CLB Slices % Dffs or Latches % V. RESULTS AND FUTURE WORK We have implemented the CLAP (Cellular logic Array Processor) algorithm for the edge detection of both rectangularly sampled images and hexagonally sampled images. The results show that hexagonally sampled images have more pleasing visual appearance and this is due to symmetry and definite neighborhood property of the hexagonal grid. The algorithm was tested using gray level images and can be extended to color (RGB) Images. We can also perform other Image Processing operations such as Seletonizing, Thinning, Morphological Dilation, Erosion, Opening and Closing of images over the Hexagonal lattice. With this venture in mind, we have taen the problem of image seletonization on the hexagonal lattice. To compare seletonization done on hexagonal lattice, the same was performed on rectangular lattice and the appropriate results and observations are discussed. The processing element and CPA of size X array for performing seletonization on a hexagonal lattice is implemented using verilog HDL, simulated and synthesized using Modelsim and Leonardo spectrum respectively. An FPGA implementation of the processing element was done to have behavioral proof the concept of the design and to estimate behavior and timing properties. VI. REFERENCES [1] Rajan, E. G., The Notion of Geometric Filters and their use in Computer Vision, IEEE International Conference on Systems, Man and Cybernetic Vancouver, B.C., Canada, pp.42-42, October 22-2, (199). [2] E. G. Rajan, T. Sanjay, K. Pramod Sanar, Hexagonal Pixel Grid Modeling and Processing of Digital Images Using Clap Algorithms, International Conference on Systemics, Cybernetics and Informatics, February 12 1, (24). [3] Lee Middleton and Jayanthi Sivaswamy, Edge detection in a Hexagonal - image processing framewor, Image and vision Computing 19, pp , (21). [4] Sudha, N., Design of a cellular architecture for fast computation of the seleton, Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 3(1) pp , (23). [] Lam, L., et al. C. Y., Thinning methodologies a Comprehensive survey. IEEE Trans. Pattern Analysis and Machine Intelligence, 14 (9): p , (1992). [6] Hilditch, C., J., Linear seletons from square cup-boards Machine Intelligence, :p.43-42, (1969). [7] E. S. Deutsch, University of Maryland, Thinning Algorithms on Rectangular, Hexagonal, and Triangular arrays. [8] Niolaos Bourbais, Nils Steffensen and Biram Saha, Design of an Array Processor for Parallel Seletonization of Images, IEEE Transactions on Circuits & Systems II : Analog and Digital Signal Processing, Vol. 44, No. 4, April [9] Lee Middleton and Jayanthi Sivaswamy, Hexagonal Image Processing A Practical Approach, Springer-Verlag London Limited 2. [1] Richard E. Woods, Rafael C. Gonzalez, Digital Image Processing, 2nd Edition, Addison-Wesley, November 21. VII. BIOGRAPHY Senthilnayai M. was born in Coimbatore city, Tamilnadu, India on October, She obtained her Bachelor of Engineering in Electronics and Communication Engineering from Bharathiar University, Coimbatore during She obtained her Master of Technology in VLSI Design in 26 from Amrita Deemed University, Coimbatore. She is currently woring as a Lecturer in Department of Electronics and Communication in Amrita Deemed University, Coimbatore. Her areas of interests include VLSI Design of image processing algorithms, Digital integrated circuits. S.Veni received her AMIE in 1994 and Master of Technology in She is currently woring as an Assistant Professor in the Department of Electronics and Communication Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, Tamilnadu., India. She is currently pursuing her Ph.D. Her areas of interest include image processing, neural networ, computer vision and VLSI architectures. She has published nearly 8 papers in the national and international conferences in these areas. Dr. K.A. Narayanan Kutty was born on in Bangalore, India. He obtained his bachelor of Engineering from Jabalpur University in 197. He obtained his Master o Technology and PhD from IISC Bangalore in 1974 and 198 respectively. He was a project engineer at Jyothi Ltd Vadodara, Chie engineer at Microwave Products India ltd. He was a consultant for major industries in erala for about 1 years. He is currently woring as a professor in VLSI Design in Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore. His areas of interests include signal processing.