Approach to Enable Real-Time HPC. President, CEO and Cofounder National Instruments

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2 Applying a Graphical System Design Approach to Enable Real-Time HPC Dr. James Truchard President, CEO and Cofounder National Instruments

3 National Instruments Leaders for 30 years in Computer-Based Measurement and Automation Direct Operations in 40+ Countries 5,000+ Employees R&D Investment: 16% of Annual Income Corporate Headquarters in Austin, Texas 600+ Alliance Partners Long History of Financial Success 9 YEARS Direct Sales Offices Distributors

4 The National Instruments Vision To do for test and measurement what the spreadsheet did for financial analysis. Virtual Instrumentation

5 The National Instruments Vision, Evolved Graphical System Design Test and Measurement Automated Test Data Acquisition Reconfigurable Instruments Real-time Measurements Embedded Monitoring Hardware-in-the-loop Industrial and Embedded Industrial Control (PAC) Machine Control Electronic Devices Code Generation To do for test and measurement what the spreadsheet did for financial analysis. To do for embedded what the PC did for the desktop.

6 Graphical System Design LEGO MINDSTORMS NXT the smartest, coolest toy of the year CERN Large Hadron Collider the most powerful instrument on earth

7 HPC Applications File / Database HPC Result

8 Real-Time HPC Applications File / Database Live Signals (Sensors) Real-Time HPC Result (Actuators) System Under Control

9 Graphical System Design enables Real-Time High Performance Computing Max Plank Institute Tokamak ESO Extremely Large Telescope Plasma Diagnostics & Control Primary Mirror and Adaptive Optics Control

10 GF FLOPs Real-Time HPC Trend Tokamak Plasma Control 40 GFLOPs (DBL) 1 ms loop rate 8-core Xeon ESO E-ELT M4 Mirror Control 2 TFLOPs 2 ms loop rate 48 x 8-core Xeon ESO E-ELT ELT M1 Mirror Control 1 TFLOPs 1 ms loop rate >900 crio FPGA Synchrotron Tomography (Proposed) 4 TFLOPs 128 x 8-core machines 3D 8k x8kx8k voxels Financial Application (Proposed) 1.2 TFLOPs European Options Farm of 10 FPGAs Larrabee Farm (Proposed) 10 TFLOPs 1M FFT/s 10 1k samples 16-core Xeon 500k complex FFT/s 1k samples FPGA board Year

11 GF FLOPs Real-Time HPC Trend Tokamak Plasma Control 40 GFLOPs (DBL) 1 ms loop rate 8-core Xeon ESO E-ELT M4 Mirror Control 2 TFLOPs 2 ms loop rate 48 x 8-core Xeon ESO E-ELT ELT M1 Mirror Control 1 TFLOPs 1 ms loop rate >900 crio FPGA Synchrotron Tomography (Proposed) 4 TFLOPs 128 x 8-core machines 3D 8k x8kx8k voxels Financial Application (Proposed) 1.2 TFLOPs European Options Farm of 10 FPGAs Larrabee Farm (Proposed) 10 TFLOPs 1M FFT/s 10 1k samples 16-core Xeon 500k complex FFT/s 1k samples FPGA board Year

12 Tokamak Plasma Diagnostics and Control with Multicore X-Ray Tomography and Plasma Control with Processing under 1 ms 192 Toroidal Stations 512 Channels per Station 10-kHz Sampling Rate per Channel All Channels Synchronized

13 Plasma Diagnostics & Control with NI LabVIEW RT Max Planck Institute (Munich, Germany) Plasma control in nuclear fusion Tokamak with LabVIEW on an eight-core real-time system with LabVIEW, we obtained a 20X processing speed-up on an octal-core co processor machine over oea single-core ge e processor Louis Giannone Lead Project Researcher Max Planck Institute

14 Next Steps: X-Ray Tomography for Plasma Control I( x, y) = B{ F 1 { f F{ p( τ, θ )}}} X-Rays Tomographic Scan Reconstruction Processing Plasma Grad- Contour Shafranov Analysis PDE 512 Channels Magnetic Actuators R R 1 R 2 ψ ψ + R 2 Z = μ orj ϑ All Operations: 1 ms Loop Time 100 GFLOPs

15 ESO E ELT Mirror Control M4 2 TFLOPs M1 200 GFLOPs (Global Control) 1 TFLOP (Local Control crio)

16 ESO E E ELT Primary Mirror (M1) Control M1 42m DIAMETER 10nm CORRECTION 984 MIRRORS 2952 ACTUATORS 5904 SENSORS 3k x 6k MATRIX 1 MILLISECOND

17 M1 Control Proposed System Setup NI crio Node for Local Sensor / Actuator I/O 1 crio Node per Mirror Supervisor Deterministic EtherCAT Network Ring crio Nodes per ecat Network Ring Supervisory Network 6 Distributed Mirror Controllers per Supervisor NI PXI Distributed Mirror Controller 6 ecat Network Rings per Distributed Mirror Controller

18 ESO E E ELT Deformable Mirror (M4) Senses Wavefront Aberrations using Guide Stars (Natural or Sodium Lasers) as References Applies Correction by Deforming M4 Mirror Requires Demanding Real-Time Computations

19 ESO E ELT M4 Wavefront Real-Time Computing Design, Operation, and Infrastructure [5k x 56k] x 56k every 300μs 1.87 TFLOPs 64 Compute Nodes (512 Cores), 16 Compute Nodes per Star, 4 Stars in System 3 Additional Stars 14k samples every 2 ms 5k samples every 2 ms Group of 4 Compute Nodes

20 ESO E E ELT M4 Hardware In-the-Loop (HIL)

21 ESO E E ELT M4 Hardware In-the-Loop (HIL) HOST WFS Loop Time Wind Speed WFRTC Loop Time CM Actuator Loop time PID and Saturation Wavefront Sensor Sensor Wavefront Real-Time Controller Setpoint Actuator Actuator

22 ESO E E ELT M4 Atmospheric Disturbance Model Wind Speed Calculates Sensors Displays Sensor Data Adds Uniformly Distributed Noise

23 GF FLOPs Real-Time HPC Trend Tokamak Plasma Control 40 GFLOPs (DBL) 1 ms loop rate 8-core Xeon ESO E-ELT M4 Mirror Control 2 TFLOPs 2 ms loop rate 48 x 8-core Xeon ESO E-ELT ELT M1 Mirror Control 1 TFLOPs 1 ms loop rate >900 crio FPGA Synchrotron Tomography (Proposed) 4 TFLOPs 128 x 8-core machines 3D 8k x8kx8k voxels Financial Application (Proposed) 1.2 TFLOPs European Options Farm of 10 FPGAs Larrabee Farm (Proposed) 10 TFLOPs 1M FFT/s 10 1k samples 16-core Xeon 500k complex FFT/s 1k samples FPGA board Year

24 Increasing Levels of Software Abstraction C# System Design Platform bstrac ction A C Assembly Language C++ Machine Code System Complexity

25 The Y-Chart System Design Methodology Application Logic Platform Architecture Analysis & Mapping 1. Kienhuis, Deprettere, van der Wolf, and Vissers., A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, p.18-37, Jan Keutzer, Newton, Rabaey, Sangiovanni-Vincentelli, System-level l Design: Oth Orthogonalization ti of Concerns and Platform-based Design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(12): p , Dec Performance Evaluation ation

26 Models of Computation Idea Model of Computation Implementation Multiply / py Accumulate

27 Models of Computation Data Flow C Code Textual Math Simulation Statechart PC/Mac/Linux PXI CompactRIO FlexRIO Custom

28 The Hybrid Approach Combined Graphical / Textual Programming

29 Parallel Programming with LabVIEW Task Parallelism Data Parallelism Pipelining Multicore Processors FPGAs

30 How We Map Problems. Model of Computation to Idea / Platform Pipelined Execution (Signal Analysis) Distributed Calculation (Finite Difference Method) Parallel Calculation (Dense Linear Algebra)

31 LabVIEW Execution Fundamentals Matrix Vector Multiply Run Queue Run Time Execution Threads Compilation Multiple Cores

32 Eliminating Artificial Complexity Text-based Compiler LabVIEW Compiler String of Characters Lexical Analyzer Tokens Parser Abstract Syntax Tree Intermediate Code & Data Dependency Graph Intermediate Code Generator & Semantic Analyzer Optimizer & Code Generator Intermediate Code Generator & Semantic Analyzer Optimizer & Code Generator Source Dataflow Graph Intermediate Code & Data Dependency Graph Executable Code Executable Code

33 FPGA Programming: g Multicore, Multiprocessor Development

34 Graphical System Design enables Real-Time High Performance Computing Max Plank Institute Tokamak ESO Extremely Large Telescope Plasma Diagnostics & Control Primary Mirror Control

35 GF FLOPs Real-Time HPC is an Opportunity Tokamak Plasma Control 40 GFLOPs (DBL) 1 ms loop rate 8-core Xeon ESO E-ELT M4 Mirror Control 2 TFLOPs 2 ms loop rate 48 x 8-core Xeon ESO E-ELT ELT M1 Mirror Control 1 TFLOPs 1 ms loop rate >900 crio FPGA Synchrotron Tomography (Proposed) 4 TFLOPs 128 x 8-core machines 3D 8k x8kx8k voxels Financial Application (Proposed) 1.2 TFLOPs European Options Farm of 10 FPGAs Larrabee Farm (Proposed) 10 TFLOPs 1M FFT/s 10 1k samples 16-core Xeon 500k complex FFT/s 1k samples FPGA board Year

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