COARSE ANGLE ROTATION MODE CORDIC BASED SINGLE PROCESSING ELEMENT QR-RLS PROCESSOR

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1 7th Europea Sigal Processig Coferece (EUSIPCO 9 Glasgow, Scotlad, August 4-8, 9 COARSE ANGLE ROTATION MODE CORDIC BASED SINGLE PROCESSING ELEMENT QR-RLS PROCESSOR Qiag Gao, Louise Crockett ad Robert Stewart EEE Departmet, Uiversity of Strathclyde, 4 George Street, Glasgow, G XW, Scotlad, UK phoe: + ( , fax: + ( , qiag.gao@eee.strath.ac.uk ABSTRACT Over the last years Digital Sigal Processig algorithm implemetatio has bee drive by the cotiued progress ad availability of high speed ASIC circuit techology. The classic method of CORDIC (Coordiate Rotatio by Digital Computer arithmetic has bee widely implemeted as part of the computatioal requiremets of the well kow QR- RLS (recursive least squares algorithm. I this paper we propose a ew modified versio of the CORDIC that features a sigle processor elemet that is easily pipeliable ad ca be used to implemet both the Gives geeratios ad Gives rotatios associated with the QR update. Usig a Xilix FPGA for implemetato results show that this proposed structure requires less resources ad produces a more regular ad therefore lower cost structure tha other equivalet methods recetly preseted.. INTRODUCTION Withi the area of wireless commuicatios, the icreasig commuicatios speeds required meas that there is sustaied demad for high speed implemetatios of data equalisers, adaptive beamformers, beamsteerers ad MIMO (multiple iput multiple output atea systems. The key algorithm to implemet these applicatios of course the least squares adaptive sigal processig techique []. Over recet years, the favoured method of high speed (parallel implemetatio has bee the QR Decompositio (QRD- RLS algorithm [] give its fast covergece, ad compared to other methods of solvig the least squares equatios, its excellet umerical coditioig []. Furthermore from a implemetatio poit of view, the QR is very well kow for its triagular systolic type array implemetatio [] [4]. The structure of this paper is orgaised as follows. I Sectio we review the stadard QR triagular array. I Sectio, the systolic array implemetatio of QR-RLS with dowdatig is briefly reviewed. I Sectio 4, the covetioal CORDIC algorithm based QR-RLS processig elemet is preseted. A ew Coarse Agle Rotatio Mode CORDIC architecture is elaborated i Sectio 5 to replace the oe covetioally used i all the Processig Elemets (PEs of the QR-RLS array. The desig of a efficiet chael iterleavig CORDIC is preseted i Sectio 6. Fially Sectio 7 proposes oe ew sigle PE QR-RLS architecture to replace the existig liear array [5][6]. EURASIP, THE CLASSIC QR TRIANGULAR ARRAY Based o [] ad [], the stadard QR-RLS recursive algorithm is summarized as: Q R( k λ u( k R u x T ( k dk ( ak ( ( Where Q is the orthogoal rotatio matrix, which triagularises the left had side matrix of Eq. (, λ is the forgettig factor (set to a value less tha, ad ak ( is the posteriori Least-Square residual. The N N matrix R is the well kow correlatio matrix, ad the N elemet vector x is the iput data vector. N is the umber of weight the adaptive filter []. Figure shows a simple sigal flow graph (SFG represetatio of the well kow stadard QR-RLS systolic array [7] aimig to fid the weights of a N weight FIR filter (this small dimesio is used to keep the SFG diagrams simple, comparig the iput sigal xk ( with the desired sigal dk ( with the aim of miimisig the power of the error sigal ek ( dk ( xk ( []. This array uses the Gives rotatio to covert the iput data ito a upper triagular matrix R []. Each stored ad updated iside of the array is oe elemet of this upper triagular matrix, where the subscript (i,j represets the locatio of the elemet i R matrix ad u vector [4]. x represets the iput sigal. The defiitios of the Boudary Cell (BC ad Iteral Cell (IC of QR-RLS array are also described i Figure. s ad c are used to express the Gives rotatio values (ofte deoted Sie & Cosie calculated with i a boudary cell. The right most colum geerates the product of the cosies γ. Note that this operatio is ormally udertake i the BCs ([] [] [4] [5] [6]. However by attachig the right most colum of ICs [8], it becomes possible to costruct the BC ad IC with very similar architectures, which ca be exploited with the efficiet foldig of both types of cell oto a sigle PE (to be discussed i Sectio 7. The posteriori error ek ( ca be foud from the multiplier []. I may implemetatios ([5], [9] the fial coefficiet weight vector is derived from the outputs of the QR decompositio algorithm usig backsubstitutio. To implemet a systolic structure for backsubstitutio, oe approach is to apped a liear array to the upper triagular

2 x(k d(k x(k d(k A r r r u 4 γ 5 r - 6 r r (a Boudary Cell (Gives Geeratio x bc if x bc, the r c i c i ; else c i r ( ij + x bc x bc r ( ij + x bc ( k + λ (b Iteral Cell (Gives Rotatio c i x ic c i ( ( + x bc r ij k x ic + λ c i R ij c i x ic λ u 4 u 4 e(k Figure - Stadard systolic array of QR-RLS γ 5 γ 5 : Delay : Multiplier r - 6 r - 7 W 46 W 47 W 48 B e(k W W W (d Dowdatig Cell (e Weight Extractio Cell x dc b i c i c i a i a w i r - ij ij W ij c i x ic λ x ic λ + c i W ij W ij ( k a i b i Figure - Systolic array of QR-RLS with dowdatig r - 6 r - 7 r - 8 QR-RLS array [5] [9]. However it is worth otig that whereas the QR triagularisatio method has excellet umerical properties ad is hece the favoured method for fixed poit implemetatio, the procedure of backsubstitutio is kow to be a process that is ot umerically well coditioed []. Aother issue with the regular implemetatio of the QR array is that it is ot easily iterfaced to the backsubstitutio array, which is a liear array that requires the R values to be first shifted out from the QR array [5]. Also, the data throughput of the liear array is lower tha that of the triagular array. Therefore i geeral the backsubstitutio operatio is ot well suited for a FPGA dataflow array (ad is usually performed o a embedded processor [5] [9]. The exteded QR-RLS (QR-RLS with dowdatig algorithm derived for weight extractio could mitigate the eed for the backsubstitutio by addig a secod lower triagular dowdatig array such that the fial adaptive filter weights ca the be extracted by a sigle multiplicatio ad subtractio operatio [] [].. QR-RLS ARRAY WITH DOWNDATING The QR-RLS with dowdatig derived for weight extractio ca be implemeted with a CORDIC-based double triagular systolic array [] []. The additioal dowdatig part must satisfy the followig equatio []: Q λ R( k λ u( k λ R ( k x T ( k dk ( R u R ak ( bk ( ( A example of this QR-RLS array with dowdatig is show i Figure. The triagular sectio o the left of dashed lie A-B, cosists of the same BCs ad ICs as Figure. The lower triagular (dowdatig sectio (o the right had side of lie A-B rotates the R matrix stored i the cells ad a exterally applied vector of zeros. Obviously, both the IC Figure ad the Dowdatig Cell (DC i Figure execute 8 early the same operatio. The oly differece is that the forgettig factor i each DC is equal to /λ. Hece the DC could also be mapped together with the IC ad BC, ad this foldig strategy will be described i Sectio 7. At this poit we should poit out that the use of a QR rhomboid array is well kow to icrease the arithmetic wordlegth compared to the stadard QR triagular array. This ca be simply observed for example by otig that for iitialisatio, the iitial values of the stadard QR upper triagular array are set to very small values, say σ, ad therefore equivaletly the iitial value the lower triagular dowdatig array, must be set to σ. However the objective of this paper is ot to review the umerical properties, but to derive a uiquely regular high speed QR array. 4. CORDIC QR BOUNDARY & INTERNAL CELLS Last sectio metioed that both the boudary ad iteral cellside the systolic QR-RLS array are based o the Gives rotatio. Oe low complexity techique that performs the Gives rotatio is the CORDIC algorithm. It is a iterative method which is used to calculate may trigoometric ad algebraic fuctios [] []. CORDIC ca be implemeted usig oly shift ad add operatios, ad hece result a efficiet hardware desig. For oe CORDIC iterative idex, i, the rotatio equatios are show i Figure (a: x i + x i d i ( i y i y i z i + y i + d i ( i x i + z i d i ( ata i (a ( x i y i d z i i >>i >>i cost x i + y i + (b z i + Figure - (a Classic CORDIC iterative algorithm (b The hardware implemetatio for sigle iteratio elemet

3 Vectorig Mode CORDIC Iteratio Cells (Boudary Cell w Agle Decisio Factor d -, -, o -6.6 o +4 o -45 o -6.6 o +4o Rotatio Mode CORDIC Iteratio Cells (Iteral or Dowdatig Celll / / Figure 4 - Itercoectio betwee the BC ad IC/DC i [] Note that the umber of iteratios of i is a fuctio of the desired umerical accuracy [4]. If the vector is rotated clockwise, the decisio factor d should equal to -, otherwise, d. The hardware architecture of the classical sigle iteratio elemet is show i Figure (b. Each boudary cell of the QR array requires the vectorig mode CORDIC where Eq. ( implemeted with the ext agle iteratio chose i order to drive y towards zero. The iteral cell uses the rotatio mode CORDIC where the d (rotatio directio is chose as a fuctio of whether agle z is egative or positive as a result of the last iteratio. As show i Figure 4, we assume both the boudary ad iteral cells have 8 iteratio cells, ad each cell has the architecture i Figure (b. The umber of iteratio cells depeds o the desired umerical accuracy [4]. The classic vectorig mode CORDIC geerates the agle z, ad the rotatio mode performs the Gives rotatio for the same agle (Figure 5. y -z x Boudary Cell (Vector Mode z Iteral Cell (Rotatio Mode Figure 5 - Lik betwee the classic QR-RLS BC ad IC/DC 5. COARSE ANGLE ROTATION MODE CORDIC Accordig to the circuit implemetatio, based o Eq. (, we eed to build three subcircuits for x, y ad z computatios. Oe of the core outputs of this paper is to fid a commo structure to allow the same array to be easily shared for the various boudary ad iteral cells. The x ad y parts are always ecessary for the Gives rotatio operatio. I the followig part of this paper, a advaced CORDIC/QR architecture is proposed i which the z compoet of Eq. ( ca i fact be discarded. As a alterative to calculatig the agle z for the Gives rotatio, we could i fact just pass the coarse agle rotatio iformatio d, i.e a or a -; give the agle used i the boudary is that same as the agle used i the iteral cells the sequece of the d directios absolutely the same. I the ext sectio we will demostrate the structure of a ew CORDIC based QR boudary ad iteral cells which are -z Boudary Cell (Vector Mode Iteral Cell (Rotatio Mode Figure 6 - Sigal trasfer betwee QR boudary ad iteral cells Vectorig Mode CORDIC Iteratio Cells d d d d d 4 d 5 d 6 Rotatio Mode CORDIC Iteratio Cells Figure 7 - Itercoectio betwee the ew BC ad IC/DC simplified based o this observatio. I Figure 6, durig the first rotatio iteratio, the vector iput to the boudary cell will be rotated by 45 O clockwise, ad the geerated d is -. Whe trasferred to the iteral cell, d is simply used to geerate the required 45 O rotatio. After three CORDIC iteratios (ad therefore three d values passed from boudary to iteral move to before the bracketed bit, we fid that the iitial vectors have bee rotated by the required agle. For a boudary cell, the total rotated agle is O, ad for iteral cell, it remais the same. Clearly as with the classic CORDIC the more iteratios udertake, the more accurate the agle of rotatio. Therefore it is possible to perform Gives rotatios of the same agle i differet cell a QR array without explicitly computig the agle, but rather commuicatig the directio d of the various CORDIC coarse agle values. As will be justified ad show ext this leads to hardware resource reductio ad produces a more regular array. The itercoectio of ew vectorig ad rotatio CORDICs is show i Figure 7. The top row of the CORDIC iteratio cells still represets the BC of the covetioal QR-RLS array, ad the bottom row of iteratio cells could be cosidered as either oe IC or DC. The lik betwee both modes CORDIC is the decisio factor d of each iteratio. Now the iteratio cell either boudary (BC or iteral (IC/dowdatig (DC PEs pricipally requires two bitshifters ad two adder/subtractors to calculate the x ad y i Eq. (, hece the BC ad IC/DC proposed above ca be easily mapped oto a sigle PE architecture by applyig this foldig techique. 5. COMPARISION WITH THE CLASSIC CORDICS We ca ow compare the sythesis results from the ew CORDIC (Coarse Cordic Gives based 6-iteratio ad 8- bit wordlegth BC ad IC with the correspodig PEs usig d 7 8

4 Type PE Slices FFs LUTs DSP48 BRAM Stadard Cordic Gives Coarse Agle Cordic Gives Stadard Cordic Lookup Boudary Iteral Boudary Iteral Boudary Figure 8 - Sythesis results for types of CORDIC based BC/ICs (6-iteratio & 8-bit wordlegth the covetioal architecture (Stadard Cordic Gives demostrated i Figure 4. For this compariso, real arithmetic arrays were compared. The FPGA resource utilizatios are listed i Figure 8. Xilix ISE. is used to target a Virtex-4 xc4vsx5-ff668 device. The ew proposed Coarse Agle Rotatio Mode CORDIC saves.5% hardware resources compared to the classic oe i [], for both the BC ad ICs. Result Figure 8 also show that the ew Coarse Agle Rotatio Mode CORDIC based BC uses early the same amout of resources as the IC, due to their similarity. Vectorig Mode CORDIC Iteratio Cells Sie Cosie LUT Agle Gives Rotatio Cell Figure 9 - Itercoectio betwee the [5] based real BC ad IC A alterative architecture (Stadard Cordic Lookup adopted i [5] is show i Figure 9. The boudary cells of the QR-RLS array i [5] use the stadard CORDIC architecture which ivolves the agle z calculatio compoet. Oe additioal LookUp Table (LUT is applied to covert each geerated z to its correspodig Sie ad Cosie values. With these trigoometric fuctios as the iputs, the IC/DC ca perform a Gives rotatio usig oly multiply ad add operatios. Here the wordlegth ad umber of CORDIC iteratios are still 8 bits ad 6 respectively. A architecture for real Give's rotatios (based o that preseted i [5] for complex umbers was costructed ad compared with the architecture preseted i this paper. Its sythesised resource utilizatio is also show i Figure 8. The hardware cost of the boudary cell based of this structure is larger (56% tha that of our proposed boudary cell. This desig also uses the Virtex-4's arithmetic elemets (DSP48 slices. The critical advatage of the coarse agle rotatio mode CORDIC based BC ad IC/DC is that they could be mapped oto a sigle processig elemet, which may result i the implemetatio of a efficiet, pipelied QR-RLS couter Pipelied CORDIC *f s couter Figure - Chael Iterleavig processor. I the ext Sectio, the cocept of sigle PE QR- RLS processor will start to be itroduced. 6. EFFICIENT CHANNEL INTERLEAVING CORDIC For maximum efficiecy a pipelied ad parallel CORDIC architecture should be implemeted. If we just assume that there are oly 4 CORDIC iteratio cells used i all three types of PE our QR-RLS array, based o the sythesis result uder the same devices ad wordlegth i Sectio 5., the clock rate of the pipelied Coarse Agle Rotatio Mode CORDIC ca reach up to MHz, ad hece with the Chael Iterleavig architecture i Figure, the data rate of up to Msamples/sec ca be supported. The Chael Iterleavig based pipelied CORDIC i Figure offers a low cost hardware solutio, which allows the work of several CORDICs to be doe by a sigle cell. However, uless iput chaels exist to fill pipelie stages the there will still be some redudacy [5]. Hece the efficiecy show here is of course a special case of multichaels beig available. Recall that the critical advatage of the ew BC ad IC is that they could be mapped oto a sigle PE without a large icremet of resourse ultilizatio. The sythesis results for this sigle PE architecture (which adopts the same wordlegth ad iteratio umber with that i Figure 8 is listed i Figure. PE Slices FFs LUTs DSP48 BRAM Sigle PE Figure - Sythesis result for the sigle PE based BC ad IC sharig Comparig above sythesis results with that i Figure 8, the cost of sigle PE which maps the BC ad IC together is % less tha the utilizatio of oe BC based o [5]. Furthermore the BC ad IC i [5] have totally differet architectures. Hece by adoptig the Coarse Agle Rotatio Mode CORDIC, the Chael Iterleavig based sigle PE architecture has the advatage of reduced cost compared to other existig techiques. 7. CHANNEL INTERLEAVING CORDIC QR-RLS To traslate the previous QR desig to a sigle Processig Elemet (PE architecture, firstly, the exteded QR-RLS structure show i Figure must be trasferred to the sigle row rolled architecture, i.e fold all the row the dashed rigs to oe liear array [5] [6]. At this poit, the data rate reduces to CLK/, where represets the umber of rows. 8

5 x(k d(k A Figure - Liear QR-RLS array trasformatio couter Pipelied CORDIC *f s Figure - Chael iterleavig for multi PEs per row The the ext step i the trasformatio is combiig all the PE the liear array by the space-time sharig. I Figure, the data streams processed by the colums of cells could be cosidered as separate chaels, ad therefore the chael iterleavig scheme we discussed above could be adopted here. This would allow the row of cells to be mapped oto a sigle, chael iterleaved CORDIC cell, as show i Figure. While the work i [5] cosiders the efficiet realisatio of boudary ad iteral cells as discrete processig blocks, this paper focuses o geeralisig the architecture of the boudary ad iteral cells, such that they ca be folded oto a sigle processig elemet. The foldig operatio o the iteral cells without applyig the chael iterleavig will result i further decrease of desig s data rate. Oe poit that eeds to be metioed is: the size of QR-RLS array depeds o the iteratio umber of CORDIC iside each PE. Whe CORDIC has 6 iteratios, the size of QR- RLS could ot exceed CONCLUSIONS I this paper we have proposed ad aalysed the Coarse Agle Rotatio Mode CORDIC. By comparig with two types of covetioal CORDIC based boudary ad iteral cells, it is obvious that the ew CORDIC has low cost. By usig the Chael Iterleavig CORDIC to multiplex more tha oe data chaels together, the pipelied architecture ca be filled up efficietly. The maximum clock speed ca B couter remai the same idepedet of the umber of multiplexed chaels. This paper has proposed a method to map the stadard QR-RLS array with dowdatig oto a sigle processig elemet architecture. The Chael Iterleavig CORDIC based sigle PE QR-RLS processor combies low hardware cosumptio with the beefit of scalability, especially whe implemetig very large matrix sizes. The achieved data rate is reduced to / of the maximum clock rate, where represets the umber of row the origial QR-RLS array with dowdatig. 9. ACKNOWLEDGEMENT The authors would like to thak the EPSRC Specket project & Xilix XUP for support i this research work.. REFERENCES [] S Hayki. Adaptive Filter Theory. Pretice Hall, editio,996. ISBN [] G H Golub, C F. Va Loa, Matrix Computatios, Editio:, Johs Hopkis Uiversity Press, 996, ISBN [] J G McWhirter, Systolic array for recursive least-squares miimisatio, Electroics Letters, Volume: 9, Issue: 8, pp: 79-7, Sept. 98 [4] R Woods, J McAllister, Y Yi, G Lightbody, FPGA-based Implemetatio of Sigal Processig Systems, Wiley, 999 [5] C Dick, F Harris, M Pajic ad D Vuletic, Real-Time QRD- Based Beamformig o a FPGA Platform Fortieth Asilomar Coferece o Sigals, Systems ad Computers, pp. - 4, Oct Nov. 6 [6] QietiQ Quixilica Floatig-Poit QR Processor Core Data Sheet, qx_qr.pdf [7] W M Getlema ad H T Kug, Matrix Triagularizatio by Systolic Arrays, Real-Time Sigal Processig IV, Proc. SPIE, Volume 98, 9-6. [8] J Ma, K K. Parhi ad Ed F. Deprettere, Aihilatio-Reorderig Look-Ahead Pipelied CORDIC-Based RLS Adaptive Filters ad Their Applicatio to Adaptive Beamformig, IEEE Trasactios o Sigal Processig, Vol. 48, NO. 8, Aug [9] Altera White Paper, Implemetatio of CORDIC-Based QRD-RLS Algorithm o Altera Stratix FPGA with Embedded Nios Soft Processor Techology, [] Bi Yag, Joha F. Bohme, "Rotatio-based RLS algorithm uified derivatio, umerical properties, ad parallel implemetatio," IEEE Tras. o Sigal Processig, vol. 4, o.5, pp. 5-67, May 99. [] M Harteeck, R W Stewart, J G McWhirter, I K Proudler, Algorithmic Egieerig Applied to the QR-RLS Adaptive Algorithm, Proceedigs of 4 th Iteratioal Coferece o Mathematic Sigal Processig, 996 [] J. E. Volder, The cordic trigoometric computig techique, IRE Tras. Electroic Computers, vol., pp. 4, Sept [] R Adraka, A survey of CORDIC algorithms for FPGA based computers, Proceedigs of the 998 ACM/SIGDA sixth iteratioal symposium o Field Programmable Gate Arrays, pp. 9-, Feb. -4, 998 [4] Y. H. Hu, The Quatizatio Effects of the CORDIC Algorithm, IEEE Tras. O Sigal Processig, Vol 4, No 4, pp , 99 [5] K. K Parhi, VLSI Digital Sigal Processig Systems: Desig ad Implemetatio, Wiley-Itersciece, 999 d 8