An Efficient Implementation of the Gradient-based Hough Transform using DSP slices and block RAMs on the FPGA

Transcription

1 A Efficiet Implemetatio of the Gradiet-based Hough Trasform usig DSP slices ad block RAMs o the FPGA Xi Zhou, Yasuaki Ito, ad Koji Nakao Departmet of Iformatio Egieerig Hiroshima Uiversity Kagamiyama 1-4-1, Higashi Hiroshima, Japa Abstract The gradiet-based Hough trasform is a improvemet of the origial Hough trasform. It is utilized to reduce substatially the computatio quatity ad make the detectio more accurate usig gradiet iformatio. The mai cotributio of this paper is to preset a efficiet implemetatio of the gradiet-based Hough trasform for straight lies detectio usig a Xilix Virtex-7 FPGA with embedded DSP slices ad block RAMs. We implemeted the circuit usig 13 DSP48E1 slices, 18 block RAMs with 36Kbits ad 8 block RAMs with 18Kbits. The experimetal results show that the architecture rus i 6.61MHz ad for a grayscale image, our circuit ca perform i + ( + ) + 3 clock cycles icludig the computatio of gradiet iformatio. Keywords-Image processig, Lie detectio, Hough trasform, FPGA, Embedded DSP slices, Embedded block RAMs I. INTRODUCTION Recet FPGAs (Field Programmable Gate Arrays) have embedded DSP slices that make a higher performace ad a broader applicatio. The Xilix Virtex-7 series FPGAs have DSP48E1 blocks that are equipped with a multiplier, adders, logic operators, etc [1]. More specifically, the DSP48E1 block has a two-iput multiplier followed by multiplexers ad a three iput adder/subtractor/accumulator. The DSP48E1 multiplier ca perform multiplicatio of a 18-bit ad a 5-bit two s complemet umbers ad produces oe 48-bit two s complemet productio. Programmable pipeliig of iput operads, itermediate products, ad accumulator outputs ehaces throughput ad improves frequecy. The DSP48E1 also has pipelie registers betwee operators to reduce the delay. The block RAM i the Virtex-7 FPGA is a embedded memory supportig sychroized read ad write operatios. I the Virtex-7 FPGA, it ca be cofigured as a 36Kbit dual port block RAMs, FIFOs, or two 18Kbit dual port RAMs. Sice FPGA chips maitai relatively low price ad its programmable features, it is widely used i those fields which eed to update architecture or fuctios frequetly such as commuicatio ad educatio areas. They are widely used i cosumer ad idustrial products for acceleratig processor itesive algorithms [], [3], [4], [5], [6], [7], [8], [9], [1]. The Hough trasform is a techique to fid shapes i images [11]. I particular, it has bee utilized to extract lies, circles, ellipses ad arbitrary shapes. The Hough trasform defies a mappig from a image ito a parameter space represeted by a accumulate array. The parameter space is defied by parameterizig detected shapes. Based o each edge poit of the image, the mappig adds a vote to correspodig elemets i the accumulate array. The elemets that are icreased represet associated parameters based o detected shapes. Therefore, the elemets that are voted itesively correspod to the parameters of shapes i the image space. The Hough trasform ca be used to extract straight lies i a biary image [1]. The idea of this method is to exploit the duality betwee poits of a lie ad parameters of that lie. A poit i the image is represeted by a curve i the parameter space ad lies of colliear poits itersect i the parameter space at oe poit. These itersectios are couted i a array of accumulators that quatizes the parameter space appropriately. I the followigs, we call this coutig to the accumulators votig. More specifically, for each edge poit (x, y) i a -dimesioal image, the votig is performed alog a curve ρ = xcosθ+y si θ ( θ < 18). Possible lies ca be detected by searchig poits that are voted itesively. Figure 1 shows a example of straight lie detectio usig the Hough trasform. For a iput image (Figure 1(a)), the biary edge image (Figure 1(b)) is obtaied by the edge detector such as Sobel filter. We ca see that the ormal Hough trasform performs well basig o the pure edge image. The result of votig to the parameter space is show i Figure (a). I this figure, darker poits show poits that are voted itesively, that is, represet probable lies. Accordig to the result of votig, the pricipal lies are detected (Figure 1(c)). There are may improvemets to the Hough trasform for lie detectio [13]. Oe of the efficiet improvemets is usig gradiet iformatio [14]. The idea of the method is to utilize gradiet directio ad magitude. It is based o the fact that if a give poit happes to ideed be o a lie, The local directio of the gradiet gives approximately the same directio of the actual lie. The gradiet magitude at the pixel is higher tha that

2 (a) Iput image (b) Biary edge image by Sobel filter (c) Lie detectio usig the Hough trasform Figure 1. Example of straight lies detectio usig Hough trasform (a) Covetioal (b) Gradiet-based Figure. Hough parameter spaces of the covetioal Hough trasform ad gradiet-based Hough trasform of other poits ot lyig o lies. Usig these ideas, we reduce the umber of useless votes by limitig the rage of votes with the local gradiet directio, ad weight voted values proportioal to the local gradiet magitude to ehace the votes of pixels o lies. I the followig, the origial Hough trasform is called covetioal Hough trasform, ad the Hough trasform usig gradiet iformatio is called gradiet-based Hough trasform to distiguish them easily. I our implemetatio, we use the Sobel filter, which is used i edge detectio algorithms [15] to obtai the gradiet iformatio. Figure (b) shows the resultig Hough space based o the above ideas. Compared with that of the covetioal Hough trasform, we ca see that votes are limited to the several parts that are darker poits i the figure. Actually, these correspod to real lies i the image ad it is easy to fid that useless votes are reduced. I this paper, we propose a FPGA implemetatio of the gradiet-based Hough trasform. Our ew idea icludes: Votig Space Partitioig: Polar coordiate votig space (θ, ρ) is partitioed ad arraged ito block RAMs. This eables us to perform votig operatios i parallel. Also, the fuctio of dual-port of block RAMs are fully used to accumulate the votig value istatly. Efficiet Usage of DSP slices ad block RAMs: DSP slices are used to compute xcosθ ad y si θ i parallel. Also, we avoid the computatio of the values of cosθ ad si θ usig block RAMs as look-up-tables. Accordig to the above, we reduce the size of the circuit ad icrease its operatig frequecy. Usig these ideas, our ew architecture for the Hough trasform uses 13 DSP48E1 slices, 18 block RAMs with 36Kbits ad 8 block RAMs with 18Kbits for the Hough trasform. Oe of the most importat key techiques for acceleratig computatio usig FPGAs is a efficiet usage of DSP slices ad block RAMs. We have implemeted our ew architectures o a Virtex-7 XC7VX485T-. Our proposed circuit rus i 6.61MHz, ad the votig operatios are performed for a gray-scale image i ++44 clock cycles. Also, for the voted results, our circuit outputs the idetified straight lies i +188 clock cycles. Therefore, our circuit ca perform i +( +)+3 clock cycles, i.e., +( +) µs. For example, for a gray-scale image of size 1 1, our circuit ca perform straight lies detectio i 3.859ms. This paper is orgaized as follows. I Sectio II, related works for FPGA implemetatio of the Hough trasform for straight lies detectio are show. Sectio III reviews the covetioal ad gradiet-based Hough trasform algorithms for lies. We describe the FPGA architecture for the Hough trasform i Sectio IV. Sectio V shows the performace evaluatio ad experimetal results. Fially, Sectio VI cocludes the paper.

3 II. RELATED WORKS May hardware algorithm for FPGA implemetatios of the Hough trasform for lies have bee proposed i past. I the existig researches, they itroduced icremetal Hough trasform [16], [17], [18], CORDIC [19], [], ad hybridlog arithmetic [1] to the computatio i Hough trasform. Sice most of recet FPGAs produced by pricipal vedors equip embedded DSP slices [], [3], [4], [5], [6], oe of the most importat key techiques for acceleratig computatio usig FPGAs is a efficiet usage of DSP slices ad block RAMs. I our previous works [7], [8], we proposed two FPGA implemetatios of the covetioal Hough trasform with DSP slices ad block RAMs. The DSP slices ad block RAMs work i the fully pipelied architecture. Both two implemetatios are based o the covetioal Hough trasform. Karaberou et al. proposed a FPGA implemetatio of the gradiet-based Hough trasform [19]. However, they used CORDIC to compute the complicated calculatios such as square roots ad trigoometrical fuctios without DSP slices ad block RAMs. As far as we kow, our proposed implemetatio is the first FPGA implemetatio of the gradiet-based Hough trasform usig DSP slices ad block RAMs. Also, compared with our previous works, i this work, the umber of utilized DSP slices is reduced cosiderably. III. HOUGH TRANSFORM The mai purpose of this sectio is to review two Hough trasform algorithms, the covetioal Hough trasform ad the gradiet-based Hough trasform. A. Covetioal Hough trasform Suppose that we have a image of size. We assume that pixels are arraged i two dimesioal xy-space such that the origi is i the ceter of the image as illustrated i Figure 3. Hece, both coordiates x ad y take itegers i Figure y ρ θ +1 ( x, y) x ρ ( θ, ρ) 18 θ Two dimesioal Spaces xy ad θρ used i the Hough trasform the rage [ + 1, ]. A pixel (x, y) ( + 1 x, y ) i the xy-space is coverted to a curve i the θρ-space by the followig formula: ρ = xcos θ + y si θ ( θ < 18) (1) Clearly, the double iequality < ρ is satisfied. The values of θ ad ρ ca also be obtaied geometrically. Suppose that we draw a lie goig through the origi with agle θ as illustrated i Figure 3. For such lie, we ca draw the orthogoal lie goig through a pixel (x, y). The value of ρ correspods to the distace to the lie. I other words, a poit (θ, ρ) of θρ-space correspods to a lie of xy-space. The key idea of the Hough trasform is to vote i θρspace oly for every edge pixel i the xy-space. Let (x, y) be the pixel i xy-space, ad let p[x][y] be the value of the pixel. I this paper we process the image i raster sca order, the Hough trasform is spelled out as follows: [Covetioal Hough Trasform] for y + 1 to for x + 1 to if p[x][y] = 1 begi for θ to 179 ρ xcos θ + y si θ v[θ][ρ] v[θ][ρ] + 1 ed For simplicity, we assume that the value of ρ is automatically rouded to a iteger. I the covetioal Hough Trasform, for each poit (x, y), the values of xcosθ ad y si θ are computed for θ =, 1,...,179. If v[θ][ρ] is storig a large value, may edge pixels i the iput pixels lie i the lie i xy-space correspods to a poit (θ, ρ) i θρ-space. However, i may extreme cases, icremetal votig operatios show i the above may cause poor performace ad some error detectios. For example, while the desity of edge poits is extremely high show i Figure 1, some spurious lies might be detected by the covetioal Hough trasform. Thus, for achievig more precise lies detectio, other approaches have bee proposed. I the followig, we describe a Hough trasform algorithm based o gradiet iformatio proposed i [14]. This algorithm uses the gradiet magitude to be the weight for accumulatio of the votig operatios, ad votes oly for agles aroud the gradiet directio. B. Gradiet-based Hough trasform I the gradiet-based Hough trasform, lies detectio is performed for a gray-scale image, ot a biary image. To obtai the gradiet iformatio for a gray-scale image, we use the Sobel filter. The Sobel filter is applied o the image for approximatig the vertical ad horizotal derivatives usig a couple of 3 3 covolutios G x ad G y : G x = [ ] I, G y = [ ] I, () where I represets the iput image ad deotes the - dimesioal covolutio operatio. The two results co-

4 volved by G x ad G y are approximatios of the gradiet for horizotal ad vertical of the image, respectively. At each pixel i the image, the resultig gradiet approximatios ca be combied to obtai the gradiet magitude usig the formula: G = G x + G y. (3) We ca also compute the gradiet directio θ usig θ = ta 1 ( G y ). (4) G x Based o the gradiet directio obtaied by the above, we vote to the parameter space. However, there is a error betwee local gradiet directio ad the directio of actual lies due to the quatizatio error. Therefore, votig operatio is performed ot oly to the agle obtaied by the gradiet directio, but also agles i the viciity of it. I our implemetatio, we itroduce weighted values w that depeds o the agle as follows: { w(θ θ λ θ θ θ θ ) = λ (5) otherwise. To be suitable for the compact FPGA implemetatio, we use the weights as power-of-two umbers. Also, the votig rage is limited to [ λ, +λ] istead of the rage [, 179] i the covetioal Hough trasform. The gradiet-based Hough trasform is spelled out as follows: [Gradiet-based Hough Trasform] for y + 1 to for x + 1 to Compute G ad θ for p[x][y] for θ θ λ to θ + λ do begi if θ < the θ θ + 18 ρ xcos θ + y si θ v[θ][ρ] v[θ][ρ] + G w(θ θ ) ed Simply speakig, the gradiet-based Hough trasform votes for each pixel of the gray-scale image with a weighted value G w(θ θ ) which is proportioal to the gradiet magitude. The parameter space will be sharpeed by such votig operatios that make the accuracy higher. Our implemetatio for the computatio of the gradiet directio ad magitude is a pipelied architecture. I the followig sectio, we show the efficiet implemetatios of the gradiet-based Hough Trasform o the FPGA. IV. OUR FPGA ARCHITECTURE FOR THE HOUGH TRANSFORM This sectio describes our FPGA architecture for the gradiet-based Hough trasform usig DSP slices ad block RAMs i Xilix Virtex-7 Family FPGA XC7VX485T- as the target device [6]. Figure 4 illustrates the outlie of our architecture. The details are described as follows. A. Structure for the computatio of gradiet iformatio I our architecture, we use a 3 3 Sobel filter to obtai gradiet iformatio. Sice we assume that iput pixels are give to the circuit i the raster sca order, we use a twolies buffer with block RAMs to provide pixels i each 3 3 subimage to the filter. Our circuit computes the horizotal ad vertical derivative approximatios usig combiatioal circuits as show i Figure 5, where dout, dout1 ad di represet pixel values i the three lies of the iput image, respectively. dout dout1 di ( 1) 1 ( ) ( 1) 1 Figure 5. (a) G x Gx dout dout1 di ( 1) ( ) ( 1) (b) G y Structure for the computatio of G x ad G y As metioed before, the algorithm eeds the gradiet directio ad magitude as show i Sectio III. The formulae iclude the computatio of the square root ad the iverse taget. Sice it is difficult to compute them directly o the circuit, we use the CORDIC IP provided by Xilix [9]. The CORDIC IP provides a hardware module that is fully pipelied architecture ad available easily o the FPGA. B. Structure for the computatio of ρ ad votig operatio Give the gradiet directio θ ad magitude G of each pixel are obtaied with a pipelied architecture, the circuit computes ρ ad performs votig operatio. Wheever the gradiet magitude G ad the gradiet directio θ of each pixel are give, the two couters for x ad y icremet appropriately. We use DSP slices ad block RAMs to compute xcos(θ λ),..., xcos(θ +λ). The detail of each circuit that computes xcosθ is show i Figure 6. The circuit cosists of oe DSP slice ad oe block RAM. Usig the block RAM as a look-up-table, cos θ is computed ad the DSP slice computes the product of x ad cosθ. We ote that i our implemetatio, sice two circuits ca share the two block RAMs for the look-up-table with the dual port, we use λ + 1 DSP slices ad λ+1 block RAMs to compute xcos(θ λ),..., xcos(θ + λ). For simplicity, the sharig is omitted i Figure 4 though it seems that every circuit that computes xcos θ has oe block RAM. Also, to compute y si θ (1 θ 179), we use the fact that sice pixel data are iput i raster sca order, the value Gy

5 Couter y Computatio for y si θ(1 θ 179) y si 1, y si,..., y si Iput pixels Couter x y si(θ 4) y si(θ 3) y si(θ ) y si(θ 1) y si θ y si(θ + 1) y si(θ + ) y si(θ + 3) y si(θ + 4) θ Sobel filter G xcos(θ 4) x cos(θ 3) xcos(θ ) x cos(θ 1) xcos θ xcos(θ + 1) xcos(θ + ) xcos(θ + 3) xcos(θ + 4) ρ for (θ 4 θ θ + 4)... V V 1 V V 3 V 4 V 5 V 6 V 7 V 8 V 9 V 1 V 177 V 178 V maximum filters (θ, ρ) Figure 4. The outlie of our FPGA architecture for the gradiet-based Hough trasform (λ = 4) y[] y Bak y si θ Couter θ 179,178,...,,1 block RAM LUT for si θ si θ... y si 1 y si y si 3 y si 179 Bak 1 Figure 7. Architecture to compute y k+1 si θ with oe DSP slice Figure 6. θ x LUT for cos θ Block RAM x cos θ DSP slice xcos θ A DSP slice ad a block RAM to compute xcos θ of y does ot chage while processig pixels are i a certai row. Therefore, whe pixels i a row y are processed, we pre-compute the values of (y+1)siθ for (1 θ 179) i the ext row ad store them ito the registers. Whe pixels i the ext row y + 1 are processed, the values are used. Figure 7 illustrates our architecture to compute ysiθ. We utilize a block RAM as a look-up-table to compute siθ, ad oe DSP slice to compute a product of y ad si θ. Also, we use two series of registers, called baks. Oe is used to pre-compute the values of y si θ for the ext row. The other is used to output the already computed y si θ for the

6 curret processig row. To compute the values of si θ, we successively geerate the value of θ = 179, 178,..., 1 by a couter. By iputtig them to the look-up-table, the values of si θ are obtaied. The products of y siθ are computed usig a DSP slice. Note that the values of y si θ are for the ext row. Therefore, the value of y is icremeted i advace. The obtaied values are successively iput to a bak of registers. I each bak, registers are coected i cascade as show i the figure. The values shift oe by oe util all the values are iput to the bak. Whe pixels i a row are fiished, the baks are switched. Figure 8 illustrates the architecture of V θ usig a block RAM. Give gradiet directio θ ad magitude G, the voted value G w(θ θ ) is computed, where θ is a costat value i each V θ. Sice i our implemetatio the value of w(θ θ ) is power of two show i Sectio III, it ca be computed with a subtractor ad a bit shifter. A block RAM i the FPGA is dual port architecture. Xilix Virtex-7 Family has 36Kbit dual-port block RAMs, which have two sets of ports operated idepedetly. Two sets of ports are: Port Set A ADDRA (ADDRess A), DOA (Data Output A), DIA (Data Iput A), ad Port Set B ADDRB (ADDRess B), DOB (Data Output B), DIB (Data Iput B). Let M[i] deote a data of address i of the block RAM. I read operatio of Port Set A, M[ADDRA] is output from DOA after the risig clock edge. I write operatio of Port Set A, the data give to DIA is writte i M[ADDRA] at the risig clock edge. Read/write operatios of Port Set B are the same as Port Set A. Port Set A ad Port Set B work idepedetly. I the block RAMs i the target device of this work, read/write operatios ca be cofigured as either RF (Read First) mode or WF (Write First) mode. I the RF mode, if readig ad writig operatios are performed to the same address, readig operatio is performed before the writig operatio. Hece the readig data is the data before writig data. O the other had, i the WF mode, sice the writig performed before the readig, the readig data is the updated data. However, whe a dual port is used, there is a restrictio that if read ad write operatio to the same address are performed for each port, the settig of block RAMs must be RF [3]. We use the block RAM to store the values of v[θ][ρ] ( < ρ ). Let v θ [i] deote a data of address i of the block RAM V θ. Sice ρ is give to its ADDRA, v θ [ρ] is output from DOA after the risig clock edge as illustrated i Figure 8. After that, v θ [ρ] + G w(θ θ ) is computed ad it is give to DIB. Sice ρ is give to ADDB, v θ [ρ] + G w(θ θ ) is writte i v θ [ρ]. I other words, v θ [ρ] v θ [ρ] + G w(θ θ ) is performed. At that time, accordig to the restrictio stated i the above, sice the same value of ρ may be iput cotiuously, the settig of block RAMs must be RF. Namely, whe the same value of ρ is iput cotiuously, the former voted value is ot read from the block RAM. To avoid this situatio, we use a additioal register to store the latest voted value ad if the same value of ρ is iput cotiuously, the stored value is used istead of the value read from the block RAM. θ θ Bit shift << G ρ G w(θ θ ) Figure 8. = ρ ADDRA ADDRB DIB + DOA v θ[ρ] A block RAM V θ to store v[θ][ρ] I the followig, whe all the votig operatios are completed, we utilize a maximum filter to output the fial correct idetified straight lies. The maximum filter is defied as the maximum of all pixels withi a local regio of a image. I here, for each value i the votig space, this filter copies the largest value from a 3 3 regio to it. Figure 9 illustrates our architecture to perform a 3 3 maximum filter to the voted results. Sice the voted values i the same ρ ca be obtaied from V, V 1,..., V 179, this architecture works row by row i a pipelie fashio. To perform a 3 3 maximum filter to each value i a certai row, it is cocurretly read from V, V 1,..., V 179. After that usig comparators, local maxima of each 3 eighborig votes i the row are obtaied. These local maxima are iput to shift registers. After local maxima i the 3 rows are computed, local maxima of each 3 3 votes are obtaied by computig maxima from correspodig 3 values. If the maximum equals to the origial value of the ceter i the correspodig 3 3 votes, its (θ, ρ) that represets a probable lie is iput to the shift registers ad output through the registers. C. Data represetatio The choice of data precisio is guided by the implemetatio cost i terms of area, simplicity of desig, speed ad power cosumptio. Higher precisio will lead to less quatizatio error i the fial implemetatio. O the other had, lower precisio will produce more compactio ad faster desigs with less power cosumptio. A trade-off

7 V V 1 V V 3 V 4 V 5 V 6 V 177 V 178 V 179 local maxima of each 3 eighborig votes i the row ρ i+1 local maxima of each 3 eighborig votes i the row ρ i local maxima of each 3 eighborig votes i the row ρ i 1 local maxima of each 3 3 votes if the maximum equals to the vote of the ceter i the correspodig 3 3 votes, output its (θ, ρ) (θ, ρ) Figure 9. Pipelie architecture of 3 maximum filter choice eeds to be made depedig o the give applicatio ad available FPGA resources. I this paper, the data format of iputs are 8-bit iteger of all pixels i the gray-scale image ad these values are iput i raster sca order. The coordiates (x, y) which are ecessary to compute ρ are appropriately geerated by the couters as show i Figure 4. I order to miimize chip space ad computatio time, short fixed poit represetatio of umbers is used. Cosiderig the structure of DSP slices ad block RAMs, we choose the data represetatio i our implemetatio, as follows. The data format of iputs that are values of pixels p[x][y] is 8-bit iteger. The data format of cos θ ad si θ is 16-bit fixed poit umber, which cosists of 1-bit sig, 1-bit iteger ad 14-bit fractio based o two s complemet. O the other had, the data formats of gradiet magitude G ad gradiet directio θ are 1-bit ad 8-bit itegers, respectively. The data format of ρ is 1- bit two s complemet iteger. Sice the rage of the value of θ is to 179, the data format of θ is 8-bit iteger. The data format of the voted value is 4-bit iteger. V. PERFORMANCE EVALUATION AND EXPERIMENTAL RESULTS We have implemeted the proposed architecture for the gradiet-based Hough trasform ad evaluated it o the Xilix Virtex-7 FPGA XC7VX485T-. Table I shows the experimetal results usig Xilix ISE I our implemetatio, the voted rage of the gradietbased Hough trasform show i Sectio III is set to λ = 4, that is for local gradiet directio θ, we perform the votig operatio to the rage θ 4 θ θ + 4. The rage was obtaied by our experimets. Due to the striget page limitatio, we omit how to determie the rage. However, the rage is eough to extract lies because the error betwee the agle of lies obtaied by the Sobel filter ad the actual agle is small [31]. Figure 1 shows the result of lies detectio for the covetioal Hough trasform ad the gradiet-based Hough trasform. Compared with the result of the covetioal Hough trasform, we ca see that the gradiet-based Hough trasform obtaied more correct lies ad exclude the iexistet lies. Let us evaluate the performace for a grayscale image. I our implemetatio, the circuit ca work i fully pipelied fashio. Namely, iput pixels ca be provided to the circuit clock by clock i raster sca order. To reduce the delay of the circuit, some pipelie registers are iserted ito betwee circuit elemets. It takes + 44 clock cycles to complete votig from the first iput pixel is give to its votig is fiished. Sice the iput image cosists of pixels, the votig operatios are performed i clock cycles, i.e., µs. After votig, clock cycles, i.e., µs are ecessary to output idetified straight lies with 3 3 maximum

8 Origial gray-scale Lies detectio Lies detectio image by the covetioal by the gradiet-based Hough trasform Hough trasform Figure 1. Compariso betwee covetioal ad gradiet-based Hough trasform algorithms filters. Therefore, i total, + ( + ) + 3 clock cycles, i.e., +( +) µs are ecessary to perform the gradiet-based Hough trasform. If a iput image of size 1 1 is give, our circuit ca detect straight lies i 3.859ms. Table I PERFORMANCE EVALUATION OF THE PROPOSED ARCHITECTURE FOR THE GRADIENT-BASED HOUGH TRANSFORM DSP48E1 slices (out of 8) 13 (1%) 36Kbit block RAMs (out of 13) 18 (17%) 18Kbit block RAMs (out of 6) 8 (1%) Slices (out of 67) 8181 (13%) Clock frequecy [MHz] 6.61 For the purpose of estimatig the speed up of our FPGA implemetatio, we have also implemeted a software approach of the gradiet-based Hough trasform usig GNU C. We have used Itel Xeo X746 ruig i.66ghz ad 18GB memory to ru the sequetial algorithm for the gradiet-based Hough trasform. For the image show i Figure 1(a) whose size is , the software implemetatio ca perform the gradiet-based Hough trasform i ms. O the other had, our circuit ca perform it i µs. Therefore, our FPGA implemetatio attais a speed-up factor of more tha 39 over the sequetial implemetatio o the CPU. There are a umber of literatures reported to implemet Hough trasform for lies usig the FPGA show i Sectio I. Algorithms, that is covetioal or gradiet-based, ad performaces such as device, logic blocks, DSP slices, frequecy ad throughput are compared i Table II. It is difficult to directly compare to other works because used algorithms, utilized FPGAs ad supported size of images differ. Cosiderig the throughput, however, it is clear that the performace of our FPGA implemetatio is better tha that of other works. VI. CONCLUSIONS We have preseted a efficiet implemetatio of the gradiet-based Hough trasform for gray-scale images usig DSP slices ad block RAMs i the Virtex-7 Family FPGA. We have implemeted the circuit usig 13 DSP48E1 slices, 18 block RAMs with 36Kbits ad 8 block RAMs with 18Kbits o the Virtex-7 Family FPGA XC7VX485T-. The experimetal results show that the architecture rus i 6.61MHz ad for a gray-scale image, our circuit ca perform i + ( + ) + 3 clock cycles, i.e., +( +) µs, icludig the computatio of gradiet iformatio. REFERENCES [1] Xilix Ic., 7 Series FPGAs DSP48E1 Slice (v1.6), 13. [] J. L. Bordim, Y. Ito, ad K. Nakao, Acceleratig the CKY parsig usig FPGAs, IEICE Trasactios o Iformatio ad Systems, vol. E86-D, o. 5, pp , May 3. [3], Istace-specific solutios to accelerate the CKY parsig for large cotext-free grammars, Iteratioal Joural o Foudatios of Computer Sciece, pp , 4.

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