Efficient Hardware Design for Implementation of Matrix Multiplication by using PPI-SO

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1 Efficiet Hardware Desig for Implemetatio of Matrix Multiplicatio by usig PPI-SO Shivagi Tiwari, Niti Meea Dept. of EC, IES College of Techology, Bhopal, Idia Assistat Professor, Dept. of EC, IES College of Techology, Bhopal, Idia ABSTRACT: I is paper, we have proposed oe desigs for matrix-matrix multiplicatio. The oe desig differs by hardware complexity, roughput rate ad differet iput/output data format to match differet applicatio eeds. We have compared e proposed desigs wi e existig similar desig ad foud at, e proposed desigs offer higher roughput rate at relatively lower hardware cost. We have syesized e proposed desig ad e existig desig usig Syopsys tools. Syesis results shows at proposed desig o average cosumes early 30% less eergy a e existig desig ad ivolves early 70% less area-delay-product a oer. Iterestigly, e proposed parallel-parallel iput ad sigle output (PPI-SO) structure cosumes 40% less eergy a e existig structure. Keywords: - Parallel-Parallel Iput ad Sigle Output (PPI-SO), Syopsis Simulatio. I. INTRODUCTION Wi e grow i scale of itegratio, more ad more sophisticated sigal processig circuits are beig implemeted i VLSI chips. These complex sigal processig circuits ot oly demad large computatioal capacity but also have high eergy ad area requiremets. Though area ad speed of operatio remai e major desig cocers, power cosumptio is also emergig as a critical factor for preset VSLI system desigers []-[4]. The eed for low power VLSI desig has two major motivatios. First, wi icrease i operatig frequecy ad processig capacity per chip, large curret have to be delivered ad e heat geerated due to large power cosumptio has to be dissipated by proper coolig techiques, which accout for additioal system cost. Secodly, e explodig market of portable electroic appliaces demads for complex circuits to be powered by lightweight batteries wi log times betwee re-charges (for istace [5]. Aoer major implicatio of excess power cosumptio is at it limits itegratig more trasistors o a sigle chip or o a multiple-chip module. Uless power cosumptio is dramatically reduced, e resultig heat will limit e feasible packig ad performace of VLSI circuits ad systems. From e evirometal viewpoit, e smaller e power dissipatio of electroic systems, e lower heat pumped ito e surroudig, e lower e electricity cosumed ad hece, lowers e impact o global eviromet [6]. Matrix multiplicatio is commoly used i most sigal processig algorims. It is also a frequetly used kerel operatio i a wide variety of graphics, image processig as well as robotic applicatios. The matrix multiplicatio operatio ivolves a large umber of multiplicatio as well as accumulatio. Multipliers have large area, loger latecy ad cosume cosiderable power compared to adders. Registers, which are required to store e itermediate product values, are also major power itesive compoet [7]. These compoets pose a major challege for desigig VLSI structures for large-order matrix multipliers wi optimized speed ad chip-area. However, area, speed ad power are usually coflictig hardware costraits such at improvig upo oe factor degrades e oer two. Wi e focus o low power desig approach, it was foud at much of e progress i e field has bee o compoet research: better batteries wi more power per uit weight ad volume; low power CPUs; very low power radio trasceivers; low power displays. Though low-power compoets ad subsystems are essetial buildig blocks for portable systems, we cocetrate o architectural level desigig for achievig at goal. A system wide Copyright to IJIRCCE 00

2 architecture is beeficial because ere are depedecies betwee subsystems, e.g. optimizatio of oe subsystem may have cosequeces for e eergy cosumptio of oer modules. Therefore, eergy reductio techiques have to be applied i all desig levels of e system. Furermore, as e most effective desig decisios are derived from e architectural ad system level, a cautious desig at ese levels ca reduce e power cosumptio cosiderably [8]. We have proposed desig for implemetig e matrix multiplicatio operatio i hardware keepig e goal of a power efficiet architecture. These desigs are verified usig various hardware simulatig tools.the etire paper has bee partitioed ito four parts. I II, proposed architectures for matrix multiplicatio have bee discussed. I III, hardware complexity ad performace compariso of e proposed structure is discussed. I IV, coclusios ad future scope of e paper work has bee preseted. II. PROPOSED ARCHITECTURE The objective of our paper work was to desig efficiet low power architecture for matrix multiplicatio operatio. From e earlier reported works i is field, e major power cosumig resource were foud to be multipliers ad e registers, used to store ad move e itermediate data. So, we have proposed ree desigs which reduce as well as optimize e umber of multipliers ad registers beig used i e matrix multiplicatio operatio. For e ease of recogitio we have amed e desigs o e basis of iput ad output dataflow. Let us cosider e matrix matrix multiplicatio for two matrices A ad B give by- C c c = A c c a a B a a b b () b b Such at, c ij = k= a ik b kj () for all i, j, a ik, b kj, ad c ij represet elemets of e matrices A, B ad C. Proposed Parallel-Parallel Iput ad Sigle Output(PPI - SO) I is desig we have reduced e resource utilizatio i terms of umber of multipliers ad registers i lieu of e completio time. This desig is particularly useful where resources are limited ad desig ca be compromised o basis of icreased completio time. The basic workig model for a 3 3 matrix-matrix multiplicatio is show i Figure below. Copyright to IJIRCCE 0

3 b 3,b,b a,a, a, a,a,a,a 3,a 3,a 3 b 3, b, b b 3,b,b LIER- b 3, b, b LIER- a,a,a, a,a, a, a 3, a 3, a 3 ADDER c 33,c 3,c 3, c 3, c, c, c 3,c,c b 3, b, b LIER-3 a 3,a 3,a 3, a 3,a 3, a 3, a 33, a 33, a 33 Figure : Proposed PPI SO Desig for = 3 From equatio, we observe at each elemet of e output matrix, C, is computed by multiplyig ad accumulatig e elemets of e correspodig row ad colum of e iput matrices, A ad B respectively. This basic idea is exploited i e desig. Cosiderig e matrix matrix multiplicatio of two matrices, e calculatio is performed usig umber of multipliers, umber of registers ad - umber of adders. Cycles are required to perform e matrix multiplicatio operatio. Each multiplier has two iput ports: oe each from matrix A ad B. I each cycle, umbers of multiplicatios are performed ad e products are fed to e adder block to give a sigle elemet of e output matrix, C. The data flow to e multipliers are such at, k multiplier is fed from k colum of matrix A ad k row of matrix B, where < k <. At e k multiplier, each elemet from matrix A is repeated for cosecutive cycles whereas e elemets from matrix B are cycled back after cycles. The partial products are e fed to e adder which computes e fial result. For a better uderstadig of e process, let us cosider e matrix multiplicatio for = 3 (as show i figure ). I is case, 3 multipliers ad 3 registers are used to calculate ad store e partial products respectively. These partial products are e fed to e adder block to compute e fial result. The first multiplier receives iput from e first colum of matrix A (a k ) ad first row of matrix B (b k ), where. Each elemet of e matrix A at e first multiplier is repeated for 3 cycles, such at e data flow ca be represeted as a a a a a a a 3 a 3 a 3.Similarly, at e first multiplier, e elemets of B are repeated after 3 cycles, such at e iput data-flow will be b b b 3 b b b 3 b b b 3. The oer two multipliers receive e compoet of A ad B i e similar order as e first multiplier. After e multiplicatio, e partial products are fed to e adder which computes e elemets of output matrix C i row major order give byc c c 3 c c c 3 c 3 c 3 c 33. So e etire matrix multiplicatio operatio is performed i =9 cycles. III. SIMULATION RESULT For a matrix multiplicatio, PPI SO desig uses multipliers ad registers. This desig is optimized for reduced compoet use ad has a pealty of icreased operatig times ( cycles). The iput is obtaied rough ports ad output is calculated out by a sigle port. This desig was compared wi prevalet matrix multiplicatio Copyright to IJIRCCE 0

4 architecture proposed by Jag et al. [] to show for e improvemets obtaied. A comparative eoretical aalysis is give i Table. Table shows sigificat reductio i umber of registers used ad computatio completio time for all proposed architectures over desig of Jag et al []. For a better aalysis, let us cosider e hardware complexities ivolved i a 8 8matrix multiplicatio which forms e basis for DCT computatio. DCT matrix ca be cosidered as a suitable iput for all ree proposed desigs. The aspect ratio of DCT matrix beig = 8 a proper aalysis ca be performed for at size. Table : Theoretical comparative hardware aalysis Matrix Size Desig by Jag et al. [] Proposed PPI SO Number of Iput Ports Number of Output Ports Number of Multipliers Number of Registers + 5 Completio Time (cycles) + Table : Syesized results for matrix size =8 Outputs per cycle Data Arrival Time (s) Area (sq. μm) Power (μw) ADP (sq. μm-ms) PPO (μw) Eergy (pj) Jag et al. [] Proposed SO PPI Table shows e Syopsys tools syesized results for matrix multiplicatio for matrix size = 8. The table shows similar results as obtaied for oer matrices of size = 3 to = 7. PPI SO provides better roughput rates ad eergy requiremets. IV. CONCLUSION AND FUTURE SCOPE Most of e digital sigal processig (DSP) algorims is formulated as matrix-matrix multiplicatio, matrix-vector multiplicatio ad vector-vector (Ier-product ad outer-product) form. Few such algorims are digital filterig, siusoidal trasforms, wavelet trasform etc. The size of matrix multiplicatio or ier-product computatio is Copyright to IJIRCCE 03

5 usually large for various practical applicatios. O e oer had, most of ese algorims are curretly implemeted i hardware to meet e temporal requiremet of real-time applicatio [9]. Whe large size matrix multiplicatio or ier product computatio is implemeted i hardware, e desig is resource itesive. It cosumes large amout of chip area ad power. Wi such a vast applicatio domai, ew desigs are required to cater to e costraits of chip area ad power ad high speed. I is cotext, we have proposed ree desigs for power efficiet implemetatio of matrix-matrix multiplicatio. The ree desigs differ by hardware complexity, roughput rate ad differet iput/output data format to match differet applicatio eeds. We have compared e proposed desigs wi e existig similar desig ad foud at, e proposed desigs offer higher roughput rate at relatively lower hardware cost. As observed rough performace compariso, proposed PPI SO desig cosumes sigificatly less eergy a e oer proposed desig. This is maily due to e less umber of iput ports of e desig. A eergy-efficiet desig could be derived by optimizig e umber of iput ad output ports furer. REFERENCES [] T. Arsla, D.H. Horrocks, ad A.T. Erdoga, Overview ad Desig Directios for Low-Power Circuits ad Architectures for Digital Sigal Processig, IEE Colloquium o Low Power Aalog ad Digital VLSI: ASICS, Techiques ad Applicatios, pp. 6/ 6/5, 995. [] L. Beii, G. De Micheli, E. Macii, Desigig Low-Power Circuits: Practical Recipes, IEEE Circuits ad Systems Magazie, vol., o.,pp. 6-5, 00. [3] M. Horowitz, T. Idermaur, R. Gozalez, Low Power Digital Desig, IEEE Symposium o Low Power Electroics, pp. 8-, 994. [4] MassoudPedram, Desig Techologies for Low Power VLSI, Ecyclopedia of Computer Sciece ad Techology, pp. 3,995. [5] Pramod Kumar Meher, Hardware-Efficiet Systemizatio of DA-Based Calculatio of Fiite Digital Covolutio, IEEE Trasactio o Circuits ad Systems, vol. 53, o. 8, pp , 006. [6] Pramod Kumar Meher, New Approach to Look-Up-Table Desig ad Memory-Based Realizatio of FIR Digital Filter, IEEE Trasactio o Circuits ad Systems, vol. 57, o. 3, pp , 00. [7] R.B. Urquhart ad D. Wood, Systolic matrix ad vector multiplicatio meods for sigal processig, i IEE Proceedigs FCommuicatios, Radar ad Sigal Processig, vol. 3, o. 6,pp.63 63,984. [8] S. Tugsiavisut, S. Jirayucharoesak ad P. A. Beerelt, A Asychroous Pipelie Comparisoswi Applicatios to DCT Matrix-vector Multiplicatio, i Proceedigs of e 003 Iteratioal Symposium o Circuits ad Systems(ISCAS), vol. 5, pp. V-36 - V-364, 003. [9] J. Lloyd, Parallel Formulatios of Matrix-Vector Multiplicatio for Matrices wi Large Aspect Ratios, i IEEE Proceedigs of e Four Euro micro Workshop o Parallel ad Distributed Processig, pp. 0-08, 996. [0] O. Mecer, M. Morf, ad M. J. Fly, PAM-Blox: High performace FPGA desig for adaptive computig, i Field Programmable Custom Computig Machies (FCCM), pp , 998. [] A. Amira, A. Bouridae, ad P. Milliga, Acceleratig matrix product o recofigurable hardware for sigal processig, i Proceedigs Iteratioal Coferece o Field-Programmable Logic ad Its Applicatios (FPL), pp. 0, 00. [] Ju-Wook Jag, Seoil B. Choi, ad Viktor K. Prasaa, Eergy- ad Time-Efficiet Matrix Multiplicatio o FPGAs, IEEE Trasactio o Very Large Scale Itegratio (VLSI) Systems, vol. 3, o., pp , 005. Copyright to IJIRCCE 04