Midterm Examination. Problems Points Total 40. yes

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1 The University of Toledo s11ms_fpga.fm - 1 Midterm Examination Problems Points Total 0 Was the exam fair? yes no /1/11

2 The University of Toledo s11ms_fpga.fm - Problem 1 10 points Hint #1 For full credit, mark your answers yes, no, or not applicable for all offered choices! 1. 1 The programming technologies of the reprogrammable CPLDs and FPGAs include: x the oxide-nitrite-oxide antifuse, x the metal-metal fuse, x the static RAM cell programming technology. x the dynamic RAM cell programming technology. x the EPROM cells based on floating-gate avalanche MOS. x the antistatic RAM cell programming technology. 1. The effect known as supply bounce affects the logical values of signals at the: x DC output pads of FPGAs, x power input pads of FPGAs, x inputs of the logic gates internal to the FPGA, x clock input pads of FPGAs, x AC input pads of FPGAs, 1. Virtex II series ilinx FPGAs contain configurable memory elements, x outside the CLBs, x inside the CLBs x inside the CLB s functional units, x inside the CLBs, but outside functional units, x inside the CLB s carry chains. /1/11

3 The University of Toledo s11ms_fpga.fm - 1. Applicable propagation delay types affect the simulation results in the following ways, x unit delays produce correct functionality, x actual delays produce realistic timing simulation, x zero time delays cannot obscure the propagation of events, x unit delays can obscure the propagation of events, x actual delays produce correct functionality. 1.5 Synthesis tools perform conversion of representations of digital circuits, x register transfer tool converts RTL models into Boolean function models, x behavioral synthesis tool converts logic circuit models into algorithmic models, x logic synthesis tool converts Boolean function models into logic circuit models, x register transfer tool converts RTL models into algorithmic models., x logic synthesis tool converts algorithmic models into Boolean function models. /1/11

4 The University of Toledo s11ms_fpga.fm - Problem 15 points Fig..1 shows a part of the ilinx Logic Cell Array (LCA) which includes eight Configurable Logic Blocks (CLB) and a partial graphical representation of the accompanying interconnect resources. K CLB1 Q F CG K CLB Q FCG K CLB Q F CG K CLB Q FCG K CLB5 Q F CG K CLB6 Q FCG K CLB7 Q F CG K CLB8 Q FCG Fig..1 A partial graphical representation of the interconnection resources in a ilinx C000 FPGA..1 Assuming that single and double length lines are accessible from CLBs whose PIPs are shown as crossing these lines, determine the routing of the minimum time delay interconnection from the output Q of CLB, to input F1 of CLB7. Highlight carefully in Figure.1 the wire segments included into the minimum time delay interconnection path.. In the space reserved for Figure., prepare the RC model of the minimum time delay interconnection that you have highlighted in Figure.1. 1 R p1 C p1 R p 10C p C p 0 C L C p1 C p1 C L C p 10C p R p C p1 Q CLB F1 CLB7 Fig.. The RC model of the interconnection path between Q(CLB) and F1(CLB7) in Figure.1. /1/11

5 The University of Toledo s11ms_fpga.fm - 5. Using the worst case parameter values from table 7., complete the model of Figure. by determining the values of the parameters of all resistors and capacitors in the model...1 Switching matrix model parameters R p1 =1.kΩ C p1 =1 ff.. PIP model parameters R p =1.kΩ C p =1 ff.. Single-length line parasitic capacitance to ground C L =C LY = 75fF.. Total parasitic capacitance to ground at a node represented by a single/double length wire segment in Figure.1, C W = C p1 + C p + C L + C p1 = 6C p1 + C p + C LY = ( ) = 70 ff..5 Total parasitic capacitance to ground at the node of a terminal of a CLB in Figure.1, C T = 10C p = = 10 ff. Prepare the expression of the Elmor s time constant for the interconnection path from Q(CLB) to F1(CLB7) in terms of the elements of the RC circuit shown in Figure.. t D = R 1 C 1 + R C + R C = = R p C W +(R p1 +R p )C W + (R p1 +R p )C T.5 Using the parameter values calculated in part., evaluate the expression of the Elmor s time constant. t D = (R p1 +Rp)C W + (R p1 +Rp)C T = R p1 CW + R p1 CT = R p1 (C W + C T ) = (70 +10) = = = 1.5nsec /1/11

6 The University of Toledo s11ms_fpga.fm - 6 Problem 15 points Figure -1 shows the architecure of a state machine whose design ought to be verified using a cyclebased simulator. In the architecture shown in Figure.1, - modules labelled by CG6, CG7, CG8, CG9, CG10, CG11 and CG1 represent the seven combinational logic gates, - modules labelled R, R and R5 represent state registers, - terminals labelled S1 and S represent external signal inputs, - clock signal connection to registers is not shown. S1 CG9 CG10 CG11 CG1 R CG8 R S CG6 CG7 R5 Figure.1 Architecure of a state machine whose design ought to be verified by cycle-based simulation. Determine a necessary order of evaluation of outputs of combinational logic gates which will satisfy the requirement that, no gate is evaluated before all its inputs have been evaluated. Hint #1 For full credit, give answers to all questions, prepare all required circuit diagrams, write all equations for which the space is reserved, and show all algebraic and numerical expressions whose evaluation produces shown numerical results. Solution An explicit demonstration of understanding the following solution steps is expected..1 Prepare a graphical representation of the gate digraph G G (V G,E G ) of the combinational subcircuit in the architecture of Figure.1, and show its drawing in the space reserved for Figure.(a). Label the vertices of the set V G in the following way: - vertices representing the input signal terminals S1 and S: labelled by 1 and respectively, - vertices representing the registers R, R and R5: labelled by, and 5 respectively, - vertices representing combinational gates CG6 through CG1: labeled by the order numbers of gates, 6, 7, 8, 9, 10, 11, and 1 respectively. /1/11

7 The University of Toledo s11ms_fpga.fm - 7 Vertex Adjacency set (a) (b) Figure. Gate digraaph G G (V G,E G ) of the combinational sucircuit in the architecure of the state machine of Figure.1(a)Graphical representation of G G. (b)set of adjacency sets of G G.. Prepare the set of adjacency sets of G G and show it in the space reserved for Figure.(b).. Perform the depth-first search of G G starting with the following two initialization steps: 1 o include into sequence V R all vertices representing input signals to the combinational logic subcircuit, o start the search from the vertex labelled "1".. Show the progression of the search and the determined evaluation order by filling in the three ordered vertex sequences in Figure.. Expansion sequence V R : Processing sequence V P : Oredering stack V F : Figure. Three vertex sequencies generated by the DFS of G G..5 Determine the order of evaluation of combinational gates for cycle-base simulation. Show the determined order in the space reserved for Figure.. Evaluation order of combinational gates is CG9 CG10 CG11 CG8 CG1 CG6 CG7 Figure. The determined order of evaluation of combinational gates. /1/11