ECE 551: Digital System Design & Synthesis

Transcription

1 ECE 551: Digital System Design & Synthesis Lecture Set 9 9.1: Constraints and Timing (In separate file) 9.2: Optimization - Part 1 (In separate file) 9.3: Optimization - Part 2 04/14/03 1 ECE Digital System Design & Synthesis Lecture Optimization and Timing Analysis - Part 2 Overview Controlling Hierarchical Boundaries Controlling Logic-Level and Gate-Level Optimization 04/14/03 2

2 References Design Compiler User Guide Design Compiler Reference Manual: Optimization and Timing Analysis 04/14/03 3 Controlling Hierarchical Boundaries Removing Levels of Hierarchy Merging Cells from Different Subdesigns Optimizing Across Hierarchical Boundaries 04/14/03 4

3 Removing Levels of Hierarchy Optimization does not cross hierarchical boundaries Potential for preventing effective optimization Particularly problematic for combinational circuits Techniques Ungroup before optimization Explicit Ungrouping during optimization Automatic Ungrouping of Small Hierarchies 04/14/03 5 Ungroup Before Optimization Ungroup merges subdesigns into parent cell or design Some subdesigns may lose constraints The default ungroup affects only the top level of the hierarchy within the parent cell or subdesign To recursively ungroup downward add option - Command: ungroup -all - Can have list of arguments 04/14/03 6

4 Explicit Ungroup During Optimization Command: set_ungroup or ungroup _all Applies to specified cells or referenced designs Cancelled by set_ungroup (object) 04/14/03 7 Automatic Ungrouping of Small Hierarchies Set compile_auto _ungroup_num_cells # where # is limit on number of cells to be ungroup. Enter command compile -auto_ungroup Command begins execution at the bottom of the current hierarchy so is in effect recurs. So ungrouping is recursive Will not apply ungrouping in cases where: Wire-load models in hierarchy different than parent Certain constraints are on hierarchical pins 04/14/03 8

5 Merging Cells from Different Subdesigns Groups cells into new design group {cell_1, cell2} -design cell_pair current_design = cell_pair ungroup -all current design = top design 04/14/03 9 Optimizing Across Hierarchical Boundaries - 1 Boundary Optimization Crosses subdesign boundary through ports looking for: constants unconnected pins complementing Commands (in dc_shell) compile -boundary_optimization //on current design set boundary_optimization subdesign_name 04/14/03 10

6 Optimizing Across Hierarchical Boundaries - 2 For constants: Propagate from input ports to contract logic For unconnected pins: Propagate x from output ports to contract logic For complements: If signal that is complement of one specified on port is available, it will be used if cost reduced 04/14/03 11 Controlling Logic-Level and Gate-Level Optimization Concepts Goal to first order is reduction of product terms Relates to be delay and area Designs typically hierarchical and consist of d and random logic Datapaths are often d logic Control functions such as instruction decoding are structurally random 04/14/03 12

7 Concepts (continued) For effective optimization, may require application of different optimization techniques Structured - Preserve and build on existing Random - Remove redundancy and improve the 04/14/03 13 How Design is Optimized - 1 Two Levels Logic level - Boolean equations Gate level - Interconnection of target library cells Logic level optimization Flattening - reducing the equation to two levels Structuring - Finds shared terms to reduce area - typically increases delay if not constrained 04/14/03 14

8 How a Design is Optimized - 2 Gate-Level Optimization Performs mapping of equation representation to available cells in the technology library Selects cells based on delay constraints or area constraints Overall Optimization See Fig. 4-3 DCRMO (next slide) Flattening Structuring Mapping 04/14/03 15 Overall Optimization 04/14/03 16

9 set_ & set_ Default settings _boolean _timing - map_effort medium Default settings for attribute set to _effort low _minimize single _phase _boolean _timing 04/14/03 17 About Flattening Flattening removes all intermediate variables and uses distributive laws to eliminate all parentheses. Result is a two-level sum-of-products form Can be faster due to reduced number of levels Good way to eliminate bad logic ; but also way to eliminate good logic Flatten random control logic, not highlyd designs. 04/14/03 18

10 About Flattening (continued) Not all designs can be ed Flatten designs which do not result in a huge number of product terms < 1000 Do not designs with 1,000,000 or more product terms Designs in between are unknown Guidelines If outputs consistently or for most input patterns - If contains many XORs and muxes - don t 04/14/03 19 Effect of Flattening on Speed Example: Mapped ed Design without Structuring - Fig. 4-5 DCRMO (see next slide) - three levels + inverters can be fast Flattening may place large loads on inputs resulting in speed reduction. Flattening without and with structuring - Fig. 4-6 DCUG (see slide after next) - one level vs. 5 levels 04/14/03 20

11 Mapped, Flattened Design without Structuring 04/14/03 21 Flattening With and Without Structuring 04/14/03 22

12 Enabling & Controlling Flattening - 1 Default - does not In hierarchical design, by default on the current design only - Exception - use design option with list of designs Removing: set_ -design TEST Reporting Flatten Attributes - report_compile_options 04/14/03 23 Enabling & Controlling Flattening - 2 Setting Flatten Effort -effort option where option is: low - default - appropriate for ing most designs medium - s a design beyond where DC can re it effectively high - causes the ing process to proceed until the design is completely ed or until workstation runs out of memory. Might never terminate! 04/14/03 24

13 Enabling & Controlling Flattening -3 Minimization Reduces the number and size of product and sum terms Resembles Karnaugh map reduction Types: single output -default - minimize equations for individual outputs - no product term sharing multiple output - minimize with maximum and shared product terms between outputs - see Fig. 4-7 DCRMO (See next slide). none - does not perform minimization 04/14/03 25 Single & Multiple Output Minimization 04/14/03 26

14 Enabling & Controlling Flattening - 4 Phase assignment Fig. 4-8 DCRMO (See next page) Compares and select implementations for both original circuit and its complement Complement handled and the fed into inverter. Well known that less costly version among the two 04/14/03 27 Phase Assignment 04/14/03 28

15 About Structuring Adds intermediate values and logic to design - sub-function factor evaluated and selected Results in shared terms Default - timing driven Area efficient, but may be slower if no delay constraints or if set_ -timing. Example - Fig DCRMO (See next slide) - Unconstrained structuring - more area efficient, but has eight levels of logic Example - Fig DCRMO (See slide after next) - Timing Driven Structuring (Default) 04/14/03 29 Unconstrained Structuring Example 04/14/03 30

16 Timing-Driven Structuring Example 04/14/03 31 Controlling Structuring - 1 set_ - applies only to current design unless -design option where option is list of subcircuits boolean - optimization uses Boolean relationships that are not typically in our usual algebra & don t care information and reduces circuit area. Examples: a + a = a, a + a = 1. Two algorithms selected by compile_new_boolean_ 04/14/03 32

17 Controlling Structuring - 2 Before v Introduced in v Uses ATPG (Automatic Test Pattern Generation) to manipulate logic networks! Optimizes circuit identifying high fanout nodes and attempting removal. Adds connections that make original nodes redundant Fig DCRMO (See next slide) - Boolean Optimization Example 04/14/03 33 Boolean Optimization Example 04/14/03 34

18 Improving Random Logic Designs -boolean effort option for compile_new_boolean_ set_ - boolean -boolean_effort Used to specify effort for CPU time use for structuring the designs: low -default -appropriate for most medium - More than one pass - recommended - sufficient for optimal results for most design high - All CPU-intensive strategies, multiple passes 04/14/03 35 Controlling Specific Optimization Steps Global logic restructuring Constant propagation - propagates logic constants to produce simpler logic Deleting unconnected gates Local optimizations Critical path resynthesis (enabled in higheffort compiles only) Gate sizing - upsizes critical path gates and downsizes non-critical path gates 04/14/03 36

19 Optimization Control Strategies for Structured Designs Structured Designs Datapath components Arithmetic circuits Parity circuits Selection circuits Goals Area Speed 04/14/03 37 Structured Designs: Area Optimization - 1 Choice 1: compile Is: _boolean _timing -map_effort medium Generally favors multilevel design but can handle timing constraints 04/14/03 38

20 Structured Designs: Area Optimization - 2 Choice 2: set_ compile Is: Does mapping only Assumes logic-level optimization including (and _timing) not needed 04/14/03 39 Structured Designs: Area Optimization - 3 Choice 3: set_ -boolean - boolean_effort medium compile Is: _boolean _timing - boolean_effort medium - map_effort medium 04/14/03 40

21 Structured Designs: Area Optimization - 4 Choice 3: (continued) Does some re-structuring Takes advantage of don t cares Gets rid of some redundancy 04/14/03 41 Structured Designs: Area Optimization - 5 Table 4-3 DCRMO: Comparative Analysis for 32-bit CLA (See next slide) Default reasonable Boolean optimization better Flattening tends to destroy original, so not as good In this case, phasing of only marginal value 04/14/03 42

22 Comparative Analysis for 32-bit CLA - Area 04/14/03 43 Structured Designs: Speed Optimization - 1 Choice 1: compile Is: _boolean _timing -map_effort medium Timing-driven structuring optimizes critical paths which using structuring to reduce area 04/14/03 44

23 Structured Designs: Speed Optimization - 2 Choice 2: set_ compile Is: Does mapping only Assumes logic-level optimization including (and _timing) not needed Same as Choice 2 for area! 04/14/03 45 Structured Designs: Speed Optimization - 3 Choice 3: Is: set_ set_ -boolean - boolean_effort medium compile _boolean _timing -map_effort medium 04/14/03 46

24 Structured Designs: Speed Optimization - 4 Choice 3: (continued) Removes existing Reduces number of levels to improve timing Uses timing-driven structuring to further deal with critical delay paths while optimizing area for non-critical paths 04/14/03 47 Structured Designs: Speed Optimization - 5 Table 4-4 DCRMO: Comparative Analysis for 32-bit CLA (See Next Slide) Default reasonable Flattening plus structuring reduces delay a bit Phasing reduces delay more Flattening only is counter-productive Increases critical path delay and area Removes and does not rebuild 04/14/03 48

25 Comparative Analysis for 32-bit CLA - Speed 04/14/03 49 Optimization Control Strategies for Und Designs Und Designs No datapath components No arithmetic circuits No large parity circuits Few selection circuits Random control logic Goals Area Speed 04/14/03 50

26 Und Designs: Area Optimization - 1 Choice 1: compile Is: _boolean _timing -map_effort medium Timing-driven structuring optimizes critical paths while using structuring to reduce area 04/14/03 51 Und Designs: Area Optimization - 2 Choice 2: set compile Is: _boolean _timing - map_effort medium 04/14/03 52

27 Und Designs: Area Optimization - 3 Choice 3: set_ set_ -boolean - boolean_effort medium compile Is: _boolean _timing -boolean_effort -map_effort medium medium 04/14/03 53 Und Designs: Area Optimization - 4 Choice 4: set_ -minimize multiple_output -phase set_ -boolean -boolean_effort medium compile Is: -minimize -phase _boolean _timing -boolean_effort -map_effort multiple_output medium medium 04/14/03 54

28 Und Designs: Area Optimization - 5 Table 4-5 DCRMO: Comparative Analysis for PLA Design (See next slide) Default reasonable Flattening with minimizing and structuring reduces area Boolean optimization and phasing gives further area improvement at the expense of delay Not phasing gives delay and slight area improvement! Not structuring is horrible! 04/14/03 55 Comparative Analysis for PLA Design 04/14/03 56

29 Und Designs: Speed Optimization - 1 Choice 1: compile Is: _boolean _timing -map_effort medium Timing-driven structuring optimizes critical paths which using structuring to reduce area 04/14/03 57 Und Designs: Speed Optimization - 2 Choice 2: set compile Is: _boolean _timing - map_effort medium Flattening provides a new start for structuring which may achieve improved area 04/14/03 58

30 Und Designs: Speed Optimization - 3 Choice 2 (continued): Removes existing Reduces number of levels to improve timing Uses timing-driven structuring to further deal with critical delay paths while optimizing area for noncritical paths 04/14/03 59 Und Designs: Speed Optimization - 4 Choice 3: set_ set_ compile Is: Flattening without structuring reduces path length; area intensive 04/14/03 60

31 Und Designs: Speed Optimization - 5 Choice 4: set_ set_ - effort medium compile Is: -effort medium More aggressive ing without structuring reduces path length; area intensive 04/14/03 61 Und Designs: Speed Optimization - 6 Table 4-6 DCRMO: Comparative Analysis for PLA Design (See next slide) Default reasonable With Structuring Flattening increases delay Flattening with phasing gives slight delay improvement Without Structuring Flattening reduces delay Flattening with phasing increases delay! 04/14/03 62

32 Comparative Analysis for PLA Design 04/14/03 63 Summary Many possible routes to chose from in synthesis procedures Design needs to be prepared for synthesis (uniquify, don t touch, ungroup) Separation in synthesis for d and random logic Specific choices of optimization setting better for each 04/14/03 64