Optimizing Synchronous Systems for Multi-Dimensional. Notre Dame, IN Ames, Iowa computation is an optimization problem (b) circuit

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1 Optimizing Synchronou Sytem for ulti-imenional pplication Nelon L. Pao and Edwin H.-. Sha Liang-Fang hao ept. of omputer Science & Eng. ept. of Electrical & omputer Eng. Univerity of Notre ame Iowa State Univerity Notre ame, IN me, Iowa 500 btract Time-critical ection of multi-dimenional problem, uch a image proceing application, are in general iterative or recurive. In thi paper thee ection are modeled a cyclic multi-dimenional data ow graph (FG), which are alo ued torepreent the digital circuit deigned to compute uch problem. Each node in the FG i aociated with a et of functional element in the circuit. emory element and circuit path are aociated with graph edge repreenting data dependencie. Thi new optimization technique conit of a multi-dimenional retiming being applied to the FG toreduce it cycle time while conidering memory requirement. Thi technique guarantee that all functional element of a circuitry, deigned tobe applied toproblem involving more than one dimenion, can be executed imultaneouly. The algorithm run in O(EV ) time, where V i the et of node and E i the et of edge of the FG repreenting the circuit. Introduction omputation-intenive application uually depend on time critical ection, coniting of loop of intruction alo called iteration. The deign of application-pecic olution for uch ection improve the computing performance. multi-dimenional () retiming tranformation i preented in thi tudy to achieve an additional improvement, while conidering the conequence of uch tranformation on the memory requirement. Retiming wa initially propoed by Leieron-Saxe [4] focuing on - problem. Such a technique preent a lower bound in the achievable cycle time due to the the number of delay exiting in a cycle. ot of the reearch in thi area ha followed thi approach and conequently ubect to the ame contraint []. ulti-dimenional ytem have been covered in tudie uing linear program- Thi work wa upported in part by ORU Faculty Enhancement ward under Grant No. 465, by the NSF Reearch Initiation ward IP , and by the William. ench, Jr. Fellowhip. (,0) (,) z - z - Figure : pecial cae of FG where row-wie computation i an optimization problem circuit deign, notice that z i equivalent to one regiter ming method [5, 7]. However, the parallelization of operation that require data produced on the ame iteration depend on the ue of multiple proceor. In thi paper, we utilize the concept of retiming preented in [, 6] to model the placement of regiter along the circuit data path, while conidering the conequence in the memory tructure. Thi new method i applicable to any problem involving more than one dimenion. For implicity, we ue - problem a example. The two dimenion are generically referred a row and column. Let' examine a imple example hown in gure, where node ; are adder and ; are multiplier. Figure how the equivalent digital circuit. We ued the notation zi to indicate a delay element in the i direction. If aumed that the computation follow arow-wie equence and that the total number of point in the row-direction i, then the - delay (;) can be repreented by a FIFO tructure of ize +, i.e., a erial implementation of z and z element. The z element repreenting the - delay (;0) i equivalent to only one delay. The current cycle time for thi deign i equivalent to the equential execution of two addition and one multiplication. In thi cae, the initial aumption on the computation equence trongly aect how much the deign can be optimized, ince the - retiming can not reduce the initial cycle time. y uing our algorithm, we apply a - retiming ( ; 4) to node and ( ; ) to node, reulting in the fully parallel olution hown in gure with a cycle time equivalent to one multiplication. z -

2 (3,-3) (-,) (3,-4) (-,) (-,) z - p z q - z - - z In order to enforce thee contraint, initially, we propoe the utilization of a chedule vector uch that >0for every 6= (0;0;:::;0). It i obviou that uch chedule vector exit, whenever the FG i realizable. The following theorem introduce the method of computing a legal retiming. Figure : retimed FG, ignoring the original computation equence optimized circuit deign aic Principle circuit deign i modeled a a multi-dimenional data ow graph (FG) G =(V;E; d;t), where V i the et of computation node, i.e., the functional element in the circuit deign, E i the et of dependence edge, equivalent to the circuit data path, d i a function repreenting the multi-dimenional delay, alo known a dependence vector, between two node, implicitly indicating the torage element required in the circuit deign, and t i a function repreenting the computation time of each node. We ue =(d x;d y) a a general formulation of any delay hown in a two-dimenional data ow graph (FG). n iteration i the execution of each node in V exactly once. We ay that a deign i fully parallel if all node in one iteration can be executed imultaneouly. Vector are ued to indicate the equence of computation. chedule vector i the normal vector for a et of parallel hyperplane that dene uch a equence. Node in the ame hyperplane will be executed equentially, according to a econd level of chedule aociated with the hyperplane. Weay that an FG G =(V; E;d;t) i realizable if there exit a chedule vector for the iteration pace with repect to G, i.e., d 0[3] and it ha no zero-delay cycle. n orthogonal chedule vector i achedule vector parallel to one of the axi repreenting the dimenion direction in the problem. non-orthogonal chedule vector, require a wavefront execution equence. 3 ulti-imenional Retiming n retiming r reditribute the node of an FG in the iteration pace, uch that each iteration till ha one execution of each nodeing. Thi tranformation i equivalent to a reditribution of the delay element in a circuit. retiming vector r(u) repreent delay component puhed into the graph edge u! v, and ubtracted from the edge w! u. The choice of the correct retiming function i important to guarantee the realizability of the circuit. legal retiming for an FG G tranform G in G r =(V;E; d r;t) uch that G r i till realizable. We ue a general et of contraint for a legal retiming that produce full parallelim among the node of an FG: () the iteration pace of the retimed FG G r doe not contain any cycle. () d r(e) 6= (0;0;:::;0) for any edge e E. Theorem 3. Given an FG G = (V; E;d;t), a chedule vector for G, and u V anode with all the incoming edge having non-zero delay. legal retiming r(u) i any vector orthogonal to. Proof: For ome node u with incoming edge e and outgoing edge e,.t., d(e ) 6= (0;0;:::0),in order to verify if the reulting FG i realizable, we compute the inner product of and each of the retimed dependence vector. Thu, d r(e ) = d(e ) r(u) = d(e ) >0. For e, d r(e ) = d(e ) + r(u) = d(e ). Wehavenow two cae: ae : if d(e ) 6= (0;0;:::0) then d(e ) >0, and the reulting graph i realizable. ae : if d(e )=(0;0;:::0) then d r(e )=r(u). Since d r(e ) >0 and for each edge e, >0, it i impoible to have a linear combination of thee delay vector orthogonal to ; i.e., parallel to d r(e )=r(u). Therefore, the reulting graph i realizable. Here we introduce an important corollary from theorem 3.. orollary 3. explore the capability of uing multiple value of the retiming function. orollary 3. Given an FG G = (V;E; d;t), a chedule vector for G, a vector r orthogonal to, a node u V with all incoming edge non-zero, and k, then (k r)(u) i a legal retiming. 4 emory Size onideration The nal chedule vector play an important role in the retiming proce. In thi ection, we dicu the relationhip between the chedule vector and the torage element in the circuit deign. In a two-dimenional (-) problem, a row-wie execution i equivalent to a chedule vector (0; ) and it implie that delay (; 0) mut be tranlated into ingle regiter delay element. elay of the form (d x; 0) produce queue of ize d x, which i independent of the problem ize. If i the number of point in the row-direction, the delay of the form (0;d y) are equivalent to queue of ize d y. Figure 3 how a equence of execution impoed by a row-wie computation in a two-dimenional problem. We notice the progre in the y-direction a indicated by the chedule vector (0; ), and a fater recurion in the x-direction. Nonorthogonal chedule vector dene execution hyperplane that require a more complex formulation of the queue ize. ecaue thee hyperplane are not parallel to the orthogonal axi x or y, the numberofpoint vary according to the boundarie of the iteration pace and the lope of the hyperplane. The following lemma how how to compute the

3 maximum number of integral point in an execution hyperplane for a two-dimenional iteration pace with equal number of point in both direction: Lemma 4. Given a FG G with an iteration pace of dimenion, an execution hyperplane h dened by a chedule vector =( x; y), the maximum number of integral point P (h) for h i: P (h) = max( x; y ) Proof: From the geometric contruction below, where h i a hyperplane dened by, the triangle OSP and O O P are proportional. Since OS i the ditance between two integral point, we may aume OS =, then = OP O = O SP = O x = O. y ut O and O then x and y. Therefore max( x ;. y ) Uing integral point, S h k. max( x; y) k = P (h). The ditance between hyperplane, computed by d for ome dependence d [3], and the maximum number of point in a hyperplane give u a good approximation for the upper bound of the queue ize required between the production and conumption of ome data. However, dependencie may have a diplacement component in the hyperplane direction whenever the dependence vector i not parallel to the chedule vector. Thi diplacement can add or ubtract point to that upper bound, depending on the vector direction. To compute the number of point aected by thi diplacement we ue the following lemma: Lemma 4. Given a FG G = (V; E;d;t) with an iteration pace of dimenion, a chedule vector = ( x; y) for G, u V, a equence of execution? =( y; x) for each hyperplane h dened by, and u + h, the number of point P h(d) between u + and the proection of node u in h i given by: P h(d) =? k? Proof: From the geometric contruction below, where h iahyperplane for, the ditance SU in integral point u h S α can be computed a co?. However, we know that co =?? therefore, P h(d) =? k? where the oor function i ued to guarantee the reult a an integer. U Figure 3: Iteration pace and a row-wie execution = Iteration pace and a non-orthogonal execution equence with a chedule vector (,) Following thi reaoning, the next theorem how a general formulation to compute the maximum queue ize required by a pecic delay vector for - problem: Theorem 4.3 Given a realizable FG G =(V;E;d;t), a chedule vector =( x; y) for G, and a et of hyperplane h dened by, the maximum queue ize for ome dependence i given by: Q =(d)p(h)+p h(d). Proof: Immediate from lemma 4. and 4.. If d = 0, contradicting the denition of chedule vector preented earlier, the ize of the queue for thoe delay vector would be reduced to the term P h(d), which repreent a xed ize queue not dependent on the problem dimenion. Figure 3 how an iteration pace and the execution equence for a chedule vector (; ). elay vector with value ( ; ) repreent a dependence within a hyperplane, and are tranlated into one regiter at the circuit level. In order to optimize the memory deign, we try to elect a chedule vector uch that the term d i mall or eventually zero. Therefore, we redene the contraint in the election of the chedule vector by allowing d =0. Intuitively, we know that the non-zero delay vector whoe product with could reult zero mut be the outermot dependencie in the pan of non-zero delay vector. However, we alo know that a rt tranlation of dependencie in regiter can introduce the contraint found in the - retiming. Therefore, to avoid uch contraint weintro- duce a new election criteria for. We aume, without lo of generality that all node repreent unit time operation and dene uch criteria in the following theorem. Theorem 4.4 Given a realizable FG G =(V; E;d;t) with t(v) =for any v V,ifd ;d are the outermot delay vector of G, a uitable chedule vector for obtaining full parallelim of G through retiming i one of the following: ()?, for fd ;d g and for any cycle l, if elthen d(l) 6= k for any integer k. ()?, for fd ;d g and for any cycle l, if elthen d(l) =kfor any integer k t(l). (3) uch that >0for any non-zero delay edge e E. Proof: To obtain full parallelim implie to ditribute the delay in uch away that no zero-delay edge are left after retiming. For cae (), we have P n d(ei)=d(l) for 0

4 e 0! e! e n! l = v 0 v ::: v0. Without lo of generality, aume P the rt edge have zero delay. fter retiming, d P n 0 r(e i)=rbut d(ei) =d(l)6=kr8k, then d(e i) 6= k r 8 i n, od r(e i)=d(e i) mr6=(0;0) for ome 0 m. Therefore, all edge have non-zero delay. In the econd cae, d(l) =k and k i greater than the number of edge in the cycle, then there i at leat one ditribution where t(l) edge have d r(e) =rand one edge ha d r(e) =(k t(l)+)r. ae 3 i imilar to cae ince r i not parallel to any d. ccording to the theorem above, the chedule vector i initially elected to be orthogonal to one of the outermot dependence vector. If the contraining condition are not atied, the chedule vector i elected baed on the original denition under the contraint >0. For thi lat cae, we decided to work with a chedule vector =(d +d ), where d ;d are the outermot delay vector and,.t., i not orthogonal to d or d, ince thi i a guaranteed choice that reult >0. fter chooing the chedule vector, we need to keep the retimed vector equivalent to minimum ize queue. We chooe a retiming function in uch away to produce minimum delay, a dened below: enition 4. minimum retiming function r i a legal retiming uch that there i no integral vector f and integer contant g uch that r = g f. 5 The lgorithm In a rt approach for tranforming a FG and, conequently, it equivalent circuit into a fully parallel FG, our algorithm verie if there i a negative cycle in the iteration pace whenever the retiming vector ued i parallel to any of the outermot delay vector. We call thi procedure, hown below, ParallelRetim. It i the rt ection of the main algorithm decribed later. ParallelRetim(G) /* compute the outermot dependence vector */ fd ;d g outermot (G); f ound F LSE for each d fd ;d g and f ound = F LSE do f d r gcd(d x;d y /* nd the minimum retiming function */ ) 8e E, if x r x = y r y then weight(e)= x r x ele E E feg /* modied ingle-ource hortet path follow */ count 0 0; put(u; Queue) 8u V length(u) tail lat(queue) while Queue 6= and count < V f get(u; Queue) 8 v, uch that u! e v if length(u) +(weight(e) ) <length(v) length(v) length(u) +weight(e) if v 6 Queue then put(v,queue) if u = tail then count ++, tail lat(queue) g f ound (Queue = ) g return (f ound) If the choen retiming i not valid, a new retiming vector, not parallel to any delay vector, i choen. We call the main algorithm omdr for ircuit Optimization via ulti- imenional Retiming. The mathematical decription of thi algorithm i preented below: lgorithm omdr(g) if (ParallelRetim(G) = FLSE) /* ue vector non parallel to the delay vector*/ for ( =0;d (d +d )? non-parallel to d or d ; + +); r d gcd(d x;d y /* nd the retiming function */ ) /* begin topological ort */ 8e E, if6=(0;0) then E E feg count 0 while V 6= f 8u V if outdegree(u) = 0 put(u; Queue); V V fug while Queue 6= f get(u; Queue); length(u) count 8 w,. t. w!u outdegree(w) outdegree(w) g count ++g /* compute the retiming function for each node*/ 8v V, compute r(v) =length(v)r end In the rt tep, the outermot dependence vector for a FG are computed in O(E) time through the uage of the function outermot. The rt outermot delay vector i conidered to be parallel to the retiming vector. ependence vector non-parallel to the retiming vector are conidered innite ource of delay and are removed from the graph. On the other ide, dependence vector parallel to the retiming function are tranformed into - value repreenting how many time we can retime that edge. Therefore, a typical - retiming olution i ued to verify that the retiming i legal. modied ingle-ource hortet path algorithm compute in O(V E) time the hortet path length meaured from a ingle-ource node, providing u the coecient for the nal retiming function. If the algorithm fail for both outermot edge, the greedy olution i adopted, i.e., =(d +d ) which guarantee that a olution i found. modied topological ort i ued to order the node in level, tored in the vector length, ino(e) time. Every node i aigned to a unique level number, producing the coecient for the retiming function. Thi algorithm guarantee that a fully parallel olution i achievable, and only ingle regiter, or xed number of regiter are inerted into the direct circuit path. Thee propertie are hown in the theorem below: Theorem 5. Given an FG G =(V; E;d;t), the optimization algorithm omdr tranform G to G r, uch that; () G r i realizable () G r i fully parallel (3) all zero delay edge u! v of G, after retiming, will have xed-ize queue of ize k, k, when (k r)(u) wa the retiming function applied to u. Proof: () y uing the algorithm omdr, the ingleource hortet path algorithm will detect a cycle if one

5 X(Z,Z ) Y(Z,Z ) X(Z,Z ) Y(Z,Z ) -c(,0) -c(,0) -c(,) -c(,0) -c(0,) -c(,) -c(,0) -c(0,) -c(,) -c(,) (,0) (,0) (0,) (,-4) (,-4) 5 (,) (,) (,-) (,-) Figure 4: circuit deign for an IIR lter equivalent FG Figure 5: circuit deign of the retimed lter equivalent FG exit when the retiming function i choen parallel to one of the outermot dependence edge. If a cycle i detected, a new retiming function will be ued. The retiming of each nodev ibylength(v i) r reult in nal delay vector of the form r, +r,orrwhere =length(v i). Theorem 4.4 how that a realizable graph i achievable. Item () i proven by theorem 4.4 and corollary 3.. Item (3) i immediate from theorem 4.3. On the general cae, the deired cycle time may be large enough to accommodate the equential execution of two or more operation. In uch a ituation, a light modication of the algorithm, combining thoe node that erially executed would t in the target cycle time, produce a circuit (not fully parallel) with a lower number of non-zero delay edge, atifying the pecied cycle time. Such a olution i not preented in thi paper due to pace contraint. 6 Example In thi ection we preent the application of our method to a - lter deign with tranfer function H(z ;z )= P P n =0 n =0 c(n ;n)z n z n with c(i; ) =0for= and for i = = 0. The deign i hown in gure 4. Uing the algorithm omdr, we begin by nding a poible retiming function. the outermot dependence edge are (; 0) and (0; ). The former can not be elected a bai for the retiming function due to the cycle 4!! 3! 4! 5. Therefore, the elected retiming function i r =(0;). The algorithm produce the following coecient for the retiming function: 5 i aigned to -4, node 4 and 5 to -3, 3 to -, and to -, and nally,,, 3, and 4 to 0. The reulting retiming function i: r(5) = (0; 4), r(4) = r(5) = (0; 3), r(3)=(0; ), and r()=(0; ). The nal fully parallel graph and the modied circuit deign can be een in gure 5. omparing the reult with the original cycle time, we notice that the critical path wa reduced from 4 adder and one multiplier to one functional element, with a cycle time equal to the execution time of one multiplication. Thi repreent a gain equivalent to5 time in computational time. nother important reult on thi example i that all new delay have ize one for the chedule vector =(;0). It i clear that the full parallelim produced by our algorithm will alway guarantee optimal reult with repect to the cycle time of the circuit. Reference [] L.-F. hao and E. H.-. Sha, \ Static Scheduling of Uniform Neted Loop," Proc. of the 7th Int'l Parallel Proceing Sympoium, 993, pp [] Gnanaekaran, R., \ - Filter Implementation for Real-Time Signal Proceing". IEEE Tran. on ircuit and Sytem, 988, vol. 35, n. 5, pp [3] S. Y. Kung, VLSI rray Proceor, Englewood li, NJ: Prentice Hall, 988. [4]. E. Leieron and J.. Saxe, \ Retiming Synchronou ircuitry". lgorithmica, 6, 99, pp [5] L.-S. Liu,.-W. Ho and J.-P. Sheu, \ On the Parallelim of Neted For-Loop Uing Index Shift ethod," Proc. of the International onference on Parallel Proceing, 990, Vol. II, pp [6] N. L. Pao, E. H.-. Sha, and S.. a, \ Schedule-aed ulti-imenional Retiming". Proc. of the 8th International Parallel Proceing Sympoium, 994, pp [7]. arte and Y. Robert, \ ontructive ethod for Scheduling Uniform Loop Net," IEEE Tran. on Parallel and itributed Sytem, 994, Vol. 5, no. 8, pp [8] R. Taran, ata Structure and Network lgorithm, SI, Philadelphia, P, 983.