HyperLynx 教程. Pre-layout (LineSim):

Transcription

1 HyperLynx 教程 Pre-layout (LineSim): Signal-integrity and EMC analysis Crosstalk and differential-signal analysis Analysis for gigabit-per-second, SERDES-based designs Stackup and impedance planning Post-layout (BoardSim): Signal-integrity analysis and batch-mode simulation Crosstalk and differential-signal analysis Analysis for gigabit-per-second, SERDES-based designs Multi-board, system-level simulations

2 Pre-Layout Analysis: LineSim 页码,1/9 Pre-Layout Analysis: LineSim User Quotes... LineSim is installed and working just great!... It's terrific. It should be on every engineer's PC. - Engineer, and new LineSim User... a great tool for emergencies when we found a problem in production... It let me try a number of solutions quickly... and reduce the time it took to get the fix done... I proved the accuracy to myself and others by comparing LineSim results to actual measured waveforms. Even our consultant was so impressed that he bought it for himself. - Technical Specialist/Manager, Fortune 500 Office Equipment Manufacturer... the most user-friendly signal integrity software on the market. - PCI Bus Pioneer, Large Microprocessor Manufacturer The rapid prototyping capabilities and ease-of-use of the tool (LineSim) allowed multiple topologies to be tried and simulated... Without this tool, the circuit would have failed in the lab, and... would not have been able to be corrected without a board re-spin. With the rising cost of board re-spins and the need to shrink a product's time to market, it is essential that a tool of this nature be employed... in order to get new designs and upgrades right the first time. - Hardware Engineer, Computer Systems Manufacturer Introduction Some designers assume that signal-integrity, crosstalk, and EMC analysis begin after a PCB is laid out. But one of the HyperLynx tools LineSim allows you to consider all of these effects much earlier in the design process, before layout even starts. Working at this early stage, you can develop constraints for PCB placement and routing that will give you the greatest chance of producing a successful first-prototype board. Why initiate signal-integrity, crosstalk, and EMC analysis early in the design process? Because, the earlier you begin, the earlier you catch mistakes; and the sooner you catch mistakes, the less time and money you spend fixing them. It's been estimated that it costs 10 times more to fix a mistake after PCB layout than before, and another 10 times more to fix it after prototyping than before. That's a factor of 100 in terms of real, total cost you can save by starting early. How LineSim Works LineSim allows you to quickly enter and solve "what-if" signal-integrity, crosstalk, SERDES, and EMC problems at any stage of the design cycle. Analysis is based on your choice of two unique editors created specifically for entering schematics representing physical interconnects (as you need to for signal-integrity and EMC simulations). LineSim s classic editor is a super-fast, point-and-click way of very quickly entering transmission-line schematics (especially smaller ones). LineSim s "free-form editor is also easy to use and learn, but better-suited for larger schematics or designs involving external SPICE or Touchstone models. Using either editor, signal-integrity and crosstalk results appear as waveforms or eye diagrams in an oscilloscope; EMC simulation occurs in the frequency domain and results appear in a spectrum analyzer. To run LineSim, you do not need to interface to any other software tool, e.g., PCB layout. Instead, you enter problems directly in LineSim's special interface, then get immediate results. Why does LineSim work from a special "interconnect" or "transmission-line" schematic rather than an ordinary PCB schematic? Because ordinary PCB schematics do not contain the physical information needed for signal-integrity, crosstalk, GHz-level, and EMC analysis. Consider a clock net on a PCB schematic: it is drawn as a "wire" that connects a driver IC to several receiver ICs. However, the schematic tells nothing about how the "wire" is actually constructed. For example, is it a simple PCB trace on a board's outer layer, or a more-complex trace that uses outer and inner layers, and passes through one or more vias? These kinds of physical details determine how the clock net behaves from a signal-integrity and EMC standpoint. LineSim is optimized for efficient input of physical schematics, allowing easy what-if analysis. Circuit mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/pre_layout_analysis_li...

3 Pre-Layout Analysis: LineSim 页码,2/9 elements transmission lines, ICs, and passive components are added with a simple click of the mouse button. Physical parameters including coupled cross sections for transmission lines are modeled by right-clicking on any element. Simulating a Simple Clock Net In LineSim Suppose you're about to start a board design. Of all the signals on a PCB, clock nets are usually the most critical from a high-speed-design standpoint. (SERDES-based designs don t use clock signals, but here we're discussing traditional, synchronous designs.) Let's see how LineSim could help you make important signalintegrity decisions about your clock net before you even begin drawing your board's logic schematic. Since this example involves just a simple interconnect schematic (as an introduction to the tool), let s use the classic LineSim cell-based editor. In later examples, we ll try the free-form editor. Load the Demo Schematic "Clock.tln" In this demonstration, you can only simulate the schematics supplied with the demo (you can't create your own). Let's begin by loading a schematic representing a simple clock net. Load the demo schematic "Clock.tln" using File > Open LineSim Schematic: 1. On the File menu, select Open LineSim Schematic. A dialog box opens. 2. Double-click on the file name "Clock.tln". (Schematics drawn with the cell-based editor use the.tln extension.) The dialog box closes and a schematic appears in LineSim's editor. The schematic is drawn vertically to fit better in LineSim's half window for this demo. The triangular symbol at the top represents a driver IC. Next are two transmission-line symbols, one labeled as "microstrip" and one as "stripline." In the middle and at the bottom are more triangular symbols, representing receiver ICs. Together, these make up a schematic of a simple clock net with a driver IC, a PCB trace routed on a board's outer layer (the "microstrip") to a receiver IC, and a trace routed on an inner layer (the "stripline") to another receiver. In a moment, we'll see how this schematic was drawn. But first, let's run a quick simulation to see how this hypothetical daisy-chained clock net would behave if you actually built it on a board. Simulate the Clock Net Before simulating, notice in the schematic that each IC symbol is marked with a colored arrow. These indicate that the ICs are attached to oscilloscope probes; the arrow color corresponds to the channel color in the oscilloscope. Now, simulate the clock net using Simulate > Run Interactive Simulation; set the oscilloscope to a 50-MHz clock and the timebase to 5 nsec/div: 1. On the Simulate menu, select Run Interactive Simulation. The Digital Oscilloscope dialog box opens; you can increase its size by dragging its corners with the mouse. 2. In the Driver Waveform area, select the Oscillator radio button. 3. In the MHz box, type "50". 4. In the Horizontal Scale area, click the up arrow button twice to change the timebase to 5 nsec/div. 5. Click the Start Simulation button. Unless your computer is quite slow, the simulation should take only a few seconds or so to complete. The waveforms on the screen are the actual voltages you'd see if you built the clock net described on the schematic. Notice that the voltages at the receiver ICs (the yellow and purple oscilloscope traces) show a large amount of overshoot / undershoot so much that the receiver ICs "see" at least one extra clock edge per cycle. To view this problem more clearly, let s plot the receiver ICs' thresholds in the oscilloscope. Display a receiver s threshold by choosing component U(A1) in the Thresholds For combo box: In the oscilloscope, pull down the Threshold For combo box and select component U(A1). Notice that two dashed, dark blue horizontal lines appear in the oscilloscope; these are the receiver ICs 0.8-V and 2.0-V input thresholds (Vil and Vih). (They were read automatically by LineSim from the receiver s IC models.) Sure enough, the falling-edge waveform crosses the Vil threshold three times, which could cause double-clocking. (If you built this clock net, your board would probably fail.) mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/pre_layout_analysis_li...

4 Pre-Layout Analysis: LineSim 页码,3/9 Also, there is considerable high-frequency content in the waveform; that is a likely source of serious EMC trouble (more on that later). Fixing the Clock Net Let's determine how to fix this clock net. Termination (i.e., adding passive components to match transmissionline impedances) is a good way of fixing many kinds of basic signal-integrity problems. In this demo version of LineSim, you can modify a schematic, but you can't modify a schematic and simulate it. You can simulate the schematics supplied with this demo (as long as you don't modify them). Therefore, we'll make changes to the schematic to see how editing is done, then load another schematic which we can simulate that has the same changes made in it. Add a Terminator to the End of the Net Add a parallel AC terminator to the end of the clock net by clicking in a resistor and capacitor; set the resistor to 50 ohms and the capacitor to 150 pf: 1. Close the oscilloscope by clicking the Close button. 2. Near the receiver IC, just below and to the right of the green "CELL:A2" label, point to the pull-down resistor shape. When you point to it, a red box appears around the resistor. 3. Click once (with the left mouse button) to make the resistor "activate." It changes color and appears in the schematic. 4. Immediately below the resistor, point to the capacitor shape, and left-click once to make it activate. 5. Point back to the resistor, and with the right mouse button, click once. The Edit Resistor Values dialog box opens. 6. In the Resistance box, type "50". Click OK. 7. Point to the capacitor, and again with the right mouse button, click once. The Edit Capacitor Values dialog box opens. 8. In the Capacitance box, type "150". Click OK. This demonstrates how schematics are created in LineSim s fast, cell-based editor: left-click on grayed-out elements (transmission lines, ICs, terminating components) to activate them and add them to the schematic right-click on an element to model its physical characteristics (select an IC model, specify an impedance, change a value, and so forth) Notice how fast this is: there are no symbols to select and even no wiring to perform. The 50-ohm value for the terminating resistor is a guess based on the fact that a terminator should match the impedance of the transmission line it's terminating (note that the second line in the schematic has an impedance of about 50 ohms). The capacitor value is also a guess; generally, the longer the line being terminated, the larger the capacitor should be. (Later, we'll see how LineSim can automatically find the best terminating-component values, so you don't have to make guesses.) About modeling transmission lines and ICs: If you want more information about modeling transmission lines (as PCB cross sections, as part of a stackup, with connector models, etc.) or modeling ICs, click one of the topics below. - Click here for more information on how transmission lines are modeled (cross sections, stackups, connectors). - Click here for more information on how IC drivers and receivers are modeled. Simulate the Terminated Net Now let's simulate to see if the clock net has an improved waveform; load the schematic "Clockfix.tln" and simulate it: 1. Since you edited the schematic, it can't be simulated in the demo version of LineSim. Instead, on the File menu, select Open LineSim Schematic. A dialog box opens. 2. Double-click on the file name "Clockfix.tln". The dialog box closes and a schematic identical to the one mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/pre_layout_analysis_li...

5 Pre-Layout Analysis: LineSim 页码,4/9 you just created appears in LineSim's editor. 3. On the Simulate menu, select Run Interactive Simulation. The Digital Oscilloscope dialog box opens. 4. In the Driver Waveform area, select the Oscillator radio button. 5. In the MHz box, type "50". 6. In the Horizontal Scale area, click the up arrow button twice to change the timebase to 5 nsec/div. 7. Click the Start Simulation button. This time, the receiver ICs' waveforms (yellow and purple) look considerably better: almost all of the overshoot is gone. By increasing the capacitor's value, you could further "tune" the waveform to eliminate all of the negative overshoot this is one of LineSim's strengths: how easy it is to perform "what-if" analysis. But let's look at another circuit, and in the process, find out about an even easier way to determine optimal termination values. A Series-Terminated Net with IBIS Model We fixed the clock net by adding a parallel AC terminator at the end of the net. Let's look briefly at another net that is series terminated. Also, let's use an IBIS-format model for the driver IC. (For details on the IBIS format and how ICs are modeled generally, click here.) Load the Schematic "Ser_ibs.tln" Load the schematic "Ser_ibs.tln": 1. Click the Close button to close the oscilloscope. 2. On the File menu, select Open LineSim Schematic. A dialog box opens. 3. Double-click on the file name "Ser_ibs.tln". The dialog box closes and a new schematic appears. On this net, an IC modeled with an IBIS model drives a transmission line and receiver IC. (Scroll the schematic to the right to see the receiver, if needed.) The driver is series-terminated with a resistor, whose value is temporarily 0.0 ohms. Simulate the net with the 0-ohm resistor; set the IBIS model to Slow-Weak: 1. On the Simulate menu, select Run Interactive Simulation. 2. In the IC Modeling area, click the Slow-Weak radio button. 3. Click the Start Simulation button. The simulator runs, showing what the falling-edge signal on this net would look like: it has very little ringing. IBIS models can include min/typ/max data; let's change the model to run with best-case-fast/strong parameters. Re-simulate with the 0-ohm resistor, but change the IBIS model to run Fast-Strong: 1. In the IC Modeling area, click the Fast-Strong radio button. 2. Click the Start Simulation button. The simulation runs again, plotting over the previous simulation's results. Note how the waveform has changed: now there is considerable ringing. We need to terminate this net to protect against the faster versions of our driver IC. Run the Terminator Wizard to Find an Optimal Termination Let's change the series resistor to a value that will actually terminate the net. But instead of picking the value ourselves and "tweaking" it until it works perfectly, let's ask LineSim to pick the best value for us. This shows a powerful feature of both LineSim and BoardSim: the Terminator Wizard, a "smart" tool that can analyze nets in detail and automatically pick the best terminations to use (types and values). Run the Terminator Wizard; "apply" the resistor value it recommends; and re-simulate: 1. On the Wizards menu, click Run Terminator Wizard. A dialog box opens. mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/pre_layout_analysis_li...

6 Pre-Layout Analysis: LineSim 页码,5/9 2. In the Select a Device Pin list box, double-click U(A0). The dialog box closes, and the Terminator Wizard opens and performs its analysis. It is recommending a 28.1-ohm terminating resistor. 3. "Apply" the Wizard's recommendation to the resistor in the schematic by clicking the Apply Values button (upper right corner). 4. Close the Terminator Wizard by clicking OK. When you run the Terminator Wizard, LineSim automatically analyzes the selected net, presents a list of trace statistics, and, at the bottom of the list, makes suggestions for termination values. In this case, the Wizard correctly determines that the termination type is "series," and makes suggestions for the optimum value of R. In these calculations, LineSim automatically accounts for such effects as capacitive loading of receiver ICs, total line length, and driver impedance. In the schematic editor, notice that, because we clicked the Apply button, the resistor has changed from 0 ohms to the Terminator Wizard's recommended value of 28 ohms. Now let's simulate to see if the terminator works. Re-simulate the net; then reset the oscilloscope to 'Typical' IC modeling: 1. In the oscilloscope, click the Erase button. 2. Click the Start Simulation button. 3. Before proceeding to the following sections of the demonstration, click the Typical radio button in the IC Modeling area so that simulations are again running from typical IC data. Note how dramatically improved the waveform is. At the receiver (yellow trace), the signal is nearly perfect. By allowing just a small amount of undershoot at the receiver, the Terminator Wizard has achieved the least possible delay to the receiver IC, yet ensured that the receiver's low-side clamp diode is not turned on. The Terminator Wizard is a sophisticated tool. For example, in the analysis you just ran, it automatically determined the following information (all displayed in the Wizard dialog box): - switching impedance of the driver IC (average of high-side and low-side values) - driver slew time (again, average of high and low) - total net physical length - nominal characteristic impedance of the net - adjusted, "effective" impedance of the net, given receiver-ic loading - what kind of terminator (e.g., series, parallel AC, etc.) you're using - topology of the net, so that the Wizard knows what termination style to recommend if no terminator is present - driver-to-series-resistor stub length, in case the distance is too long - the optimal termination value to use, given all of the above Note: If you run an EMC analysis on this schematic, you won't get any radiation because the transmission line is modeled non-physically as a "simple" line. LineSim's EMC-analysis engine must have physical data about a transmission line (e.g., where it is in a PCB's stackup) in order to calculate radiation. EMC Analysis of the Clock Net We've investigated several nets' signal integrity. Now, let's consider how the clock net we saw earlier might behave from an EMC standpoint. (Later, we ll look at more signal-integrity simulations, for example, for a DDR design and SERDES example.) About EMC-Analysis Tools: EMC-analysis software is roughly divided into two categories back-end, system-level verification tools and front-end, what-if design tools. Verification tools, because they attempt to perform system-level simulations, are so modeling-intensive and cumbersome that they tend to be impractical. LineSim is a front-end design tool that's easy to run and attacks EMC problems early in the design cycle. Run the Spectrum Analyzer on the Clock Net First, re-load the original version of the clock net's schematic (load "Clock.tln"): 1. On the File menu, select Open LineSim Schematic. A dialog box opens. 2. Double-click on the file name "Clock.tln". The dialog box closes and the original version of the clock net without a terminator appears in the editor. mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/pre_layout_analysis_li...

7 Pre-Layout Analysis: LineSim 页码,6/9 Then, simulate the net to find its radiation profile, using Simulate > Run Interactive EMC Simulation. First, set up the EMC-analysis probe, using the Set button: 1. On the Simulate menu, select Run Interactive EMC Simulation. The Spectrum Analyzer dialog box opens; you can increase its size by dragging its corners with the mouse. 2. In the Probe area, click the Set button. The Set Spectrum Analyzer Probing dialog box opens. At this point, we have a decision to make. EMC behavior can be investigated by predicting the net's far-field radiation, or simply by probing its trace current directly and viewing the current in the frequency domain. Use of a current probe is especially appropriate in LineSim, because radiation prediction requires physical detail which is sometimes missing in a LineSim schematic: it's not possible to predict radiation from a purely electrical transmission line, for example (radiation algorithms require detailed stackup knowledge). But LineSim can always collect trace-current data, no matter how you construct your schematic. Note: Some EMC experts always prefer dealing just with trace currents, rather than radiation predictions. HyperLynx's radiation algorithm is powerful, but it is admittedly not able to account for the effects of attached cables, the product's enclosure, etc. By concentrating on just the frequency content of a net's currents which LineSim can predict with high accuracy you can very effectively manage your EMC problems. Let's continue, then, using a current probe: 1. In the Probe Type area, notice that both antenna and current probes are available. Select the Current radio button. Most controls in the dialog box gray out. 2. In the Pins list box, double-click on pin U(A0). The dialog box closes. Then, run the EMC simulation: 1. In the spectrum analyzer, verify that the Vertical Offset is set to 100 ma. 2. Click the Start Simulation button. The simulation runs. The spectrum analyzer works first in the time domain, collecting data, then runs an FFT to transform the current waveform into the frequency domain. Examine the Spectrum Analyzer's Results LineSim's spectrum analyzer works just like a real analyzer connected directly to a current probe. The yellow vertical bars show you the magnitude of the current at every frequency at which there is significant radiation. Notice that the current spectrum has a strong peak at the simulation's base frequency; the current level is close to 100 ma. If this net were on a real board, you would probably want to see if you could lower this peak somewhat. EMC Analysis of the Terminated Clock Net Now, let's run the "fixed" version of the clock net (the one with the AC parallel terminator added) to see if its EMC profile looks better than the unterminated net's. Remember that in the licensed version of LineSim, you could do this easily by adding the resistor and capacitor at the net's end. In this demo version, you must load a separate schematic. Run the Spectrum Analyzer on the Terminated Net First, re-load the "fixed" version of the clock net's schematic (load "Clockfix.tln"): 1. On the File menu, select Open LineSim Schematic. A dialog box opens. 2. Double-click on the file name "Clockfix.tln". The dialog box closes and the fixed version of the clock net with the terminator added appears in the editor. Then, simulate the net to find its EMC profile, using Simulate > Run Interactive EMC Simulation: 1. On the Simulate menu, select Run Interactive EMC Simulation. The Spectrum Analyzer dialog box opens. mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/pre_layout_analysis_li...

8 Pre-Layout Analysis: LineSim 页码,7/9 2. In the Probe area, click the Set button. A dialog box opens. 3. In the Probe Type area, verify that the Current radio button is selected. 4. In the Pins list box, double-click on pin U(A0). The dialog box closes. 5. In the spectrum analyzer, set the Vertical Offset to 100 ma. 6. Click the Start Simulation button. Notice that the clock net's peak current level is now substantially improved: reduced in fact, by approximately half. (It may look at first glance like less than half, but note that the vertical scale is logarithmic.) This net will therefore radiate substantially less than the unterminated version. Notice that we've made this improvement even before PCB layout: a proactive way of treating EMC problems that catches problems early in the design cycle and significantly reduces the likelihood of certification failure and redesign downstream. Notice also the connection between good signal-integrity and EMC design: the same termination improved both the signal quality and EMC behavior. About LineSim s Free-Form Schematic Editor In the examples shown earlier in this demonstration, we used LineSim s cell-based editor, which is optimized for very quick drawing of simple interconnect schematics. In the following sections, we ll switch to using LineSim s free-form editor, which more easily handles larger schematics (and allows for including SPICE or Touchstone models.) When you actually begin using LineSim, you ll have a choice of which editor to learn or you may wish to use both, for maximum flexibility. Note that the underlying dialog boxes in both editors are identical, so learning both is fairly easy. Signal-Integrity of a DDR Data Path The examples you saw earlier in this section were instructive, but very simple. Let s look at one more example for the signal integrity of a DDR data path that is more similar to the type of work you d actually do using LineSim. Load the Demo Schematic "DDR_4DIMM_data_min.ffs" Begin by loading a schematic that represents a typical DDR data path. Load the demo schematic "DDR_4DIMM_data_min.ffs" using File > Open LineSim Schematic: 1. On LineSim's File menu, select Open LineSim Schematic. A dialog box opens. 2. Double-click on the file name "DDR_4DIMM_data_min.ffs". The dialog box closes and a schematic appears in LineSim's free-form editor. Note: Running half-screen in the demonstration version, the details of the schematic are difficult to see (because the schematic automatically fits to the screen width). If you wish, you can use the View > Zoom Area In menu command to zoom into the schematic and see it in more detail. However, this is not necessary, and the instructions below are written assuming that you stay at the present zoom level. Note the difference between this editor and the one you saw in earlier examples. The free-form editor functions more like a standard schematic tool: you choose symbols from a palette, and wire them together. This technique tends to work better for large or complex designs. But otherwise, there s not much difference between the two editors: all of the associated dialog boxes (for modeling transmission line or ICs, for example) are identical. The schematic we ve loaded represents a typical topology for a DDR data path, implemented in LineSim s free-form schematic editor. (The schematic was drawn so that the entire design fits on a single page, but it could just have easily been stretched out to fit on multiple screens.) The DDR bus could be run at various speeds, but we ll try to make it work at 266 Mbs (133 MHz). The design is based on the minimum interconnect lengths allowed by the JEDEC spec; trace widths and stackup have been designed to give the desired impedances. Looking from left-to-right, the design incorporates these elements: A DDR controller, represented by an IBIS model for a Xilinx Virtex-4 SSTL2 driver Several transmission lines representing extra package parasitics (recommended by Xilinx in their IBIS model), breakout routing, and routing to the first DIMM module; plus a series termination resistor just after the breakout mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/pre_layout_analysis_li...

9 Pre-Layout Analysis: LineSim 页码,8/9 The first of four DIMM modules, consisting of the following elements: A transmission line representing the DIMM s connector Transmission lines representing routing to a series resistor on the DIMM, and then more routing A T in the routing, with transmission-line branches going to two SDRAM data inputs, each represented by a Micron Technology MT46V16M8A0 IBIS model A transmission line representing more routing, between DIMM 1 s and DIMM 2 s connectors Then DIMM2 (a copy of DIMM 1 s structure); DIMM2-DIMM3 routing; DIMM3; DIMM3-DIMM4 routing; and DIMM4 Finally, a parallel pull-up-resistor terminator, to 1.25V Simulating the DDR Data Path Let s attach some oscilloscope probes, then simulate to see how the data bus s signal integrity looks. Assign probes using Simulate > Attach Scope Probes to the following device pins controller.dqs, dimm1.front, dimm2.front, dimm3.front, and dimm4.front; in the oscilloscope, select an oscillator stimulus and set it to 133 MHz; set the horizontal scale to 2 ns/div and vertical scale to 500 mv/div; and display the thresholds at one of the receiver pins: 1. On the Simulate menu, select Attach Scope Probes. A dialog box opens. 2. In the Pins list, locate pin controller.dqs, then double-click on it; a probe is attached. Repeat for pins dimm1.front, dimm2.front, dimm3.front, and dimm4.front. Then click OK to close the probing dialog box. In the schematic, notice that a colored probe has appeared at each selected pin. 3. On the Simulate menu, select Run Interactive Simulation. The oscilloscope dialog box opens. 4. In the Driver Waveform area, click the Oscillator radio button. In the MHz box, type 133. In the IC Model area, verify that the Typical radio button is selected. 5. In the Horizontal Scale area, click the up arrow once to set the scale to 2 ns/div. In the Vertical Scale area, click the down arrow once to set the scale to 500 mv/div. 6. In the Threshold For combo box, choose pin dimm1.back. The receivers Vil and Vih threshold values are plotted in the oscilloscope display, as dashed blue lines. 7. Then click the Start Simulation button to begin simulating. The resulting waveforms show a problem: at the left-most of the DIMMs (yellow waveform), there is a noticeable anti-reflection that causes DIMM 1 s received signal to dip back slightly above the high threshold. This means that there is at least a possibility that DIMM 1 would get double-clocked. Some versions of this design would fail in the field. Improving the Data Path s Signal Integrity There are various ways you could potentially improve the data path s waveforms. One possibility is by changing termination values (especially the series resistor at the driver or pull-up at the end of the bus, which are not on the DIMM modules and therefore under our control). Let s trying changing the pull-up s value. Change the pull-up resistor s value to 22 ohms, then re-simulate: 1. Minimize the oscilloscope by clicking its minimize button (in the upper right corner: ). 2. In the schematic, point to the pull-up resistor (at the far right edge), and right-click with the mouse. On the pop-up menu, select Edit Value and Parasitics. The Edit Resistor Values dialog box opens. 3. In the Resistance box, type 22. Then click OK. 4. Find the minimized oscilloscope, and click on its restore button ( double boxes ); the oscilloscope reappears. Click the Erase button to clear the old waveforms. 5. Click Start Simulation to re-simulate. New waveforms appear. Notice that the rising edge waveform is now OK: the ringback at DIMM 1 (yellow waveform) is well above the Vih threshold. It is still marginal, though, on the falling edge (versus Vil). To improve the falling edge, recall that the schematic uses the minimum possible interconnect lengths (per the JEDEC spec). Sometimes, it actually helps to increase routing length. Let s see if that s true in this case. mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/pre_layout_analysis_li...

10 Pre-Layout Analysis: LineSim 页码,9/9 Right-click on the three transmission lines that represent the routing between DIMMs 1-2, 2-3, and 3-4; increase each line s length to 1.2 inches: 1. Minimize the oscilloscope. 2. To display all of the schematic in the window, LineSim zoomed out quite far. Let's zoom in to make it easy to read the component text. On the View Menu, click Zoom Area In. Then drag the dashed zoom rectangle around the driver for the DDR controller and the first three transmission lines connected to it. 3. Using the scroll bar near the bottom of the schematic, scroll to the right until you see TL20, labeled DIMM1 DIMM2. (If the entire label is not displayed, touch it with the mouse; a tool tip appears.) Rightclick on it; on the pop-up menu, select Edit Type and Values. In the Edit Transmission Line dialog box, click on the Values tab; in the Length box, type 1.2. Then click OK. 4. Repeat step 3 for each of transmission lines TL26 and TL Then restore the oscilloscope; click Erase; and click Start Simulation to re-simulate. Success! We ve made the signal quality on all receivers on the DDR data bus clean enough to work reliably. About Modeling ICs An important aspect of simulation is the modeling of ICs, particularly driver ICs. So far, we have not addressed this topic in any detail. If you continue through this demonstration, you'll learn more about IC modeling. If modeling is of particular concern to you, click here to jump ahead to some information specifically about IC modeling. Click here to continue with the front-to-back HyperLynx demonstration; next, we turn our attention to pre-layout crosstalk analysis and simulation of differential pairs. Click here to return to the main menu. mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/pre_layout_analysis_li...

11 LineSim's Crosstalk and Differential-Signal Features 页码,1/7 LineSim's Crosstalk and Differential-Signal Features If you started this demonstration at the beginning, you've already seen how LineSim's signal-integrity and EMC analysis features can help you prevent signal-integrity and EMC problems early in the design cycle. LineSim's crosstalk-analysis features extend the advantages of working up-front to two further high-speed areas: crosstalk and differential signaling. In this section, we'll see some examples of each. How LineSim's Crosstalk Analysis Works As demonstrated in the overview of LineSim's "base" features, LineSim allows you to quickly construct schematics of various interconnect scenarios, and simulate to see the resulting waveforms. LineSim's crosstalk-analysis option lets you go a step further and add line-to-line coupling into your schematics. With this capability, you can: accurately predict how much crosstalk will occur when two or more PCB traces are routed near each other efficiently specify maximum parallelism, minimum line separation, and other routing constraints see the effects on crosstalk waveforms of trace separation; trace width; dielectric thickness; driver-ic edge rate and impedance; parallel run length; and so forth confidently design high-speed buses that meet tight timing and low-crosstalk-noise requirements learn the difference between forward and backward crosstalk, and develop an intuitive sense of when crosstalk occurs and how to minimize it implement resistor-termination strategies that can greatly reduce or eliminate end-of-the-line crosstalk A key technical element of LineSim's ability to analyze coupled transmission lines is its fast, built-in boundaryelement field solver. In one of the examples below, you'll have the opportunity to explore a few of the solver's features in detail. Using LineSim for Differential-Signal Analysis LineSim's coupled-line analysis features are also valuable in the design of differential signals, since the same line-to-line coupling that causes crosstalk on unrelated signals also creates differential impedance and other electrical characteristics important in differential signaling. Differential pairs are common in very-high-speed design, and are used widely in gigabit-per-second, SERDES-based designs. Specifically, you can use LineSim to: Accurately simulate differential signals, taking full account of the coupling between traces Explore termination options for differential signals, and determine when a single line-to-line resistor is sufficient or when a full "array" termination is required LineSim also offers features that make it easy to plan for targeted differential impedance. This happens mostly in the stackup editor; to see an example of differential-z0 planning, click here. In the following sections, we'll look at some examples of how LineSim's crosstalk-analysis option can make preventing crosstalk and designing differential signals easier. Crosstalk Example: Planning Minimum Trace Separation on a Bus Suppose you're designing a bus, and you want to guarantee that no more than 300 mv of crosstalk can occur between any of the bus' signals. Let's see how LineSim's crosstalk option could help you meet this design goal, and develop the proper routing constraints to achieve it. How to Simulate Crosstalk on a Bus A typical parallel-style bus in a digital system contains many physically parallel traces 16, 32, 64, maybe even more signals. (This is not true of gigabit-per-second, SERDES-based designs, which emphasize serial links, but here we're talking about traditional synchronous-style designs.) However, when you simulate to predict crosstalk on such a bus, you definitely would not bother simulating all of the signals. Rather, you would take advantage of the fact that the crosstalk driven into a given "victim" trace comes predominantly from two other traces: the neighboring ones on either side. So, typically, you would bother to simulate only a set of

12 LineSim's Crosstalk and Differential-Signal Features 页码,2/7 three traces (or maybe five), as shown in this example. Load the Demo Schematic "XT_Trace_Separation.ffs" In this demonstration, you can only simulate the schematics supplied with the demo (you can't create your own). Let's begin by loading a schematic representing three adjacent traces on a bus. Load the demo schematic "XT_Trace_Separation.ffs" using File > Open LineSim Schematic: 1. On LineSim's File menu, select Open LineSim Schematic. A dialog box opens. 2. Double-click on the file name "XT_Trace_Separation.ffs". The dialog box closes and a schematic appears in LineSim's free-form editor. In the schematic, the three transmission lines represent the side-by-side traces on the bus described above. The triangular IC-driver symbols at the left end of each line show that all three traces are being driven from the left side. Each line also has a receiver IC at its right end. The ICs are modeled with a generic 3.3-V fast CMOS model from the HyperLynx-supplied library EASY.MOD. "Victim" versus "Aggressor" Traces Look at how the driver ICs are set up in the Assign Models dialog box; note that the middle trace's driver is set to "Stuck Low" rather than "Output": 1. Point to any of the left-end driver-ic symbols in the schematic. Double-click on the symbol; the Assign Models dialog box opens. 2. In the Pins list, highlight IC pin U1.1 by clicking once on it. Look in the Buffer Settings area to the right and note that this pin (the driver IC on the uppermost trace) has been set to be an "Output," meaning that it will switch high/low or low/high when simulation runs. 3. Similarly, in the Pins list box, highlight pin U1.3 (third in the list). It is also set as an "Output." 4. Now highlight pin U1.2. This is the driver on the middle trace. Notice in the Buffer Settings area that it has been set to "Stuck Low." This means that it will NOT switch when simulation is run. 5. Click OK to close the dialog box. Back in the schematic editor, note that middle-trace driver has a "0" near its symbol, indicating visually that it is "stuck low." The reason that the driver ICs are set up this way (middle trace "stuck low" and outer traces switching) is that we want the middle signal to be the "victim" in our analysis and the outer signals the "aggressors," i.e., we want to see how much crosstalk develops on the middle trace when its neighboring traces switch. But notice that we didn't leave the middle trace completely undriven; rather, we applied a driver-ic model, but held it in a static state. Modeling driver ICs on victim traces is very important, since low-impedance drivers reflect rather than absorb crosstalk energy. About "victims" and "aggressors": LineSim will simulate any mixture of "victim" and "aggressor" traces - in fact, the simulator makes no distinction between the two. Generally, you would refer to traces which are actively switching as "aggressors" and those on which you're trying to observe the resulting crosstalk as "victims." In this simulation, we could just as well have made the middle trace also switch, in which case it would have been both an aggressor to the other traces AND their victim. How the Traces' Coupling was Defined LineSim's crosstalk option lets you add coupling information to any LineSim schematic. (For more information on LineSim's basic, non-crosstalk features, click here.) The drawing for this example was created by entering a LineSim schematic with three transmission lines and their driver and receiver ICs; then adding information about how the three lines are coupled together. Any line in a schematic can be made coupled simply by rightclicking on it and changing its type to "coupled stackup" (not in the demonstration version, though). Any number of "coupling regions" can be defined, and any line can be added into any coupling region. When a transmission line is coupled, it displays differently in the schematic editor than when uncoupled. Notice that the t-lines in this schematic have rat s nest lines between them, indicating that they re coupled together. Once transmission lines are gathered into a coupling region, the region's cross-section properties and length can be defined to match exactly the problem you want to simulate. The definition you make is geometric; it is LineSim's job to convert this data into electromagnetic parameters. Right-click on a transmission line to edit it and click the Edit Coupling Regions tab; look at how a region's mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/linesim_s_crosstalk_an...

13 LineSim's Crosstalk and Differential-Signal Features 页码,3/7 cross section is defined geometrically: 1. Point to any of the transmission lines in the schematic, and right-click with the mouse. A menu appears. 2. Select Edit Type and Values. The Edit Transmission Line dialog box opens. 3. Click on the Edit Coupling Regions tab. 4. Notice how the dialog box allows you to completely define the coupling region's geometry. The Coupling Regions list box (on the left) shows a "tree list" of the region's stackup layers and transmission lines, and a graphical view of the current definition. The various edit boxes on the right let you change geometric parameters for the currently highlighted trace (or in some cases, globally for the entire region). The Impedance list box (lower right) gives a summary of the resulting electrical characteristics (much more electrical data is available elsewhere; see below). This coupling region is currently defined as follows: traces are together on an inner, "stripline" layer traces are 6 mils wide and 8 mils apart (edge-to-edge) the region's cross section applies over a length of 12 inches Before we actually make any changes to the coupling region, let's run a simulation to see how much crosstalk occurs with the current arrangement. (Perhaps our design goal of no more than 300 mv of crosstalk voltage is already satisfied.) Run a Simulation with Existing Coupling to See How Much Crosstalk Occurs Simulate the existing schematic and coupling region using Simulate > Run Interactive Simulation; set the oscilloscope timebase to 2 nsec/div, and simulate once with a falling edge and once with rising: 1. Click OK to close the Edit Coupling Regions dialog box. 2. On the Simulate menu, select Run Interactive Simulation. The Digital Oscilloscope dialog box opens. 3. Verify that the Driver Waveform is set to Edge, Falling Edge, and the IC Modeling to Typical. 4. In the Horizontal Scale area, click the up arrow button once to change the timebase to 2 nsec/div. 5. Click the Start Simulation button. 6. When the simulation is complete, change the Driver Waveform to Rising Edge, and re-simulate. The green and yellow waveforms show the crosstalk voltages on the middle, "victim" trace, at the receiver and driver ends, respectively. That the yellow waveform hardly moves is no surprise, since this end of the line is held low by a low-impedance CMOS driver. But the situation is very different at the green, receiver end: there is more than 1V of crosstalk when the aggressor signals are driving high. (To see which waveforms correspond to which driver edge, in the Display area, toggle the Previous Results check box on and off; the waveform that persists is for the rising-edge simulation.) >1V is well above our design criterion of 300 mv maximum crosstalk. When we simulated, LineSim ran its built-in boundary-element field solver to convert all of the geometric data we entered into electromagnetic coupling parameters. In this example, we won't look specifically at the results generated by the field solver (though they are always available in the Edit Transmission Line dialog box's Field Solver tab, by clicking the View button). Later, in a differential-pair example, we'll look at the solver's output in detail. Note: It is the backward-crosstalk pulse reflecting off the victim line's driver IC that generates the 1-V problem. With a little experience using LineSim, you will be able to comfortably distinguish forward crosstalk from backward. Backward crosstalk persists for twice the delay length of the aggressor net that creates it (compare the length in time of the pulses in the green waveform to the transmission-line delay reported in the schematic). Increase the Trace Separation to Decrease the Crosstalk One obvious way to decrease the crosstalk is to increase the separation between the traces. Edit the coupling region, increase the trace separation from 8 mils to 12, and re-simulate to see by how much the crosstalk is reduced: mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/linesim_s_crosstalk_an...

14 LineSim's Crosstalk and Differential-Signal Features 页码,4/7 1. Point to any of the transmission lines in the schematic (you don't need to close the oscilloscope first), and right-click with the mouse and select Edit Type and Values to re-open the Edit Transmission Line dialog box. 2. Click on the Edit Coupling Regions tab. 3. In the Coupling Regions list box, highlight the middle trace. There are two ways to do this: either click once on transmission line "TL2" in the tree list; or carefully point to the middle trace in the graphical viewer, and click. 4. In the Trace-to-Trace Separation area, in both the Left and Right edit boxes, type "12" to increase the separation from the aggressor traces. The separations become wider in the graphical viewer. 5. Click OK to close the dialog box, then back in the oscilloscope, click the Start Simulation button. Notice that the maximum crosstalk (green waveform) has indeed been reduced, but only to about 750 mv, still well above the acceptable level. Decrease the Stackup Dielectric Thickness There are many ways besides trace separation to affect crosstalk. One that is sometimes overlooked is the PCB stackup. Let's try making a simple stackup change to further decrease the amount of crosstalk on our bus. Edit the PCB stackup and decrease the separation between the plane layers and the inner signal layers from 10 mils to 5; then re-simulate: 1. On the Edit menu, select Stackup. The stackup editor opens. 2. Verify that the Basic tab is selected. 3. In the Thickness cell for the dielectric between layers "VCC" and "Inner1" (i.e., row 5 of the spreadsheet), type "5". Press <Enter> or click some other cell in the spreadsheet to tell the stackup editor to accept the new value. 4. Repeat for the dielectric layer between layers "Inner2" and "GND" (row 9); type "5". 5. Verify in the graphical stackup viewer that the desired layers display as 5 mils thick. Then click OK to close the editor. 6. Back in the oscilloscope, click the Start Simulation button. Now the maximum crosstalk at the victim trace's receiver end (green waveform) is sharply reduced, to about 280 mv. This meets our design goal, with a little margin to spare. In general, crosstalk is a complex effect that is influenced by many different factors: e.g., driver-ic technology, trace separation, trace width, line length, line-end termination (crosstalk generally requires more-complex termination than single-line reflections), and PCB stackup (layer ordering and dielectric thickness/material). LineSim lets you rapidly explore many different options to see which combinations most effectively meet your requirements. One of the most powerful uses for LineSim is the development of routing guidelines and constraints. For example, in this case, we now know that the routing for this bus must be set to a minimum trace separation of 12 mils. We also have a stackup constraint: we know that two of our dielectrics need to be 5 mils thick. Differential-Trace Example Differential signaling is a technology that actually takes advantage of the coupling between neighboring traces. When you design a differential pair, you often deliberately couple the two traces together fairly strongly, so that any signal induced by external noise on one is also induced on the other and then rejected by the differential receiver at the ends of the lines. However, differential-pair design involves non-trivial issues like determining what geometries to pick to achieve a specific differential impedance. Terminating differential traces can also sometimes be challenging. LineSim's crosstalk option is a powerful tool for differential-signal applications, because of the built-in boundary-element field solver. The field solver automatically calculates differential impedances, determines coupling parameters, and suggests termination values. Achieving a Specific Differential Impedance It's common in differential signaling for IC vendors or bus specifications to recommend specific differential- mk:@msitstore:d:\hyperlynx75\demo.chm::/demo/linesim_s_crosstalk_an...