Crosstalk, Part 2 Simulating Crosstalk Effects

Size: px
Start display at page:

Download "Crosstalk, Part 2 Simulating Crosstalk Effects"

Transcription

1 TECHNICAL PUBLICATION Crosstalk, Part 2 Simulating Crosstalk Effects Douglas Brooks, President UltraCAD Design, Inc. April

2 ABSTRACT It is known that forward crosstalk increases (for all practical purposes) with increasing coupled length, but has a pulse width that is constant. Backwards crosstalk, on the other hand, rises quickly (within the critical region) to a constant maximum, but has a pulse width that increases with increasing coupled length. Simulations using HyperLynx LineSim show this very effectively and clearly. The tool can illustrate how impedance loading of the victim trace can impact the magnitude, and even the polarity, of the backward crosstalk pulse. HyperLynx also can be used to clearly illustrate how the backward crosstalk pulse is twice the propagation time through the coupled region plus one rise time, how the crosstalk signal is impacted by the relationship between the traces and their reference planes and also with each other, and how an aggressor AC signal's period can interact with the length of the coupled region to create some surprising crosstalk effects. BASIC MODEL To simulate basic crosstalk concepts without any spurious effects getting in the way, we will structure a fairly specific, simple model. This model will be designed with the intent of excluding all spurious effects except those caused by crosstalk between the traces themselves. The stripline portion of the model is shown in Figure 1. INTRODUCTION In a previous article 1 I talked about the nature of crosstalk, especially forward vs backward crosstalk and how forward crosstalk is virtually zero in a stripline environment. This article will introduce several HyperLynx simulations illustrating various characteristics of crosstalk. The reader will gain an understanding of (a) how to use HyperLynx LineSim to simulate crosstalk, and (b) how to recognize various crosstalk effects. We will illustrate a variety of simulations: Basic crosstalk concepts Difference between microstrip and stripline crosstalk effects The effect of trace terminations on crosstalk Crosstalk sensitivity to trace height and separation What happens when there is coupling over only part of the trace length Another topic, crosstalk coupling when we tune traces with closely coupled "serpentine" traces, has been covered in a separate article. 2 Figure 1 - Basic HyperLynx LinSim model for simulation. The stackup for this model is shown in Figure 2. In HyperLynx, the stackup is created or edited by the menu selection Edit/Stackup. In this paper we are going to be using the layers labeled "Top" (microstrip) and "Stripline" (Signal layer 4). The stripline stackup values have been carefully created to achieve a propagation speed of almost exactly 6"/ns for ease in understanding the results. Figure 2 - HyperLynx Stackup Editor. PAGE 1

3 If you right-click one of the transmission line segments the "Edit Transmission Line" window displays (Figure 3a). The most significant entry here is that the "Coupled Stackup" radio button has been selected. The "Edit Coupling Regions" tab (Figure 3b) reveals the name and the layer of the coupling region. But more importantly, there are places to edit the length and width of the trace and the separation from the adjacent (coupled) trace. This illustration shows a length of 12 inches, a trace width of eight mils, and a separation of only five mils. We can expect the crosstalk to be fairly significant for two traces ten mils away from their reference plane (Figure 2) and only five mils apart (Figure 3b) ohms, to properly terminate the transmission lines. The near resistor on the victim line has been set to ten M ohms to simulate an open circuit or a high impedance pin on a device. Thus, the backward crosstalk signal on the victim line will reflect off this point (with a 100% reflection coefficient 3 ) and travel back toward the far end of the victim line. Figures 3a and 3b - Transmission Line Edit windows. We need terminating resistors for the traces. If you select a resistor "holder" and then right-click it, the Edit Resistor Values window displays (Figures 4a and b). We have set the values of the two far end resistors to Figures 4a and 4b - Setting terminating resistor values (top) and parasitics (bottom). HyperLynx allows you to set parasitic values for the passive devices (Figure 4b). This can be useful or desirable if you want to try to precisely simulate how a circuit will work with "real world" devices. For this theoretical basic model, I have set all the parasitic values to the minimum allowed by Hyperlynx. This is so we can look as closely as possible to the crosstalk effects, isolated from any other effects that might distort the results. PAGE 2

4 Finally, we need a driver to drive the aggressor trace. That is identified in Figure 1 as "Ramp2nsec." Because there are some things I specifically want to identify from the basic results, I have created a driver with some very special characteristics. This driver rises almost perfectly linearly from zero to full value in two ns. That compares with a typical device that would have normal "roll-on" and "roll-off" characteristics. The purpose for this will become clear later. But the driving signal in this model is either constant or it is linear at 50%/ns. There is virtually no roll-on or roll-off. To create a driver like this, start by Selecting Edit/Databook IC Models (.Mod). Figure 5a shows the Edit.MOD Model for the Device Model TDR in the GENERIC MOD Library. Figure 5b shows how I edited this model, and then saved it as Ramp2nsec in the USER.mod library for my use. The edited model is the driver we are going to use in this simulation. Figure 6 - Result from the basic simulation. INITIAL RESULTS Running the simulation (Simulate/Run Scope..) leads to the results shown in Figure 6. The red trace (a) in Figure 6 is the driver. Note how it rises from zero to full value (about 4.4 Volts) in almost exactly two ns. The green trace (b) is the driven signal showing up at the far end of the driven trace two ns later (the trace is 12 inches, or two ns long.) The blue trace (c) is the backward crosstalk signal arriving at, and reflecting from, the ten Mohm resistor at the front of the victim trace. In this example, the magnitude of the signal here is approximately 1.2 Volts. 4 The orange trace (d) is this reflected signal showing up at the far end of the victim trace, two ns later. Its magnitude is about.6 V. The near end backward crosstalk pulse is actually.6 V, too, but it shows up in the model as twice that value because of the 100% positive reflection at the end of the (effectively) unterminated transmission line. It is instructive to look at pulse widths and shapes here. And now it begins to come clear why we structured such a special driver. The crosstalk signal has the same rise time as the driver does (two ns). And since there is no perceptible roll-on or roll-off, it is very clear where these signals start and finish. Figure 5a and 5b - Device model windows. Figure 5a (top) shows a standard GENERIC MOD model for a TDR. Figure 5b (bottom) shows how this model was edited to create Ramp2nsec device model used in the simulation. In the article referenced in Footnote 1, I pointed out that the backward pulse width is twice as wide as the propagation time through the coupled region. That is approximately true if you measure it from the midpoint of the rise and fall times. What is precisely true (and can be seen in this special case) is that the backward pulse width is twice the propagation time through the coupled region PLUS one rise time! Note that the rise time of the driving pulse is exactly two ns. The PAGE 3

5 coupled region is two ns long; twice that is four ns. The backward crosstalk pulse in Figure 6 is six ns from start to finish-twice the coupled region (4) plus one rise time (2). The reason is this. As the very first part of the driven signal enters the coupled region, the backward crosstalk signal begins to form. As the very first part of the driven signal arrives at the far end of the coupled region, it generates a backward pulse component that is twice the coupled region behind the first. It is the length of the coupled region later, and it is the length of the coupled region further away from the beginning. These combine to double the coupled region width. But that only concerns the very first part of the driver signal (the beginning of the rise time). The last part of the driven signal (the top of the rise time) also contributes to the backward crosstalk pulse. It is one rise time later than the first part of the driven signal. Altogether, these factors combine to a backward pulse that is twice as wide as the coupled region plus one rise time. critical length the backward pulse width is a triangle. If the coupled region is shorter than the critical length, the width follows the same rule as before, but the crosstalk signal does not have time to rise to its maximum value. This, then, illustrates the fundamental rule: The backward pulse increases in amplitude with the length of the coupled region until the critical length, then it rises no further. The pulse width is twice the coupled region plus one rise time. TERMINATIONS COUPLED LENGTH Figure 7 illustrates what happens as we change the coupled length. The driver is as before. The longest backward crosstalk pulse is the same as in Figure 6. Two other pulses are shown: one each for a six inch coupled region (one ns) and a three inch coupled region (.5 ns). Each of these backward pulses has a width of twice the coupled region plus one rise time. When the coupled region is the "critical length," 5 i.e. one-half the rise time, the signal just has time to rise to its maximum value and then decay again. So at the Figure 7 - Simulation results for three coupled lengths, 3" (a), 6" (b), and 12" (c). Figures 8a (top) and 8b (bottom) - The impedance at the near-end of the victim trace can have a dramatic effect on the magnitude, and even the polarity, of the backward crosstalk pulse. It is interesting to see what happens as we vary the terminating resistor at the front (near end) of the victim line. If the victim trace is terminated in its characteristic impedance at the near end, the backward crosstalk pulse travels back to it (Figure 8a) but then is completely dissipated at that point. There is no forward reflection. If, on the other hand, the trace is shorted at the near end, Figure 8b, then there is a PAGE 4

6 100% negative reflection of the backward pulse. Note that the pulse at the far end of the victim trace in Figure 8b is exactly the same shape and amplitude as the pulse in Figure 6, but opposite in sign. (There is no signal at the near end of the victim trace in Figure 8b, of course, because the trace is shorted at that point!) Clearly, the magnitude (and even the polarity) of the crosstalk signal depends on the termination at the near end of the victim line. Any devices that exist on that portion of the line (including another device driver at the beginning of the victim line) contribute to that loading. And those devices may present different loading characteristics depending on their state (i.e. "on" or "off" or "high" or "low"). This makes estimating and troubleshooting crosstalk issues that much tougher. SEPARATION AND HEIGHT ABOVE PLANE The two primary ways to reduce crosstalk are well known: 6 route traces close to their reference plane, and spread the traces further apart. Figure 9 simulates each of these effects. If the trace separation increases from five mils to ten mils, the magnitude of the backward crosstalk signal reduces as shown in Figure 9a. If the reference plane is brought closer to the traces (from ten mils to five mils) the magnitude also reduces, as shown in Figure 9b. It should be noted that when the trace is placed closer to the reference plane, the characteristic impedance drops. Therefore, the terminating resistors were adjusted accordingly. MORE TYPICAL DRIVER Figure 9a and 9b - The magnitude of the crosstalk pulse decreases with increasing separation, Figure 9a (top), and with decreasing height above the underlying plane, Figure 9b (bottom). All the simulations so far have been with the special ramp driver described in Figure 5b. There are some slight changes when we do the simulation using a more typical high-speed device model. Figure 10 illustrates the model with a driver selected from the EASY.MOD library, the CMOS 3.3V ULTRAfast device. Figure 11 illustrates the results of this model for the same stripline trace configuration used in Figure 6. As is apparent, the results are very similar. It gets more interesting when we do this simulation on the microstrip (top) layer (Figure 12). The stackup is as shown in Figure 2. The trace impedance has changed because the geometry is now Figure 10 - Stripline simulation with a more conventional driver model. PAGE 5

7 backward direction. Thus, there is a well-defined backward crosstalk signal but no forward crosstalk signal. But in a microstrip environment, the two forward components do not perfectly cancel. Thus there is a net forward crosstalk signal that can appear in microstrip environments that almost never occurs in stripline environments. IMPACT OF COUPLED LENGTH Figure 11 - Simulation result of the stripline model of Figure 10. microstrip instead of stripline, and the terminating resistors have therefore been adjusted. Similarly, the propagation speed has changed. 7 The simulation result is as shown in Figure 13. The simulation is similar to that in Figure 11 except for the sharp negative-going pulse at the far end of the victim trace. This is the forward crosstalk pulse. Recall from the article referenced in Footnote 1, there are two coupling effects that take place in a crosstalk situation, capacitive and inductive. Capacitive coupling sends signal components in both directions in the victim trace, but inductive coupling only sends a signal component in the backward direction. In a stripline environment, the two components almost perfectly cancel in the forward direction, but reinforce each other in the Figure 12 - Microstrip model with a more typical driver model. Figure 13 - Simulation result of the model in Figure 12. The article referenced in Footnote 1 also points out that the backward crosstalk signal is relatively constant in magnitude and has a pulse width twice as wide as the propagation time down the coupled region, but the forward crosstalk signal has an amplitude that continually increases as the coupled region increases and has a fixed pulse width equal to the rise time (or the fall time) of the aggressor signal. 8 This result is illustrated in Figure 14, where three simulations are shown. The simulations are identical except for the length of the coupled region (six, 12 and 24 inches respectively.) Although forward crosstalk is rarely a problem in typical PCB designs (because the coupled length is PAGE 6

8 Figure 14 - Simulation results when the coupled length is varied from 6 to 12 to 24 inches. rarely long enough to generate a significant signal), many designers follow the rule that if crosstalk is a performance issue or concern, all crosstalk sensitive traces will be routed in a stripline environment. This should be considered a conservative rule. Many designers have no particular crosstalk problems when routing in either environment. OSCILLATING (AC) DRIVER Up to now we have looked at simulations with a single pulse driven down the trace. Some surprising things can happen if we look at the more typical case of a clock signal driven down the trace. Consider the model shown in Figure 10 with the trace length adjusted to six inches (one ns). Let's drive this model with three different square wave frequencies, 300 MHz, 500 MHz, and 700 MHz, respectively. The results are shown in Figures 15a, 15b, and 15c, respectively. It is striking that there is no apparent crosstalk signal when the clock rate is 500 MHz. That does not mean that there is no crosstalk! The clock half-cycle is one ns. At time equal one ns there is a clock transition going in one direction. One ns later there is a clock transition going in the other direction. One ns later..., etc. The time of these transitions happens to coincide exactly with the trace length (one ns). Thus, the crosstalk components caused by each transition are canceling out. Imagine the difficulty of troubleshooting a crosstalk problem when varying frequencies are involved! Figures 15a, 15b, and 15c - Crosstalk effects can be an unexpected function of frequency. Here are the results from the same model driven by an aggressor signal of 300 MHz (a, top), 500 MHz (b, middle), and 700 MHz (c, bottom). The larger waveform is the driver. The smaller one is the resulting crosstalk signal. PAGE 7

9 COUPLED OVER PARTIAL LENGTH As a final simulation illustration, consider the case of two traces which are coupled over only part of their length. Figure 16 illustrates such a model. These are simulated as microstrip traces to incorporate the added complexity of a forward crosstalk pulse. The entire propagation delay is nine inches (1,281.4 ns) ns along the aggressor trace and 16 inches (2,287.3 ns) along the victim trace. The result of this simulation is shown in Figure 17. Note in particular that the forward and backward crosstalk signals arrive at the far end of the victim trace at significantly different times. If you were an engineer and saw these traces on a scope for a signal trace and for a (supposedly) quiet adjacent trace, it would not be readily intuitive that these signals were related! That is one of the difficulties in troubleshooting crosstalk problems if you are not familiar with what they look like or if you are not sensitive to the possibility that they could even exist. SUMMARY Figure 16 - Simulation of a condition where the traces are coupled over only a portion of their length. HyperLynx LineSim is a very effective tool for simulating crosstalk. It is equally effective for simulating actual circuits and for simulating hypothetical situations to see what the effects might look like. Crosstalk effects are quite similar in microstrip and in stripline environments, except forward crosstalk can become an issue in the former. Simulations can illustrate quite clearly the fundamental rule that forward crosstalk grows continuously (for all practical purposes) with increasing coupled length, but its pulse width remains constant. Backward crosstalk, on the other hand, rises quickly (within the critical region) to a constant maximum amplitude, but has a pulse width that increases with increasing coupled length. The maximum amplitude, and even its polarity, can be a function of impedance loading at the front (near end) of the victim trace. Using a controlled driver waveform, it is easy to show that the backward crosstalk pulse width is twice the propagation time through the coupled region plus one rise time. Finally, for AC waveforms, there can be an interaction between the period of the waveform and the FOOTNOTES propagation time through the coupled region that can have a very significant effect on the resulting crosstalk signal. 1. "Crosstalk, Part 1; Understanding Forward vs Backward," available at 2. "Adjusting Signal Timing, Part 2; Crosstalk Effects in Serpentine Traces," available at 3. Information on reflection coefficients can be found in a great many sources. See for example, "Transmission Line Terminations; It's the End that Counts," available at Figure 17 - Simulation result of the model in Figure 16. PAGE 8

10 4. This crosstalk signal is quite high because we have structured an example with very strong coupling (traces relatively far from their reference plane and close to each other), and because there is a 100% reflection here at the effectively unterminated end of the transmission line. 5. This is the same critical length we talk about with transmission lines. There are many, many articles on this topic. See, for example, "Propagation Times and Critical Length; How They Interrelate," available at 6. Brooks, Douglas, Signal Integrity Issues and Printed Circuit Board Design, Prentice Hall, 2003, Chapter "Microstrip Propagation Times; Slower than We Think," available at 8. Same as Footnote 1. to those without a technical background. You can visit his web page at and him at doug@ultracad.net. ABOUT THE AUTHOR Douglas Brooks has a B.S and an M.S in Electrical Engineering from Stanford University and a PhD from the University of Washington. During his career has held positions in engineering, marketing, and general management with such companies as Hughes Aircraft, Texas Instruments and ELDEC. Brooks has owned his own manufacturing company and he formed UltraCAD Design Inc. in UltraCAD is a service bureau in Bellevue, WA, that specializes in large, complex, high density, high speed designs, primarily in the video and data processing industries. Brooks has written numerous articles through the years, including articles and a column for Printed Circuit Design magazine, and has been a frequent seminar leader at PCB Design Conferences. His primary objective in his speaking and writing has been to make complex issues easily understandable For more information, call us or visit: Copyright 2004 Mentor Graphics Corporation. This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposed only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use of this information. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. All other trademarks are the property of their respective owners. Corporate Headquarters Mentor Graphics Corporation 8005 S.W. Boeckman Road Wilsonville, Oregon USA Phone: Silicon Valley Headquarters Mentor Graphics Corporation 1001 Ridder Park Drive San Jose, California USA Phone: Fax: Europe Headquarters Mentor Graphics Corporation Deutschland GmbH Arnulfstrasse Munich Germany Phone: Fax: Pacific Rim Headquarters Mentor Graphics (Taiwan) Room 1603, 16F, International Trade Building No. 333, Section 1, Keelung Road Taipei, Taiwan, ROC Phone: Fax: Japan Headquarters Mentor Graphics Japan Co., Ltd. Gotenyama Hills 7-35, Kita-Shinagawa 4-chome Shinagawa-Ku, Tokyo 140 Japan Phone: Fax: JC Printed on Recycled Paper TECH6300-w PAGE 9

MEMORY TEST AND REPAIR SOLUTION FOR ARM PROCESSOR CORES STEVE PATERAS JANUARY 2011

MEMORY TEST AND REPAIR SOLUTION FOR ARM PROCESSOR CORES STEVE PATERAS JANUARY 2011 MEMORY TEST AND REPAIR SOLUTION FOR ARM PROCESSOR CORES STEVE PATERAS JANUARY 2011 S I L I C O N T E S T A N D Y I E L D A N A L Y S I S W H I T E P A P E R w w w. m e n t o r. c o m Many large systems-on-chip

More information

Taking Advantage of SystemVerilog for Design with ModelSim

Taking Advantage of SystemVerilog for Design with ModelSim D IGITAL S IMULATION A PPLICATION N OTE Taking Advantage of SystemVerilog for Design with ModelSim www.model.com Introduction SystemVerilog (SV) is the next generation of the popular Verilog language.

More information

DESIGNING MULTI-FPGA PROTOTYPES THAT ACT LIKE ASICS

DESIGNING MULTI-FPGA PROTOTYPES THAT ACT LIKE ASICS Design Creation & Synthesis White Paper DESIGNING MULTI-FPGA PROTOTYPES THAT ACT LIKE ASICS May 2009 ABSTRACT FPGA prototyping has become indispensable for functional verification and early software integration

More information

Copyright 2011 by Dr. Andrew David Norte. All Rights Reserved.

Copyright 2011 by Dr. Andrew David Norte. All Rights Reserved. Near-End Crosstalk Considerations For Coupled Microstriplines David Norte, PhD www.the-signal-and-power-integrity-institute.com Thornton, Colorado, 80234, USA Abstract This paper addresses the impact of

More information

CHAPTER 2 NEAR-END CROSSTALK AND FAR-END CROSSTALK

CHAPTER 2 NEAR-END CROSSTALK AND FAR-END CROSSTALK 24 CHAPTER 2 NEAR-END CROSSTALK AND FAR-END CROSSTALK 2.1 INTRODUCTION The high speed digital signal propagates along the transmission lines in the form of transverse electromagnetic (TEM) waves at very

More information

THREE THINGS TO CONSIDER WHEN DESIGNING ELECTRONIC PRODUCTS WITH HIGH-SPEED CONSTRAINTS BY: PATRICK CARRIER, MENTOR GRAPHICS CORP.

THREE THINGS TO CONSIDER WHEN DESIGNING ELECTRONIC PRODUCTS WITH HIGH-SPEED CONSTRAINTS BY: PATRICK CARRIER, MENTOR GRAPHICS CORP. THREE THINGS TO CONSIDER WHEN DESIGNING ELECTRONIC PRODUCTS WITH HIGH-SPEED CONSTRAINTS BY: PATRICK CARRIER, MENTOR GRAPHICS CORP. P A D S W H I T E P A P E R w w w. p a d s. c o m INTRODUCTION Designing

More information

TDR/TDT Analysis by Crosstalk in Single and Differential Meander Delay Lines for High Speed PCB Applications

TDR/TDT Analysis by Crosstalk in Single and Differential Meander Delay Lines for High Speed PCB Applications TDR/TDT Analysis by Crosstalk in Single and Differential Meander Delay Lines for High Speed PCB Applications Gawon Kim, Dong Gun Kam, and Joungho Kim Dept. of EECS, KAIST Korea Advanced Institute of Science

More information

UltraCAD Design Inc.

UltraCAD Design Inc. UltraCAD Design Inc. Differential Impedance Transmission Line Calculator UCCALC.exe Help File and Operator s Manual Version 3.5 Welcome Thank you for using UltraCAD's Differential Impedance Calculator.

More information

FPGA ADVANTAGE FOR HDL DESIGN

FPGA ADVANTAGE FOR HDL DESIGN FPGA ADVANTAGE FOR HDL DESIGN A STREAMLINED S OLUTION FOR FPGA DESIGN The FPGA Advantage Design Solution gives you smooth data transition from one step of your design process to the next. All steps are

More information

ECE 497 JS Lecture - 21 Noise in Digital Circuits

ECE 497 JS Lecture - 21 Noise in Digital Circuits ECE 497 JS Lecture - 21 Noise in Digital Circuits Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements - NL05 program available -

More information

HyperLynx 教程. Pre-layout (LineSim):

HyperLynx 教程. Pre-layout (LineSim): HyperLynx 教程 Pre-layout (LineSim): Signal-integrity and EMC analysis Crosstalk and differential-signal analysis Analysis for gigabit-per-second, SERDES-based designs Stackup and impedance planning Post-layout

More information

Constraint Manager for xpcb Layout. Table of Contents

Constraint Manager for xpcb Layout. Table of Contents Table of Contents 2014 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject

More information

AN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY

AN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY AN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY BY STEVE KAUFER, MENTOR H I G H S P E E D D E S I G N W H I T E P A P E R OVERVIEW Digital designers are now required to make the leap from time domain to

More information

EMC ISSUES OF WIDE PCB BUSES

EMC ISSUES OF WIDE PCB BUSES EMC ISSUES OF WIDE PCB BUSES Bertalan Eged István Novák Péter Bajor Technical University of Budapest, Department of Microwave Telecommunications A device under test with 17 coupled microstrip traces was

More information

Revolutionary High Performance Interconnect Which Maximizes Signal Density

Revolutionary High Performance Interconnect Which Maximizes Signal Density Revolutionary High Performance Interconnect Which Maximizes Signal Density Tom Cohen and Gautam Patel Teradyne Connection Systems 44 Simon St. Nashua, New Hampshire 03060 Phone: 603-791-3383, 603-791-3164

More information

Tsi384 Board Design Guidelines

Tsi384 Board Design Guidelines Tsi384 Board Design Guidelines September 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 (408) 284-8200 FAX: (408) 284-2775 Printed in U.S.A. 2009, Inc. GENERAL

More information

2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Description. Features. Block Diagram DATASHEET

2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Description. Features. Block Diagram DATASHEET DATASHEET 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) or LVDS input pairs

More information

Mobile Pentium II TM System Clock Chip ICS DATASHEET

Mobile Pentium II TM System Clock Chip ICS DATASHEET DATASHEET ICS9248-92 Recommended Application: The ICS9248-92 is a fully compliant timing solution for the Intel mobile 440BX/MX chipset requirements. General Description: Features include two strong CPU,

More information

EDA365. DesignCon Impact of Backplane Connector Pin Field on Trace Impedance and Vertical Field Crosstalk

EDA365. DesignCon Impact of Backplane Connector Pin Field on Trace Impedance and Vertical Field Crosstalk DesignCon 2007 Impact of Backplane Connector Pin Field on Trace Impedance and Vertical Field Crosstalk Ravi Kollipara, Rambus, Inc. ravik@rambus.com, (650) 947-5298 Ben Chia, Rambus, Inc. Dan Oh, Rambus,

More information

A novel method to reduce differential crosstalk in a highspeed

A novel method to reduce differential crosstalk in a highspeed DesignCon 5 A novel method to reduce differential crosstalk in a highspeed channel Kunia Aihara, Hirose Electric kaihara@hirose.com Jeremy Buan, Hirose Electric jbuan@hirose.com Adam Nagao, Hirose Electric

More information

Application Note AN105 A1. PCB Design and Layout Considerations for Adesto Memory Devices. March 8, 2018

Application Note AN105 A1. PCB Design and Layout Considerations for Adesto Memory Devices. March 8, 2018 Application Note AN105 A1 PCB Design and Layout Considerations for Adesto Memory Devices March 8, 2018 Adesto Technologies 2018 3600 Peterson Way Santa Clara CA. 95054 Phone 408 400 0578 www.adestotech.com

More information

2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Features

2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Features DATASHEET 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) input pairs and

More information

CENG 4480 Lecture 11: PCB

CENG 4480 Lecture 11: PCB CENG 4480 Lecture 11: PCB Bei Yu Reference: Chapter 5 of Ground Planes and Layer Stacking High speed digital design by Johnson and Graham 1 Introduction What is a PCB Why we need one? For large scale production/repeatable

More information

SPEED2000 TDR/TDT Simulation Tutorial. Product Version 16.6 December 2012

SPEED2000 TDR/TDT Simulation Tutorial. Product Version 16.6 December 2012 Product Version 16.6 December 2012 2012 Cadence Design Systems, Inc. All rights reserved. Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA. Open SystemC, Open SystemC Initiative,

More information

Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008, ver. 1.1 Introduction LVDS is becoming the most popular differential I/O standard for high-speed transmission

More information

2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features

2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features DATASHEET 2 TO 4 DIFFERENTIAL CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential

More information

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH DOUBLE-WIDTH BUS SWITCH

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH DOUBLE-WIDTH BUS SWITCH QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH DOUBLE-WIDTH BUS SWITCH IDTQS32X2245 FEATURES: Enhanced N channel FET with no inherent diode to Vcc Dual '245 function 25Ω resistor for low noise Low propagation

More information

ICS548A-03 LOW SKEW CLOCK INVERTER AND DIVIDER. Description. Features. Block Diagram DATASHEET

ICS548A-03 LOW SKEW CLOCK INVERTER AND DIVIDER. Description. Features. Block Diagram DATASHEET DATASHEET ICS548A-03 Description The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two.

More information

Tektronix DPO Demo 1 Board Instruction Manual

Tektronix DPO Demo 1 Board Instruction Manual xx ZZZ Tektronix DPO Demo 1 Board Instruction Manual www.tektronix.com *P071253900* 071-2539-00 Copyright Tektronix. All rights reserved. Licensed software products are owned by Tektronix or its subsidiaries

More information

HDMI ESD Protection Without Sacrificing Performance Adding ESD Protection to HDMI, Even at 3.4GHz, Just Became Easier

HDMI ESD Protection Without Sacrificing Performance Adding ESD Protection to HDMI, Even at 3.4GHz, Just Became Easier HDMI ESD Protection Without Sacrificing Performance Adding ESD Protection to HDMI, Even at 3.4GHz, Just Became Easier ABSTRACT WHAT SPEED DOES HDMI OPERATE AT ANYWAY? The newest high-definition multimedia

More information

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH DOUBLE-WIDTH BUS SWITCH

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH DOUBLE-WIDTH BUS SWITCH QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH DOUBLE-WIDTH BUS SWITCH IDTQS32X245 FEATURES: Enhanced N channel FET with no inherent diode to Vcc 5Ω bidirectional switches connect inputs to outputs Dual

More information

Symbol Parameter Min Typ Max VDD_CORE Core power 0.9V 1.0V 1. 1V. VDD33 JTAG/FLASH power 2.97V 3.3V 3.63V

Symbol Parameter Min Typ Max VDD_CORE Core power 0.9V 1.0V 1. 1V. VDD33 JTAG/FLASH power 2.97V 3.3V 3.63V 1 Introduction The user guide provides guidelines on how to help you successfully design the CME-M7 board which includes the power supply, configuration, clock, DDR2 or DDR3, high speed USB, LVDS and ADC

More information

RClamp TM 0504M RailClamp Low Capacitance TVS Diode Array PRELIMINARY Features

RClamp TM 0504M RailClamp Low Capacitance TVS Diode Array PRELIMINARY Features Description RailClamps are surge rated diode arrays designed to protect high speed data interfaces. The RClamp series has been specifically designed to protect sensitive components which are connected

More information

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS 10-BIT BUS SWITCH WITH FLOW-THROUGH PINOUT

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS 10-BIT BUS SWITCH WITH FLOW-THROUGH PINOUT QUICKSWITCH PRODUCTS HIGH-SPEED CMOS 10-BIT BUS SWITCH WITH FLOW-THROUGH PINOUT IDTQS361 FEATURES: Enhanced N channel FET with no inherent diode to Vcc 5Ω bidirectional switches connect inputs to outputs

More information

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUADRUPLE BUS SWITCH WITH INDIVIDUAL ACTIVE LOW ENABLES

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUADRUPLE BUS SWITCH WITH INDIVIDUAL ACTIVE LOW ENABLES QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUADRUPLE BUS SWITCH WITH INDIVIDUAL ACTIVE LOW ENABLES IDTQS315 FEATURES: Enhanced N channel FET with no inherent diode to Vcc Pin compatible with the 74 15 function

More information

Xpedition xpcb Layout Advanced. Student Workbook

Xpedition xpcb Layout Advanced. Student Workbook Xpedition Student Workbook 2015 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors

More information

Optimum Placement of Decoupling Capacitors on Packages and Printed Circuit Boards Under the Guidance of Electromagnetic Field Simulation

Optimum Placement of Decoupling Capacitors on Packages and Printed Circuit Boards Under the Guidance of Electromagnetic Field Simulation Optimum Placement of Decoupling Capacitors on Packages and Printed Circuit Boards Under the Guidance of Electromagnetic Field Simulation Yuzhe Chen, Zhaoqing Chen and Jiayuan Fang Department of Electrical

More information

MDI for 4x25G Copper and Fiber Optic IO. Quadra (CFP4 proposal) Connector System

MDI for 4x25G Copper and Fiber Optic IO. Quadra (CFP4 proposal) Connector System MDI for 4x25G Copper and Fiber Optic IO Quadra (CFP4 proposal) Connector System Nov 7, 2011 Nathan Tracy, TE Connectivity Tom Palkert, Molex 4x25Gb/s MDI Potential Requirements Critical Needs: Excellent

More information

Tsi381 Board Design Guidelines

Tsi381 Board Design Guidelines Tsi381 Board Design Guidelines September 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 (408) 284-8200 FAX: (408) 284-2775 Printed in U.S.A. 2009, Inc. GENERAL

More information

IDT PEB383 QFP Board Design Guidelines

IDT PEB383 QFP Board Design Guidelines IDT PEB383 QFP Board Design Guidelines February 2010 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 (408) 284-8200 FAX: (408) 284-2775 Printed in U.S.A. 2009 GENERAL

More information

Crosstalk Analysis Application

Crosstalk Analysis Application Crosstalk Analysis Application User's Guide Notices Keysight Technologies, Inc. 2009-2017 No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval

More information

PAD ANALOG / DIGITAL TRAINER OPERATOR S MANUAL

PAD ANALOG / DIGITAL TRAINER OPERATOR S MANUAL PAD - 234 ANALOG / DIGITAL TRAINER OPERATOR S MANUAL Rev. 7/94 GENERAL OPERATING PROCEDURES 1. This manual should be read thoroughly before engaging in any experimentation. 2. As a general rule, NEVER

More information

Multi-Drop LVDS with Virtex-E FPGAs

Multi-Drop LVDS with Virtex-E FPGAs Multi-Drop LVDS with Virtex-E FPGAs XAPP231 (Version 1.0) September 23, 1999 Application Note: Jon Brunetti & Brian Von Herzen Summary Introduction Multi-Drop LVDS Circuits This application note describes

More information

AN-715 APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA Tel: 781/ Fax: 781/

AN-715 APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA Tel: 781/ Fax: 781/ APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Tel: 781/329-4700 Fax: 781/326-8703 www.analog.com A First Approach to IBIS Models: What They Are and How They Are Generated by

More information

ProASIC3/E SSO and Pin Placement Guidelines

ProASIC3/E SSO and Pin Placement Guidelines ProASIC3/E SSO and Pin Placement Guidelines Introduction SSO Effects Ground bounce and VCC bounce have always been present in digital integrated circuits (ICs). With the advance of technology and shrinking

More information

National Semiconductor Application Note 1115 John Goldie July FIGURE 2. Device Configurations

National Semiconductor Application Note 1115 John Goldie July FIGURE 2. Device Configurations DS92LV010A Bus LVDS Transceiver Ushers in a New Era of High-Performance Backplane Design Bus LVDS (BLVDS) is a new family of bus interface circuits invented by based on LVDS technology. This family of

More information

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH 32-BIT MULTIWIDTH BUS SWITCHES

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH 32-BIT MULTIWIDTH BUS SWITCHES QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH 3-BIT MULTIWIDTH BUS SWITCHES IDTQS3X5 FEATURES: Enhanced N channel FET with no inherent diode to Vcc Bidirectional switches connect inputs to outputs Zero

More information

Connecting EPSON Display Controllers to Topway LCD Panels

Connecting EPSON Display Controllers to Topway LCD Panels Connecting EPSON Display Controllers to Topway LCD Panels Document Number: Issue Date: 2012/04/23 SEIKO EPSON CORPORATION Rev. 1.0 Page 2 NOTICE No part of this material may be reproduced or duplicated

More information

ProASIC PLUS SSO and Pin Placement Guidelines

ProASIC PLUS SSO and Pin Placement Guidelines Application Note AC264 ProASIC PLUS SSO and Pin Placement Guidelines Table of Contents Introduction................................................ 1 SSO Data.................................................

More information

Application of Zero Delay Buffers in Switched Ethernet

Application of Zero Delay Buffers in Switched Ethernet 3 Application Note15 Application of Zero Delay Buffers in Switched Ethernet By Cameron Katrai Abstract With the best and tightest characteristics of any PLL driver, Pericom s collection of Zero Delay Clock

More information

Report # 20GC004-1 November 15, 2000 v1.0

Report # 20GC004-1 November 15, 2000 v1.0 I N T E R C O N N E C T A P P L I C A T I O N N O T E Z-PACK HS3 Connector Routing Report # 20GC004-1 November 15, 2000 v1.0 Z-PACK HS3 6 Row 60 Position and 30 Position Connectors Copyright 2000 Tyco

More information

HYPERLYNX DDR3 Wizard

HYPERLYNX DDR3 Wizard HYPERLYNX DDR3 Wizard w w w. m e n t o r. c o m HyperLynx DDR3 Wizard Virtual Lab Exercise Guide This tutorial outlines the steps for completing a DDR3 Wizard DDR analysis example in HyperLynx BoardSim.

More information

Installing the Right Ethernet Interconnect to Ensure Reliable Performance in Aircraft. White Paper

Installing the Right Ethernet Interconnect to Ensure Reliable Performance in Aircraft. White Paper Installing the Right Ethernet Interconnect to Ensure Reliable Performance in Aircraft White Paper October 2016 Today s aerospace industry is demanding faster digital networks with increased performance

More information

T1/E1 CLOCK MULTIPLIER. Features

T1/E1 CLOCK MULTIPLIER. Features DATASHEET ICS548-05 Description The ICS548-05 is a low-cost, low-jitter, high-performace clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using IDT s patented analog/digital

More information

High Speed Characterization Report. DVI-29-x-x-x-xx Mated With DVI Cable

High Speed Characterization Report. DVI-29-x-x-x-xx Mated With DVI Cable High Speed Characterization Report DVI-29-x-x-x-xx Mated With DVI Cable REVISION DATE: 07-18-2004 TABLE OF CONTENTS Introduction... 1 Product Description... 1 Overview... 2 Results Summary... 3 Time Domain

More information

INTRODUCTION REFLECTION AND REFRACTION AT BOUNDARIES. Introduction. Reflection and refraction at boundaries. Reflection at a single surface

INTRODUCTION REFLECTION AND REFRACTION AT BOUNDARIES. Introduction. Reflection and refraction at boundaries. Reflection at a single surface Chapter 8 GEOMETRICAL OPTICS Introduction Reflection and refraction at boundaries. Reflection at a single surface Refraction at a single boundary Dispersion Summary INTRODUCTION It has been shown that

More information

Schematic/Design Creation

Schematic/Design Creation Schematic/Design Creation D A T A S H E E T MAJOR BENEFITS: Xpedition xdx Designer is a complete solution for design creation, definition, and reuse. Overview Creating competitive products is about more

More information

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS 10-BIT BUS SWITCH

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS 10-BIT BUS SWITCH QUICKSWITCH PRODUCTS HIGH-SPEED CMOS 10-BIT BUS SWITCH IDTQS338 FEATURES: Enhanced N channel FET with no inherent diode to Vcc 5Ω bidirectional switches connect inputs to outputs Zero propagation delay,

More information

JitKit. Operator's Manual

JitKit. Operator's Manual JitKit Operator's Manual March, 2011 LeCroy Corporation 700 Chestnut Ridge Road Chestnut Ridge, NY, 10977-6499 Tel: (845) 578-6020, Fax: (845) 578 5985 Internet: www.lecroy.com 2011 by LeCroy Corporation.

More information

EPROM. Application Note CMOS EPROM. Interfacing Atmel LV/BV EPROMs on a Mixed 3-Volt/5- Volt Data Bus

EPROM. Application Note CMOS EPROM. Interfacing Atmel LV/BV EPROMs on a Mixed 3-Volt/5- Volt Data Bus Interfacing Atmel LV/BV EPROMs on a Mixed 3-volt/5-volt Data Bus Introduction Interfacing Atmel Corporation s low voltage (LV/BV) EPROMs on a common data bus with standard 5-volt devices can be achieved

More information

Designing the Right Ethernet Interconnect to Increase High-Speed Data Transmission in Military Aircraft. White Paper

Designing the Right Ethernet Interconnect to Increase High-Speed Data Transmission in Military Aircraft. White Paper Designing the Right Ethernet Interconnect to Increase High-Speed Data Transmission in Military Aircraft White Paper May 216 Abstract: Designing the right high-speed Interconnect that enables systems to

More information

Technical Data Sheet Photolink- Fiber Optic Receiver

Technical Data Sheet Photolink- Fiber Optic Receiver Technical Data Sheet Photolink- Fiber Optic Receiver Features 1. High PD sensitivity optimized for red light 2. Data : NRZ signal 3. Low power consumption for extended battery life 4. Built-in threshold

More information

MAX 10 FPGA Signal Integrity Design Guidelines

MAX 10 FPGA Signal Integrity Design Guidelines 2014.12.15 M10-SIDG Subscribe Today s complex FPGA system design is incomplete without addressing the integrity of signals coming in to and out of the FPGA. Simultaneous switching noise (SSN) often leads

More information

Layer Stackup Wizard: Intuitive Pre-Layout Design

Layer Stackup Wizard: Intuitive Pre-Layout Design Application Brief Layer Stackup Wizard: Intuitive Pre-Layout Design INTRODUCTION This Application Brief describes the Layer Stackup Wizard, a powerful utility within ANSYS SIwave for pre-layout stackup

More information

Flow-through. Pipelined Address Controls APPLICATION NOTE AN-254 THE MOST COMMONLY ASKED QUESTIONS ABOUT SYNCHRONOUS DUAL-PORT SRAMS.

Flow-through. Pipelined Address Controls APPLICATION NOTE AN-254 THE MOST COMMONLY ASKED QUESTIONS ABOUT SYNCHRONOUS DUAL-PORT SRAMS. THE MOST COMMONLY ASKED QUESTIONS ABOUT SYNCHRONOUS DU-PORT SRAMS APPLICATION NOTE AN-254 By Cheryl Brennan What is a dual-port? A dual-port SRAM is a single static RAM array with two sets of address,

More information

Session 4a. Burn-in & Test Socket Workshop Burn-in Board Design

Session 4a. Burn-in & Test Socket Workshop Burn-in Board Design Session 4a Burn-in & Test Socket Workshop 2000 Burn-in Board Design BURN-IN & TEST SOCKET WORKSHOP COPYRIGHT NOTICE The papers in this publication comprise the proceedings of the 2000 BiTS Workshop. They

More information

T10 Technical Committee From: Barry Olawsky, HP Date: 13 January 2005 Subject: T10/05-025r1 SFF8470 Crosstalk Study

T10 Technical Committee From: Barry Olawsky, HP Date: 13 January 2005 Subject: T10/05-025r1 SFF8470 Crosstalk Study To: T10 Technical Committee From: Barry Olawsky, HP (barry.olawsky@hp.com) Date: Subject: T10/ Revision History Revision 0 (5 January 2005) First revision Revision 1 () Second revision Further clarify

More information

A Practical Approach to Preventing Simultaneous Switching Noise and Ground Bounce Problems in IO Rings

A Practical Approach to Preventing Simultaneous Switching Noise and Ground Bounce Problems in IO Rings A Practical Approach to Preventing Simultaneous Switching Noise and Ground Bounce Problems in IO Rings Dr. Osman Ersed Akcasu, Jerry Tallinger, Kerem Akcasu OEA International, Inc. 155 East Main Avenue,

More information

HyperLynx DDRx Interface Analysis. Student Workbook

HyperLynx DDRx Interface Analysis. Student Workbook HyperLynx DDRx Interface Analysis Student Workbook 2017 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation

More information

Features. Applications

Features. Applications HCSL-Compatible Clock Generator for PCI Express General Description The is the smallest, high performance, lowest power, 2 differential output clock IC available for HCSL timing applications. offers -130dBc

More information

Q2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation Gbps. Revision Date: February 13, 2009

Q2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation Gbps. Revision Date: February 13, 2009 Q2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation 2 5.0 Gbps Revision Date: February 13, 2009 Copyrights and Trademarks Copyright 2009 Samtec, Inc. Developed in conjunction

More information

Board Design Guidelines for PCI Express Architecture

Board Design Guidelines for PCI Express Architecture Board Design Guidelines for PCI Express Architecture Cliff Lee Staff Engineer Intel Corporation Member, PCI Express Electrical and Card WGs The facts, techniques and applications presented by the following

More information

AOZ8900. Ultra-Low Capacitance TVS Diode Array PRELIMINARY. Features. General Description. Applications. Typical Application

AOZ8900. Ultra-Low Capacitance TVS Diode Array PRELIMINARY. Features. General Description. Applications. Typical Application Ultra-Low Capacitance TS Diode Array General Description The is a transient voltage suppressor array designed to protect high speed data lines from Electro Static Discharge (ESD) and lightning. This device

More information

AN 523: Cyclone III Devices Configuration Interface Guidelines with EPCS Devices

AN 523: Cyclone III Devices Configuration Interface Guidelines with EPCS Devices AN 523: Devices Configuration Interface Guidelines with Devices February 2014 AN-523-1.3 Introduction This application note provides the guidelines to Cyclone III family devices ( and LS devices) interfacing

More information

High Speed and High Power Connector Design

High Speed and High Power Connector Design High Speed and High Power Connector Design Taiwan User Conference 2014 Introduction High speed connector: Electrically small Using differential signaling Data rate >100Mbps High power connector: Static

More information

2mm PITCH METRIC CONNECTORS FOR PCB CONNECTION

2mm PITCH METRIC CONNECTORS FOR PCB CONNECTION 2mm PITCH METRIC CONNECTORS FOR PCB CONNECTION FCN-086 /087 SERIES OVERVIEW Fujitsu s 2mm hard metric connector F-PACK-3 (FCN-086/087 series) are connectors for connecting boards developed to support high-speed

More information

What s New in HyperLynx 8.0

What s New in HyperLynx 8.0 What s New in HyperLynx 8.0 Copyright Mentor Graphics Corporation 2009 All Rights Reserved. Mentor Graphics, Board Station XE Flow, ViewDraw, Falcon Framework, IdeaStation, ICX and Tau are registered trademarks

More information

BUS SWITCHES PROVIDE 5V AND 3V LOGIC CONVERSION WITH ZERO DELAY. Figure 1. 5V & 3V Logic Mixture in PC Design

BUS SWITCHES PROVIDE 5V AND 3V LOGIC CONVERSION WITH ZERO DELAY. Figure 1. 5V & 3V Logic Mixture in PC Design BUS SWITCHES PROVIDE 5V AND 3V LOGIC CONVERSION WITH ZERO DELAY APPLICATION NOTE AN-11A ABSTRACT Battery operated computer systems, such as notebook computers, need support logic with a combination of

More information

IDTQS3VH383 QUICKSWITCH PRODUCTS 2.5V/3.3V 8-BIT HIGH BANDWIDTH BUS EXCHANGE BUS SWITCH

IDTQS3VH383 QUICKSWITCH PRODUCTS 2.5V/3.3V 8-BIT HIGH BANDWIDTH BUS EXCHANGE BUS SWITCH QUICKSWITCH PRODUCTS 2.5V/3.3V 8-BIT HIGH BANDWIDTH BUS EXCHANGE BUS SWITCH IDTQS3VH383 FEATURES: N channel FET switches with no parasitic diode to Vcc Isolation under power-off conditions No DC path to

More information

Reference. Menu Overview. Functions Common to Generator (TX) and Analyzer (RX) AC Power. Selecting 115 VAC or 230 VAC Operation

Reference. Menu Overview. Functions Common to Generator (TX) and Analyzer (RX) AC Power. Selecting 115 VAC or 230 VAC Operation Menu Overview A wide range of "auxiliary" setup functions is provided in the GB1400 Generator and Analyzer Menu systems. To enter the Generator or Analyzer Menu system, simply press the instrument's F1

More information

A Proposed Set of Specific Standard EMC Problems To Help Engineers Evaluate EMC Modeling Tools

A Proposed Set of Specific Standard EMC Problems To Help Engineers Evaluate EMC Modeling Tools A Proposed Set of Specific Standard EMC Problems To Help Engineers Evaluate EMC Modeling Tools Bruce Archambeault, Ph. D Satish Pratapneni, Ph.D. David C. Wittwer, Ph. D Lauren Zhang, Ph.D. Juan Chen,

More information

AN USB332x Transceiver Layout Guidelines

AN USB332x Transceiver Layout Guidelines AN 17.19 USB332x Transceiver Layout Guidelines 1 Introduction SMSC s USB332x comes in a 25 ball Wafer-Level Chip-Scale Package (WLCSP) lead-free RoHS compliant package; (1.95 mm X 1.95 mm, 0.4mm pitch

More information

CheckSum. FUNC-2B Functional Test Module. The FUNC-2B features:

CheckSum. FUNC-2B Functional Test Module. The FUNC-2B features: CheckSum FUNC-2B Functional Test Module FUNC-2B Functional Test Module Made in U.S.A. The CheckSum Model FUNC-2B Functional Test System is designed to be used as an extension to a CheckSum ICT System.

More information

Extended core storage for the control data systems

Extended core storage for the control data systems Extended core storage for the control data 64 6600 systems by GALE A. JALLEN Control Data Corporation Minneapolis, Minnesota NTRODUCTON The software operating systems for the Control Data 64/6600 Extended

More information

Modeling of Gigabit Backplanes from Measurements

Modeling of Gigabit Backplanes from Measurements Modeling of Gigabit Backplanes from Measurements Introduction In past few years, the communication and computer industries indicate rapidly increasing demand for accurate SPICE and IBIS models that are

More information

White Paper. AC Surge Protection. Evaluation of Series Element Surge Protective Device for Protection of Electronic Equipment and Systems

White Paper. AC Surge Protection. Evaluation of Series Element Surge Protective Device for Protection of Electronic Equipment and Systems White Paper AC Surge Protection Evaluation of Series Element Surge Protective Device for Protection of Electronic Equipment and Systems Richard Odenberg, Research & Advanced Applications, Founder of Transtector

More information

XRD8775 CMOS 8-Bit High Speed Analog-to-Digital Converter

XRD8775 CMOS 8-Bit High Speed Analog-to-Digital Converter CMOS 8-Bit High Speed Analog-to-Digital Converter April 2002-4 FEATURES 8-Bit Resolution Up to 20MHz Sampling Rate Internal S/H Function Single Supply: 5V V IN DC Range: 0V to V DD V REF DC Range: 1V to

More information

Technical Note LPSDRAM Unterminated Point-to-Point System Design: Layout and Routing Tips

Technical Note LPSDRAM Unterminated Point-to-Point System Design: Layout and Routing Tips Introduction Technical Note LPSDRAM Unterminated Point-to-Point System Design: Layout and Routing Tips Introduction Background Low-power (LP) SDRAM, including both low-power double data rate (LPDDR) and

More information

Teaching Math thru Big Ideas Focusing on Differentiation. Marian Small April 2017 San Diego, CA

Teaching Math thru Big Ideas Focusing on Differentiation. Marian Small April 2017 San Diego, CA Teaching Math thru Big Ideas Focusing on Differentiation Marian Small April 2017 San Diego, CA Our focus today Differentiation by focusing on big ideas Formative assessment/feedback Planning lessons/units

More information

MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION

MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION FEATURES 32K x 8 organization Single +5V power supply +125V programming voltage Fast access time: 45/55/70/90/100/120/150 ns Totally static operation Completely TTL compatible 256K-BIT [32K x 8] CMOS EPROM

More information

DDR4 Design And Verification In Hyperlynx LINESIM/Boardsim

DDR4 Design And Verification In Hyperlynx LINESIM/Boardsim DDR4 Design And Verification In Hyperlynx LINESIM/Boardsim Rod Strange Business Development Manager Teraspeed Consulting A Division of Samtec April 2016 Outline Objective/Goal DDR4 vs. DDR3 from the SI/PI

More information

EXAMINING THE IMPACT OF SPLIT PLANES ON SIGNAL AND POWER INTEGRITY

EXAMINING THE IMPACT OF SPLIT PLANES ON SIGNAL AND POWER INTEGRITY EXAMINING THE IMPACT OF SPLIT PLANES ON SIGNAL AND POWER INTEGRITY Jason R. Miller, Gustavo J. Blando, Roger Dame, K. Barry A. Williams and Istvan Novak Sun Microsystems, Burlington, MA 1 AGENDA Introduction

More information

XS1 Link Performance and Design Guidelines

XS1 Link Performance and Design Guidelines XS1 Link Performance and Design Guidelines IN THIS DOCUMENT Inter-Symbol Delay Data Rates Link Resources Booting over XMOS links XS1 System Topologies Layout Guidelines Deployment Scenarios EMI This document

More information

PCI-X Addendum to the PCI Compliance Checklist. Revision 1.0a

PCI-X Addendum to the PCI Compliance Checklist. Revision 1.0a PCI-X Addendum to the PCI Compliance Checklist Revision 1.0a August 29, 2000 PCI-X Addendum to the PCI Compliance Checklist REVISION REVISION HISTORY DATE 1.0 Initial Release 3/1/00 1.0a Updates for PCI-X

More information

Multi-Channel Design Concepts

Multi-Channel Design Concepts Multi-Channel Design Concepts Old Content - visit altium.com/documentation Modified by on 6-Nov-2013 Altium Designer introduces a robust multi-channel design system that even supports channels nested within

More information

PCB insertion loss test system

PCB insertion loss test system PCB insertion loss test system Accurate measurement of transmission line insertion loss for multi-ghz PCB fabrication Atlas Si - for SET2DIL Atlas Si - for SPP Ensures accurate insertion loss measurement

More information

QUICKSWITCH PRODUCTS 2.5V / 3.3V 20-BIT DUAL PORT, HIGH BANDWIDTH BUS SWITCH

QUICKSWITCH PRODUCTS 2.5V / 3.3V 20-BIT DUAL PORT, HIGH BANDWIDTH BUS SWITCH QUICKSWITCH PRODUCTS 2.5V / 3.3V 20-BIT DUAL PORT, HIGH BANDWIDTH BUS SWITCH IDTQS3VH1662 FEATURES: N channel FET switches with no parasitic diode to Vcc Isolation under power-off conditions No DC path

More information

Decompensated Operational Amplifiers

Decompensated Operational Amplifiers Decompensated Operational Amplifiers Abstract This paper discusses the what, why, and where of decompensated op amps in section one. The second section of the paper describes external compensation techniques,

More information

ASIX USB-to-LAN Applications Layout Guide

ASIX USB-to-LAN Applications Layout Guide ASIX USB-to-LAN Applications Revision 1.0 Dec. 11th, 2007 1 Revision Date Description 1.0 2007/12/11 New release. ASIX USB-to-LAN Applications Revision History 2 Content 1. Introduction...4 2. 4-Layer

More information

FloTHERM New Functionality

FloTHERM New Functionality FloTHERM New Functionality Software Version fth11.1 2015 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original

More information