Geometry Subsystem Design

Transcription

1 Geometr Susstem Design Ln-D Vn ( 范倫達 ), Ph. D. Deprtment of Computer Science Ntionl Chio Tung Universit Hisnchu, Tiwn Fll, /0/4

2 Outline Geometr Susstem Introduction to Shding Algorithms Proposed Low-Compleit Sudivision Algorithm Proposed Power-Are Efficient Geometr Engine Implementtion nd Comprison Results Summr 2

3 Geometr Susstem Process vertices Trnsform from world spce to imge spce Compute per-verte lighting The front-end of 3D grphic pipeline 3 From

4 Geometr Susstem 3D Grphics Sstem Source: B.-S. Ling, Y.-C. Lee, W.-C. Yeh, C.-W. Jen, "Inde rendering: hrdwre-efficient rchitecture for 3-D grphics in multimedi sstem," IEEE Trns. Multimedi, vol. 4, no. 3, pp , Sep

5 VLSI Signl Processing Sstem Design Spectrum Sstem Level Algorithm Level Architecture Level Logic Level Circuit Level Process Level

6 Introduction to Shding Gourud shding Algorithms Per-verte lighting Less computtion requirement Not good shding qulit Phong shding Per-piel lighting Huge computtion requirement Smooth nd more relistic highlight 6

7 Introduction to Shding Algorithms Phong reflection model: I k I kd Id ( N L) ks Is ( N H) Phong shding Hs smooth nd relistic speculr highlight Compute reflection model for ever piel in the polgon Require much more computtion thn Gourud shding n Shding lgo. Phong shding Gourud shding # of lighting ops. 4,300 piels 6,200 vertices 7 206/0/4

8 Introduction to Shding Algorithms Eisting Approimte Phong Shding Algorithms Tlor epnsion sed pproimte lgorithms Sphericl interpoltion sed pproimte lgorithms Mied shding Sudivision sed pproimte lgorithms No pss Pss Mied shding Sudivision 8

9 Motivtion Smooth highlight nd Phong shding qulit with low power consumption is desired. Gourud shding possesses lower power consumption ut poor qulit. Phong shding possesses high qulit ut consumes more power. Until now, no one eplores the rchitecture of sudivision lgorithms A low compleit sudivision lgorithm is proposed for lower power-re nd ner-phong shding qulit. A power-re efficient VLSI rchitecture of the geometr engine with sclle qulit is proposed to provide stisfctor trde-off etween shding qulit nd power consumption. 9

10 Proposed Low-Compleit Sudivision Algorithm Proposed sudivision lgorithm: () Tringle filtering scheme (2) Forwrd difference scheme (3) Edge function recover scheme (4) Dul spce sudivision scheme (5) Tringle setup coefficient shring scheme 0

11 Dt Flow of the Proposed Low- Compleit Sudivision Algorithm () Tringle filtering scheme (2) Forwrd difference scheme (4) Dul spce sudivision scheme Input tringles Culling H test Pss Pss Sudivision Light vertices No pss Discrded No pss (3) Edge function recover scheme (5) Setup coefficient shring scheme From GE Sudivided tringle? Yes Setup for sudivided tringle Input tringles No To rsterizer Setup for norml tringle Edge function coefficients/verte ttriute prmeters To tringle setup engine

12 Tringle Filtering Eliminte the unnecessr sudivision nd culling opertions for the generted tringles. The concept of mied shding is dopted here. Perform culling efore sudivision Culling Culling Culling Culling 2

13 Sudivision Using Forwrd Difference Sudivision lgorithm using forwrd difference scheme Step : Compute difference vectors: d nd d 2 d d N N 2 ( V S S c ( V 2 -V L -V ) / N ) / N : The numer of segments on ech edge of the originl tringle L :Sudivision level numer. S S Step 2: Generte vertices using the difference vectors V V V i k j V V V i d d d 2 Step 3: Pck the vertices into four 3 tringles nd output them

14 Rsteriztion Anoml (/2) The forwrd difference prol incurs rsteriztion noml. Lost piel 4

15 Rsteriztion Anoml (2/2) Wh the rsteriztion noml hppens? Becuse of the ccumulted numericl errors, vertices A nd A hve different coordintes. The tringles defined A nd A re not djcent to ech other. 5

16 Edge Function Recover (/3) Edge function method Test if piel is inside the tringle Line equtions of edges (edge function) Incorrect verte coordinte leds to wrong edge function Rsteriztion nomlies 6

17 Edge Function Recover (2/3) Edge function recover scheme: Derive edge functions of generted tringles using the coordinte of originl vertices. E A B C C Step : Compute the edge functions: E, E c, E c of the originl tringle using edge function Step 2: Compute the constnt difference vlues: C, C c, C c. kj C : A ( C ( ( ( )( C (( c ) ( B ) ) ) ( C - )( - ) ( 0 )( - ) ( ) 0 )( 7 ) c 0 ))

18 Edge Function Recover (3/3) Step 3: Compute edge functions for smll tringles: E i, E ik, E k, E i, E j, E ji, E kj, E jc, E ck using pre-computed originl edge functions nd the differentil vlues. For emple, for the centrl smll tringle, the edge function E kj Ejk: Akj* Bkj* Ckj 0 A B C kj kj kj A B C C Step 4: Render these smll tringles using the edge functions 8

19 Rendering Results (/4) Tepot 9

20 Rendering Results (2/4) Pwn 20

21 Rendering Results (3/4) Venus 2

22 Rendering Results (4/4) Couch 22

23 Computtion of Edge Function (/2) Recover scheme cn reduce the compleit of evluting the edge functions. 23 C B A C * B * : A E * * 0 c c c c c c c c c c c C B A C * B * : A E * * 0 c c c c c c c c c c c C B A C * B * : A E * * 0 ) * * ( 2 )) )*( ( ) )*( (( 2 c c c c B A B A C ) * * ( 2 )) )*( ( ) )*( (( 2 c c c c c c c c c B A B A C ) * * ( 2 )) )*( ( ) )*( (( 2 c c c c c B A B A C 2 muls + 3 sus 2 muls + sus

24 Computtion of Edge Function (2/2) Evluting one edge function requires: 2 multiplictions + 3 sutrctions = 2 muls + 3 dds For tringle with N S segments on ech edge, there re totl 3N S edge functions to e computed. Evluting ll edge functions for these tringles requires: 3*N S *(2 muls + 3 dds) = 6*N S muls + 9 * N S dds With the proposed recover scheme, the computtion onl requires: 3*(2 muls + 3 dds) + (3*N S -3) * ( su) + 3*(2 muls + dd) = 2 muls + (3*N S +9) dds 24

25 Dul Spce Sudivision (/4) Trnsforms in GE 25 Modelview Trnsform (Oject > Ee) Projection Trnsform (Ee > Clip) Perspective Division (Clip > NDC) Viewport Trnsform (NDC -> Window) oject oject oject ee ee ee z m m m m m m m m m m m m z ee ee ee clip clip clip clip z n f fn n f n f t t t n l r l r l r n w z clip clip clip clip clip clip NDC NDC NDC w z w w z / / / offset NDC scle offset NDC scle offset NDC scle window window window z z z z

26 Dul Spce Sudivision (2/4) Sudivide tringles in oth ee spce nd window spce Reduce the computtion of trnsforms Perspective incorrectl sudivision cn e dopted if the error is cceptle. Ee-spce sudivision dt flow: Dul spce sudivision dt flow: 26

27 Dul Spce Sudivision (3/4) Compleit nlsis of the ee-spce sudivision for one originl tringle. N GV : The numer of the generted vertices. Opertions Modelview trnsform for 3 vertices Norml trnsform for 3 vertices Computtionl Compleit 39 muls + 39 dds 39 muls + 36 dds Sudivision for 6 components : Ee coordinte: ( ee, ee, z ee ) Norml : ( N, N, z N ) Projection trnsform for N GV +3 vertices Perspective division for N GV +3 vertices Viewport trnsform for N GV +3 vertices Totl 27 6(4 L -) dds 5(N GV +3) muls + 3(N GV +3) dds 3(N GV +3) muls + (N GV +3) invs 3(N GV +3) muls + 3(N GV +3) dds ( N GV +87) muls (6 N GV +64 L + 57) dds (N GV +3) invs

28 Dul Spce Sudivision (4/4) Compleit nlsis of the proposed dul spce sudivision for one originl tringle. Opertions Modelview trnsform for 3 vertices Norml trnsform for 3 vertices Projective trnsform for 3 vertices Perspective division for 3 vertices Viewport trnsform for 3 vertices Sudivision for 0 components: Ee coordinte: ( ee, ee, z ee ) Norml : ( N, N, z N ) Window coordinte: ( window, window, zwindow, ) w Totl clip 28 Computtionl Compleit 39 muls + 39 dds 39 muls + 36 dds 35 muls + 33 dds 33 muls + 3 invs 33 muls + 33 dds 0(N GV +2) dds 87 muls (0 N GV +83) dds 3 invs

29 Tringle Setup Coefficient Shring (/3) Eliminte the unnecessr sudivision nd setup opertions for verte ttriutes Screen position Teture coordinte Depth vlue Fog fctor /w 33 mtri inverse nd mtri multipliction for ech ttriute for tringle Shring setup coefficient 3mtri multipliction for ech ttriute Re-setup for generted tringles Sudivider Screen position Ee spce coordinte Norml Lighting unit 29

30 Tringle Setup Coefficient Shring (2/3) Verte ttriutes interpoltion Prmeter u i Perspective interpoltion eqution 30 Setup one ttriute of tringle requires one 33 mtri multipliction Setup the coefficients of tringle requires one 33 inverse mtri i i i i i i i i i C B A u C B A u C B A u ] [ ] [ C B A u u u i i i ] [ ] [ u u u C B A i i i

31 Tringle Setup Coefficient Shring Level- cse (3/3) Setup one ttriute for 4 tringles require 4 33 inverse mtri nd multipliction. All sudivided tringles re on the sme plne Setup coefficients: A i, B i, C i cn e shred. Re-setup is required to compute initil point for ech tringle. u A i * Bi * Ci [ Ai Bi C i] Re-setup requires one 3 multipliction 3

32 Compleit Anlsis (/4) Nottion definition: N T : The numer of originl visile tringles N OT : The numer of originl tringles for input models N GV : The numer of new generted vertices in sudivided tringle N A : The numer of verte ttriutes Emple: 32

33 Compleit Anlsis (2/4) Conventionl sudivision lgorithm Proposed sudivision lgorithm Used schemes Numer of memor ccesses (4 L+ -)*N T (2N GV -2 L Forwrd +5)*N T difference Edge function Muls 6*N S *N T 2*N T Edge function evlution Adds 9*N S *N T (3*N S +9)*N T recover Computtion for trnsforms Muls (N GV +87)*N T 87*N T Dul spce Adds (6N GV +64 L + 57)*N T (0N GV +83)*N T sudivision Invs (N GV +3) *N T 3*N T Numer of culling test opertions *N OT *N OT Tringle filtering Numer of 33 mtri multiplictions for setup N A *N S2 *N T Ceiling {/3*N A *N S2 +N A }* N T Setup coefficient shring 33

34 Compleit Anlsis (3/4) Level- cse with L=, N GV =3, N A =5 Conventionl sudivision lgorithm Proposed sudivision lgorithm Compleit reduction percentge Numer of memor ccesses 5*N T 9*N T 40.00% Edge function evlution Computtion for trnsforms Muls 2*N T 2*N T 0% Sus 8*N T 5*N T 6.67% Muls 20*N T 87*N T 27.50% Adds 99*N T 3*N T -4.4% Invs 6*N T 3*N T 50.00% Numer of 33 mtri multiplictions for setup 20*N T 2*N T 40.00% 34

35 Compleit Anlsis (4/4) Level-2 cse with L=2, N GV =2, N A =5 Conventionl sudivision lgorithm Proposed sudivision lgorithm Compleit reduction percentge Numer of memor ccesses 63*N T 25*N T 68.88% Edge function evlution Computtion for trnsforms Muls 24*N T 2*N T 50.00% Sus 36*N T 2*N T 4.67% Muls 29*N T 87*N T 60.27% Adds 225*N T 203*N T 9.78% Invs 5*N T 3*N T 80.00% Numer of 33 mtri multiplictions for setup 80*N T 32*N T 60.00% 35

36 Proposed Power-Are Efficient Geometr Susstem Proposed GE Architecture Proposed Primitive Processing Unit (PPU) Proposed Verte Processing Unit (VPU) Reconfigurle Dtpth (RDP) light_dp trns_dp vec_norm pd POW vec_su 36

37 Proposed GE Architecture Oject spce culling Sudivision Trnsforms Lighting 37

38 Proposed GE Architecture Hrdwre feture Power-re efficient design Achieve power-re efficienc (PAE): 545. Kvertices/(s*mW*mm 2 ) Sudivision-sed sclle shding qulit support Support level-0, level- nd level-2 High performnce nd re efficient verte processing unit with reconfigurle dtpth (RDP) Speed up complicted opertions. EX: vector normliztion Hrdwre reusing 38

39 Proposed Primitive Processing Unit d => Reg_Hdiff d 2 => Reg_Vdiff 39

40 Proposed Verte Processing Unit 40

41 Proposed Reconfigurle Dtpth (RDP) Ke components : Processing elements (PE) Specil function unit (SFU) FIFO Configurtions: Configurtion Modes light_dp trns_dp vec_norm pd POW vec_su Description Dot product for lighting Dot product for trnsform Vector normliztion Perspective division Powering Vector sutrction 4

42 Proposed Verte Processing Unit Fetures High performnce Pek trnsform performnce: 50Mvertices/s Construct ASIC like dtpth for high performnce verte processing vi reconfigurle dtpth. Are efficient Provide different opertions for verte processing with the sme set of PEs. 42

43 Proposed Processing Element (PE) 43

44 Configurtion inside PE MUL 44

45 Configurtion inside PE MAC 45

46 Configurtion inside PE ADD/SUB 46

47 Configurtions etween PEs To clerl eplin interconnection etween PEs, simplified lock digrm PE is given. 47

48 Configurtions etween PEs light _dp [ X, Y, Z] [ X 2, Y2, Z2] = X* X 2 + Y* Y2+ Z* Z2 48

49 Configurtions etween PEs trns_dp [ X, Y, Z, W] [ X 2, Y2, Z2,] = X* X 2 + Y* Y2+ Z* Z2 + W 49

50 Configurtions etween PEs vec_su [ X, Y, Z]-[ X 2, Y2, Z2] 50

51 Configurtions etween PEs vec_norm X norm([ X, Y, Z]) [, Length Y, Length Z ] Length Length X 2 Y 2 Z 2 5

52 Configurtions etween PEs Pd (perspective division) X Y Z [ X, Y, Z] [,, ] W W W 52

53 Specil Function Unit Log Numer Sstem nd Opertions: Inverse Inverse squre root Power (configured with PE) 53

54 Chip Implementtion Result VC rm Rm2 Reg Bnk Power Suppl.8V M. Clock 00 MHz M. Power 28.3 mw with level- Gte Count 83,748 Core Are 2.73 mm 2 Constnt Mem Process Technolog TSMC 0.8 um CMOS Process 54

55 Comprison Results Level-0 Level- Level-2 55

56 Comprison Results PAE JSSC 2006 [2] JSSC 2007 [3] ISSCC 2007 [4] JSSC 2008 [5] This Work level-0 level- level-2 Process (nm) Frequenc (MHz) Polgon Rte (Mvertices/s) Pek Performnce of Geomert Trnsform (Kvetices/s) Power (mw) Core Are (mm * /2.5* 2 50* /25* 2 Power (mw) 55* Core Are (mm 2 ) * ) Power-Are Efficienc (Kvertices/(s mw mm 2 )) Feture Grphics Grphics Grphics Grphics, DSP Grphics with sclle-qulit hrdwre support *: With cche hit rte of 50%. *2: With cche hit rte of 0%. *3: Include rendering engine. *4: With the core re of 2.64mm2.797mm nd see cknowledgement. 56

57 Conclusions Proposed n efficient sudivision lgorithm Low compleit The reduction of the numer of memor ccesses cn e ttined 44.44% nd 68.89% for level- nd level-2, respectivel. The reduction of the numer of multiplictions for trnsforms cn e ttined 27.50% nd 60.27% for level- nd level-2, respectivel. Sclle nd ner Phong shding qulit Proposed power-re efficient geometr engine Compred with [2-5], the proposed geometr engine hs etter power-re efficienc with 545. Kvertices/(s mw mm 2 ) for level- sudivision. Compred with work in [5], the proposed geometr engine cn increse the power-re efficienc 34.7%, 3.4%, nd -2.6% with level-0, level-, level- 2, respectivel /0/4

58 Reference [] F. Arkw et l., An emedded processor core for consumer pplictions with 2.8 GFLOPS nd 36 Mpolgons/s FPU, IEEE ISSCC, Fe. 2004, pp [2] J. Sohn et l., A 55-mW 50-Mvertices/s grphics processor with fied-point progrmmle verte shder for moile pplictions, IEEE J. Solid-Stte Circuits, vol. 4, no. 5, pp , M [3] C. H. Yu, K. Chung, D. Kim nd L. S. Kim, "An Energ-Efficient Moil Verte Processor With Multithred Epnded VLIW Architecture nd Verte Cches," IEEE J. Solid-Stte Circuits, vol. 42, no. 0, Oct [4 ]B. G. Nm, J. Lee, K. Kim, S. J. Lee, nd H.-J. Yoo, A 52.4 mw 3-D grphics processor with 4 Mvertices/s verte shder nd 3 power domins of dnmic voltge nd frequenc scling, ISSCC 2007, pp [5 ]S. Y. Chien, Y. M. Tso, C. H. Chng nd Y. C. Lin, An 8.6 mw 25 Mvertices/s 400-MFLOPS 800-MOPS 8.9 mm 2 Multimedi Strem Processor Core for Moile Applictions, IEEE J. Solid-Stte Circuit, vol. 43, issue. 9, pp , Sep