UT1553B BCRT True Dual-port Memory Interface

Transcription

1 UTMC APPICATION NOTE UT553B BCRT True Dul-port Memory Interfce INTRODUCTION The UTMC UT553B BCRT is monolithic CMOS integrted circuit tht provides comprehensive MI-STD- 553B Bus Controller nd Remote Terminl functions. The BCRT design reduces the overhed plced on the host computer y utomticlly executing messge trnsfers, providing interrupts, nd generting sttus informtion. The BCRT off-lods the host processor with uilt-in memory mngement functions designed specificlly for MI-STD- 553B pplictions. This mens tht the host need only estlish the necessry dt nd/or control prmeters in memory so the BCRT cn ccess the informtion s required nd, therefore, provide the requisite MI-STD-553B us functions. UTMC vrints of the BCRT re the BCRTM, BCRT with monitor functions, nd the BCRTMP, BCRT which opertes in wide vriety of 553 protocols. This note will discuss true dul-port (TDP) interfce configurtion. The design uses 2K x 6 dul-port memory device ville from severl mnufcturers. If dditionl memory is needed, the designer cn incorporte more thn one memory chip. Some mnufcturers lso offer single pckge dul-port RAM ssemlies in configurtions up to 8K x 6. This interfce is pplicle to the BCRT, the BCRTM, nd the BCRTMP. TRUE DUA-PORT CONFIGURATION The TDP configurtion s min dvntge over oth the DMA (direct memory ccess) nd PDP (pseudo dul-port) configurtions is tht it genertes miniml impct on the host processor s opertions. In the DMA configurtion, the processor must e put on hold during ny BCRT memory ccess. Using the PDP method, the processor must wit for the BCRT whenever the BCRT is ccessing common memory. The only time the processor must wit in the TDP configurtion is when the processor tries to ccess the exct sme memory loction to which the BCRT lredy hs ccess, or when the host processor needs to ccess one of the BCRT s internl registers nd the BCRT is in memory cycle. The TDP configurtion s min disdvntge is cost. The price of dul-port devices is significntly higher thn tht of stndrd memory, nd the density of the memory devices is lower. Of course, in system where throughput is the driving issue, the TDP method is the most effective solution. CIRCUIT OPERATION - MEMORY ARBITRATION Figure shows the circuit s sic configurtion. Figure 2 detils opertion of the PD. The PD is designed s Mely mchine to improve response time nd simplify stte trnsitions. The dul-port RAM contins two signls: BUSY nd BUSYR. When oth the host nd BCRT ccess the sme memory loctions t the sme time, one of these signls will ssert. Generlly, the rules outlined in tle re followed. Tle. Simultneous Memory Aritrtion CONDITION WINNING SIDE NOTES left ns efore right left right ns efore left right left/right within ns of ech other ritrtion, 2 Notes:. = detection limit, this vlue is etween 2 nd ns depending upon the device used. 2. Aritrtion lgorithm depends on device. Exmples: lwys give to left, give to side which didn t hve it lst, rndom, etc. The TDP configurtion outlined in this note uses BUSY, BUSYR,, DMAG, MEMCSI, BCRTCS, nd to properly ritrte RAM use. When the BCRT needs to red or write to dul-port memory, it sserts. If (or when) the host ccess to memory is inctive (i.e., MEMCSI is desserted), DMAG will e sserted nd the BCRT will egin its memory cycle. Note tht in this cse, the memory loction eing ccessed does not ffect the ritrtion decision. This would seem to defet the purpose of the dul-port. owever, the BCRT- side ritrtion must work this wy for the following comintion of resons:. In order to determine usy condition in the dul-port RAM, ll ddresses must e known. 2. Once the BCRT receives DMAG, there is no wy to dely completion of its memory cycle.

2 Thus, if we try to give the BCRT grnt nd use BUSYR for collision, there is no wy to use BUSYR to dely the BCRT when n ddress mtch occurs. This is relly not prolem; since the BCRT s throughput is not very high, it cn fford to wit for host memory cycle to complete. Figure 3 shows BCRT-memory ccess timing. Note: Most host ccess times re smll (/) compred to the BCRT request-to-grnt requirement of.9µs t 2Mz. owever, when designing system, this requirement should not e overlooked. When the host ccesses memory, it is only delyed if collision occurs, thus relizing the dvntge of the dulport RAM. If nd only if n ddress mtch occurs, BUSY will ssert nd the host will hve to wit for the BCRT to complete its cycle. If the host ccesses memory loction other thn the one the BCRT is using, oth the BCRT nd host will complete their memory cycles normlly. Figure 5 shows the timing digrms for host-memory ccesses oth with nd without ritrtion. A specil ritrtion cse my lso occur in this design. After the BCRT receives DMAG, the host my ccess memory. The BCRT my tke up to four MCK periods efore it ctully egins the memory ccess, thus it is possile the host my egin cycle fter DMAG hs sserted ut efore MEMCSO on the BCRT sserts. Since the BCRT hs lredy strted cycle, it is too lte to stop this ccess. If the host nd BCRT ddress the sme memory loction in this sitution, BUSYR will ssert. As ws lredy stted, there is no wy to stop the BCRT in this sitution. To correct this prolem, the host will e delyed if BUSYR sserts. The signl will dessert nd the chip select to the host side of memory will e locked. This clers the BUSYR condition. The BCRT will complete its cycle. After completion, the host chip select will e resserted nd the host cycle will complete. The PD device controls ll of the ritrtion. It consists of stte mchine to control ccess to the BCRT us nd some rndom logic to generte the signl. Specil Cutions Since this document is written for generic processor, some cutions re necessry for direct use of this design:. To prevent multiple BCRT red/write opertions, the BCSI (BCRT chip select in) signl must e sserted low for no more thn one cycle fter the flling edge of. 2. The signl stys in n sserted stte to fcilitte fster memory ccess times. Thus during host-to-bcrt cycle, the signl must dessert high first. This dessertion my tke s long s two clock cycles. 3. During host-to-bcrt register red, the dt from the BCRT is only vlid for one clock cycle fter the signl is sserted low. 4. During host-to-memory cycle, the signl is synchronous; it my chnge to desserted stte t ny time during the cycle. As long s the host cycle does not complete while is desserted, no prolems will occur. REGISTER ARBITRATION The sme Address/Dt us is used for oth BCRT register ccess y the host nd memory ccess y the BCRT. Thus, when the host ccesses BCRT internl register, it must wit for the BCRT to complete current memory cycle. This is ccomplished using the host s signl nd the BCRT s DMACK signl. When the BCRT is given grnt, DMACK is sserted until the BCRT is finished. The ssertion of DMACK will prevent the ddress/dt uffers nd the line from eing enled. When the BCRT completes, the uffers re enled. One clock cycle lter, the signl will ssert. Figure 4 shows the timing digrms for host-bcrt ccesses with nd without ritrtion. FURTER ASSISTANCE Due to the vriety of processors to which the BCRT cn e connected, this document cnnot ddress ll the possiilities. Contct UTMC pplictions support for dditionl ssistnce. 2

3 BCRTCS MEMCSI + + BCSI PD + + MCSI BUSY BUSY BUSY BUSY BMCSO + DUA-PORT RAM BCSO ABUFEN CS DMAG CS MEMCSO RD R RRD R R G 245 O/I G 244 O 3

4 BCSO DMACK I ABUFEN BUSY + D R MCSO BUSYR MCSI To void confusion, the PD design is implemented in positive (ctive high) logic. It will e necessry to dd inverters to the design where DMAG BCSO DMAG I** BCSI BCSO + MCSI BCSO c - * low if is not sserted ** low if BCSI is sserted BCSO* Figure 2. PD Description 4

5 5 PD stte mchine equtions: BCSO : = - BCSI - S - S + S - SI - DMAG : = MCSI - - S - S : = S - + S I : = S MCSI S - - BCSI + S - S NS : S S S NS : BCSI x = don t cre = outputs which will proly need inversion MCSI BCSI DMACK BCSO DMAG I S NS c INPUT VARIABES NET OUTPUT VARIABES c c

6 no ritrtion (MCSI never sserted) CK MACINE DMAG DMACK ritrtion with host to memory ccess CK MACINE MCSI DMAG DMACK ritrtion with host to BCRT ccess - worst cse CK MACINE BCSI c DMAG DMACK Figure 3. BCRT-Memory Access (Single Word) 6

7 no ritrtion red CK MACINE c BCSI BCSO RD no ritrtion write CK MACINE c BCSI BCSO Figure 4. ost-bcrt Access 7

8 MCSI red write ritrtion MCSI red write RD 8