ECEN 468 Advanced Logic Design Lecture 36: RTL Optimization

Transcription

1 ECEN 468 Advnced Logic Design Lecture 36: RTL Optimiztion ECEN 468 Lecture 36

2 RTL Design Optimiztions nd Trdeoffs 6.5 While creting dtpth during RTL design, there re severl optimiztions nd trdeoffs, involving Pipelining Concurrency Component lloction Opertor binding Opertor scheduling Moore vs. Mely high-level stte mchines 2

3 Pipelining Intuitive exmple: Wshing dishes with friend, you wsh, friend dries You wsh plte 1 Then friend dries plte 1, while you wsh plte 2 Then friend dries plte 2, while you wsh plte 3; nd so on You don t sit nd wtch friend dry; you strt on the next plte Pipelining: Brek tsk into stges, ech stge outputs dt for next stge, ll stges operte concurrently (if they hve dt) Without pipelining: W1 D1 W2 D2 W3 D3 With pipelining: W1 W2 W3 D1 D2 D3 Time Stge 1 Stge 2 3

4 Pipelining Exmple W X Y Z W X Y Z clk + + 2ns + 2ns 2ns Longest pth is 2+2 = 4 ns So minimum clock period is 4ns Stge 1 Stge 2 clk + + 2ns + 2ns 2ns Longest pth is only 2 ns pipeline registers So minimum clock period is 2ns S clk S clk S S(0) S(1) S = W+X+Y+Z Dtpth on left hs criticl pth of 4 ns, so fstest clock period is 4 ns Cn red new dt, dd, nd write result to S, every 4 ns Dtpth on right hs criticl pth of only 2 ns So cn red new dt every 2 ns doubled performnce (sort of...) S S(0) S(1) 4

5 Pipelining Exmple W X Y Z W X Y Z clk Longest pth is 2+2 = 4 ns So mininum clock period is 4 ns clk Longest pth is only 2 ns pipeline registers So mininum clock period is 2 ns S clk S clk S S(0) S(1) S S(0) S(1) ( ) ( b ) Pipelining requires refined definition of performnce Ltency: Time for new dt to result in new output dt (seconds) Throughput: Rte t which new dt cn be input (items / second) So pipelining bove system: Doubled the throughput, from 1 item / 4 ns, to 1 item / 2 ns Ltency styed the sme: 4 ns 5

6 Pipeline Exmple: FIR Dtpth 100-tp FIR filter: Row of 100 concurrent multipliers, followed by tree of dders X xt registers Assume 20 ns per multiplier 14 ns for entire dder tree Criticl pth of = 34 ns Add pipeline registers Longest pth now only 20 ns Clock frequency cn be nerly doubled Gret speedup with miniml extr hrdwre Stge 2 Stge 1 20 ns 14 ns pipeline registers multipliers x x dder tree yreg Y 6

7 Concurrency Concurrency: Divide tsk into subprts, execute subprts simultneously Dishwshing exmple: Divide stck into 3 substcks, give substcks to 3 neighbors, who work simultneously 3 times speedup (ignoring time to move dishes to neighbors' homes) Concurrency does things side-byside; pipelining insted uses stges (like fctory line) Alredy used concurrency in FIR filter concurrent multiplictions Tsk Pipelining Concurrency Cn do both, too * * * 7

8 Concurrency Exmple: SAD Design Revisited Sum-of-bsolute differences video compression exmple (Ch 5) Compute sum of bsolute differences (SAD) of 256 pirs of pixels Originl : Min loop did 1 sum per itertion, 256 itertions, 2 cycles per iter. go AB_rd AB_ddr A_dt B_dt i_lt_256' S0 go S1 S2 S4 go ʹ sum_clr=1 i_clr=1 i_lt_256 AB_rd=1 " S3 sum_ld=1" i_inc=1 sd_reg_ld=1 Controller i_lt_256 i_inc i_clr sum_ld sum_clr sdreg_ld sdreg_clr Dtpth 256 iters.*2 cycles/iter. = 512 cycles lt A cmp B 256 sum 32 sdreg 32 9 A i bs sd -/bs/+ done in 1 cycle, but done 256 times B

9 Concurrency Exmple: SAD Design Revisited More concurrent design Compute SAD for 16 pirs concurrently, do 16 times to compute ll 16*16=256 SADs. Min loop does 16 sums per itertion, only 16 iters., still 2 cycles per iter. Orig: 256*2 = 512 cycles New: 16*2 = 32 cycles i_lt_16' S0 go S1 S2 i_lt_16 AB_ r d=1 sum_ld=1 i_inc=1 S4!go sum_clr=1 i_clr=1 go AB_ r d sd_ r eg_ld=1 C o n t r oller i_lt_16 i_inc i_clr sum_ld sum_clr D tp th <16 sd_ r eg_ld AB_ddr i sum sd_ r eg sd A0 B0 A1 B1 A14 B14 A15 B15 bs bs bs bs All -/bs/+ s shown done in 1 cycle, but done only 16 times 16 subtrctors 16 bsolute vlues Adder tree to sum 16 vlues 9

10 Concurrency Exmple: SAD Design Revisited Compring the two designs Originl: 256 itertions * 2 cycles/iter = 512 cycles More concurrent: 16 itertions * 2 cycles/iter = 32 cycles Speedup: 512/32 = 16x speedup Versus softwre Recll: Estimted bout 6 microprocessor cycles per itertion 256 itertions * 6 cycles per itertion = 1536 cycles Originl design speedup vs. softwre: 1536 / 512 = 3x (ssuming cycle lengths re equl) Concurrent design s speedup vs. softwre: 1536 / 32 = 48x 48x is very significnt qulity of video my be much better 10

11 Component Alloction Another RTL trdeoff: Component lloction Choosing prticulr set of functionl units to implement set of opertions e.g., given two sttes, ech with multipliction Cn use 2 multipliers (*) OR, cn insted use 1 multiplier, nd 2 muxes Smller size, but slightly longer dely due to the mux dely A B t1 := t2*t3 t4 := t5*t6 FSM-A: (t1ld=1) B: (t4ld=1) t2 t3 t5 t6 A: (sl=0; sr=0; t1ld=1) B: (sl=1; sr=1; t4ld=1) sl t2 t5 t3 t sr size 2 mul 1 mul * * * t1 () t4 t1 (b) t4 dely (c) 11

12 Opertor Binding Another RTL trdeoff: Opertor binding Mpping set of opertions to prticulr component lloction Note: opertor/opertion men behvior (multipliction, ddition), while component (k functionl unit) mens hrdwre (multiplier, dder) Different bindings my yield different size or dely A B C A B C t1 = t2 * t3 t4 = t5 * t6 t7 = t8 * t3 t1 = t2 * t3 t4 = t5 * t6 t7 = t8 * t3 t2 t3 t5 t8 t6 t3 sl 2x1 2x1 sr 2 muxes vs. 1 mux t2 t8 sl 2x1 t3 t5 t6 size Binding 1 Binding 2 2 multipliers llocted MULA MULB MULA MULB del y t1 t4 t7 Binding 1 Binding 2 t1 t7 t4 12

13 Opertor Scheduling Yet nother RTL trdeoff: Opertor scheduling Introducing or merging sttes, nd ssigning opertions to those sttes. A (some opertions) B t1 = t2*t3 t4 = t5*t6 C (some opertions) A B B2 C (some t1 = t2 * t3 opertions) t4 = t5 * t6 * t4 = t5 t6 (some opertions) t2 * t1 t3 t5 * t4 t6 size 3-stte schedule 4-stte schedule sl smller (only 1 *) t2 t5 2x1 t1 * t3 t6 2x1 sr t4 but more dely due to muxes, nd extr stte dely 13

14 Opertor Scheduling Exmple: Smller FIR Filter 3-tp FIR filter of Ch 5: Two sttes DP computes new Y every cycle Used 3 multipliers nd 2 dders; cn we reduce the design s size? Inputs: X (12 bits) Outputs: Y (12 bits) Locl storge: xt0, xt1, xt2, c0, c1, c2 (12 bits); Yreg (12 bits) Init FC y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2) FIR filter Yreg := 0 xt0 := 0 xt1 := 0 xt2 := 0 c0 := 3 c1 := 2 c2 := 2 Yreg := c0*xt0 + c1*xt1 + c2*xt2 xt0 := X xt1 := xt0 xt2 := xt1 X xt0_clr xt0_ld c0_ld c1_ld c2_ld c0 c1 c xt0 xt1 xt2 clk x(t) x(t-1) * * x(t-2) * Dtpth for 3-tp FIR filter + + Yreg_clr Yreg_ld Yreg 12 Y 14

15 Opertor Scheduling Exmple: Smller FIR Filter Reduce the design s size by re-scheduling the opertions Do only one multipliction opertion per stte Inputs : X (12 bits) Outputs : Y (12 bits) Locl storge : xt0, xt1, xt2, c0, c1, c2 (12 bits); Yreg (12 bits) S1 ( ) Yreg := c0*xt0 + c1*xt1 + c2*xt2 xt0 := X xt1 := xt0 xt2 := xt1 Inputs : X (12 bits) Outputs : Y (12 bits) Locl storge : xt0, xt1, xt2, c0, c1, c2 (12 bits); Yreg, sum (12 bits) S1 S2 sum := 0 xt0 := X xt1 := xt0 xt2 := xt1 sum := sum + c0 * xt0 S3 sum := sum + c1 * xt1 S4 sum := sum + c2 * xt2 y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2) S5 Yreg := sum ( b ) 15

16 Opertor Scheduling Exmple: Smller FIR Filter Reduce the design s size by re-scheduling the opertions Do only one multipliction (*) opertion per stte, long with sum (+) Inputs : X (12 bits) Outputs : Y (12 bits) Locl storge : xt0, xt1, xt2, c0, c1, c2 (12 bits); Yreg, sum (12 bits) S1 S2 S3 S4 S5 sum := 0 xt0 := X xt1 := xt0 xt2 := xt1 sum := sum + c0*xt0 sum := sum + c1*xt1 sum := sum + c2*xt2 Yreg := sum X clk mul_s1 mul_s0 sum_clr sum_ld c0 c1 xt0 xt1 xt2 3x1 MAC * + sum 3x1 yreg c2 Y Multiplyccumulte: common dtpth component Serilized dtpth for 3-tp FIR filter 16

17 Opertor Scheduling Exmple: Smller FIR Filter Mny other options exist between fully-concurrent nd fully-serilized e.g., for 3-tp FIR, cn use 1, 2, or 3 multipliers Cn lso choose fst rry-style multipliers (which re concurrent internlly) or slower shift-nddd multipliers (which re serilized internlly) Ech options represents compromises size concurrent FIR dely compromises seril FIR 17

18 More on Optimiztions nd Trdeoffs Seril vs. concurrent computtion hs been common trdeoff theme t ll levels of design Seril: Perform tsks one t time Concurrent: Perform multiple tsks simultneously Combintionl logic trdeoffs Concurrent: Two-level logic (fst but big) Seril: Multi-level logic (smller but slower) bc + bd + ef à (b)(c+d) + ef essentilly computes b first (serilized) Dtpth component trdeoffs Seril: Crry-ripple dder (smll but slow) Concurrent: Crry-lookhed dder (fster but bigger) Computes the crry-in bits concurrently Also multiplier: concurrent (rry-style) vs. seril (shift-nd-dd) RTL design trdeoffs Concurrent: Schedule multiple opertions in one stte Seril: Schedule one opertion per stte

19 Higher vs. Lower Levels of Design Optimiztions nd trdeoffs t higher levels typiclly hve greter impct thn those t lower levels Ex: RTL decisions impct size/dely more thn gte-level decisions Spotlight nlogy: The lower you re, the less solution lndscpe is illuminted (mening possible) high-level chnges size dely lnd ( ) ( b ) 19

20 Algorithm Selection Chosen lgorithm cn hve big impct e.g., which filtering lgorithm? FIR is one type, but others require less computtion t expense of lower-qulity filtering Exmple: Quickly find item s ddress in 256-word memory One use: dt compression. Mny others. Algorithm 1: Liner serch Compre item with M[0], then M[1], M[2], comprisons worst cse Algorithm 2: Binry serch (sort memory first) Strt considering entire memory rnge If M[mid]>item, consider lower hlf of M If M[mid]<item, consider upper hlf of M Repet on new smller rnge Dividing rnge by 2 ech step; t most 8 such divisions Only 8 comprisons in worst cse Choice of lgorithm hs tremendous impct Fr more impct thn sy choice of comprtor type 0: 1: 2: 3: 96: 128: 255: Liner serch 0x x x F 0x000000FF 0x00000F0A 0x0000FFAA 0xFFFF x32 memory Binry serch 20