Computer Arithmetic Logical, Integer Addition & Subtraction Chapter

Transcription

1 Computer Arithmetic Logicl, Integer Addition & Sutrction Chpter EEC7 FQ 25 MIPS Integer Representtion -it signed integers,, e.g., for numeric opertions 2 s s complement: one representtion for zero, lnced, llows dd/sutrct to e treted uniformly -it unsigned integers,, e.g., for ddress opertions Address considered -it unsigned integer Provides distinct instructions for signed/unsigned: ADD, ADDI: dd signed register, dd signed immedite cuses exception on overflow ADDU, ADDIU: dd unsigned register, dd unsigned immedite no exception on overflow Rd ADD/U Lyout of full dder cell ADDI/U immedite dt 2 Comprison Distinct instructions for comprison of signed/unsigned integers Which is lrger:... or...? Depends of type, signed or unsigned Two versions of slt for signed/unsigned: slt, sltu: : set less thn signed, unsigned Sign Extension Sign of immedite dt extended to form -it representtion: Rd SLT/U Two versions of immedite comprison lso provided: slti, sltiu: : set less thn immedite signed, unsigned SLTI/U immedite dt Thus, lwys uses -it opernds Extension occurs for signed nd unsigned rithmetic 3 4 Overflow Computer System, Top Level View MIPS hs no flg (sttus) register complictes pipeline (see Chpter 6) Overflow (underflow): Occurs if opernds re sme sign, result is different sign. Cn e checked in softwre if necessry MIPS genertes interrupt on overflow for signed rithmetic to notify progrm C compiler only genertes unsigned rithmetic instructions (voids interrupts) Representtion of result is the sme if signed/unsigned Control Dtpth Processor Compiler Memory Input Output 5 6

2 Simple Processor Dtpth Includes registers nd Cycle : Register Fetch Simple Processor Dtpth Includes registers nd Cycle 2: Opernd Opernd 7 8 Simple Processor Dtpth Includes registers nd Cycle 3: Register Write Bck Processor Control Control directs ctions in the dt pth. Instruction is top level of control Rd ADD Opernd opernd result 9 opernd2 Opernd Inside the dd mux Boolen s Ech pir of inputs resolved using corresponding gte su slt result nd or AND Unit eq/ne 2

3 One Bit Full Adder Full Adder Truth Tle Multiple-it dder cn e uilt from series of one-it full dders Adder truth tle mps inputs to the outputs Input Output Crry In Crry_In Crry_Out Crry Out Crry_Out = *Crry_In + *Crry_In + * 3 = * *Crry_in + * *Crry_in + * *Crry_in + * *Crry_in 4 Crry_Out Implementtion Two s s Complement Sutrction Crry In For two s s complement rithmetic the following is true: X + X = - X + (X + ) = Proof: result of X + X is ll ones + = Crry Out - X = X + Our strtegy for computing A B: convert to A + (-B)( nd use the ove rule for -B 5 6 One Bit Add/Sutrct Cell Modify the dder cell so tht the B input is selectle Binvert Crry In Single Bit Comine gtes with dd/sutrct unit to form - it selects which result is sent out -it s will e connected in chin to form -it Crry Out 7 8

4 Support for Set Less Thn And n input Less to -it for SLT Input connections will e seen soon Most Significnt -Bit Specilize Bit 3 to produce Overflow nd Set (for set less thn) Wht s s inside the overflow detection ox? 9 2 one-it s re cscded to form -it SLT condition is computed using A-B, Set is sign-it of result All other Less inputs set to Set is not ccurte when there s overflow, why? -Bit Support for BEQ/BNE Determine EQ/NE using sutrct opertion All zero result is EQ, else NE How is this corrected? 2 22 Ripple Crry Adder Performnce This Ripple Crry Adder is very slow. Ech stge cuses 3 two-input gte delys: c out = + c c in + c in Vector Arithmetic Allows rithmetic to e done in prllel on sucomponents of register, e.g., rithmetic on ytes: X 3 X 2 X X + Y 3 Y 2 Y Y ==================================== Z 3 Z 2 Z Z For -it dder this would e 96 two-input gte delys, much too slow Cn speedup ddition y using more hrdwre Crry-look hed dder 23 24

5 Vector Arithmetic (cont.) Multimedi Arithmetic Vector rithmetic hs een used for decdes in supercomputers for scientific pplictions Also used for rchitecture extensions to fcilitte multimedi processing for RISC processors nd for x86 (MMX,SIMD), e.g.: The intensity of ech disply dot (pixel) is often represented y yte Arithmetic on vector of ytes llows prllel pixel rithmetic, e.g., dding two scenes together it y it Simple extensions to our MIPS rchitecture nd the -it dder implementtion will llow oth -it rithmetic nd yte-prllel rithmetic: Addv Rd,, Suv Rd,, 25 Multimedi pplictions require unconventionl types of rithmetic. Multimedi rchitecture extensions include new rithmetic opertions E.g., sturting ddition/sutrction: when ltering the intensity of pixel (e.g., dding two scenes, incresing overll intensity y 2x), we do not wnt overflow or underflow to cuse wrp round (right pixel ecomes drk). Overflow or underflow detection/specil processing is not fesile her, rithmetic result should sturte t mximum or minimum vlue tht cn e represented. Thus for 8-it 8 representtion: = 255 New multimedi opertions require dditionl chnges 26