ON THE REUSE OF RTL ASSERTIONS IN SYSTEMC TLM VERIFICATION

Transcription

1 ON THE REUSE OF RTL ASSERTIONS IN SYSTEMC TLM VERIFICATION Nicola Bombieri 1,2 Franco Fummi 1,2, Graziano Pravadelli 1,2, Valerio Garnieri 1, Francesco Stefanni 1, Tara Ghasempouri 2, Michele Lora 2, Giovanni Auditore 3, Mirella Negro Marcigaglia 3 1 EDALab s.r.l. 2 Dip. Informatica, Università di Verona 3 STMicroelectronics s.r.l.

2 Mo#va#ons RTL IP reuse in SystemC TLM pla6orms SystemC and TLM SystemC is the de- facto reference standard language for design and of Embedded Systems at system level level Modeling is the key paradigm for design and at high levels RTL IP reuse Libraries of RTL IPs are available today, already stressed and verified RTL IPs are mainly implemented in Hardware Language (HDL), such as VHDL or Verilog Design teams cannot oken maintain double and equivalent of IPs (RTL and TLM) IP models oken undergo manual for Today, actually, are done at RTL over and already verified IPs are expensive Automa7c RTL- TLM abstrac7on

3 Mo#va#ons (contd.) IP aker tools for RTL- TLM methodologies for verifying: The abstracted TLM IP model The TLM IP correct based (ABV) What about exis#ng RTL IP asser#ons? CPU TLM IP (SystemC) RTL- TLM (Carbon Design, HIFSuite A2T) RTL IP (VHDL, Verilog) Bus/NoC MEM RTL IP and libraries TLM pla6orm (SystemC) SystemC wrapper Checkers (C++) synthesis (IBM FoCs) TLM (ex- novo 3

4 Goal: RTL reuse in SystemC TLM pla6orms CPU MEM TLM pla6orm (SystemC) With the aim of: TLM IP RTL- TLM (Carbon Design, HIFSuite A2T) RTL IP (VHDL, Verilog) Bus/NoC Checkers (C++) synthesis and (Proposed approach) RTL IP and libraries SystemC wrapper Checkers (C++) synthesis (IBM FoCs) TLM (ex- novo What happens to the TLM performance? 1. Avoid error- consuming re- 2. Reuse effort spent at RTL (for RTL 4

5 Limits of related work: based in SystemC TLM ABV in SystemC TLM: [Habibi- IEEE Trans.VLSI 06] First for cycle- accurate TLM [Ecker- IEEE ICCD 06,MEMOCODE 06,DATE 07] Proposal of specific language for SystemC TLM [Lahbib- IEEE DTIS 06] IBM FoCs synthesis into SystemC TLM of checkers for ABV in SystemC TLM: [Ferro- IEEE IDTL 08,FDL 09] Formal tools for ABV in SystemC TLM: [Grosse- IEEE MEMOCODE 10] TLM reuse at RTL [Bombieri- IEEE DATE 07, Kasuya- DAC 07, Pierre- CODES 13] No work for reusing RTL assertions in SystemC TLM 5

6 Methodology: genera7on of checkers from asser7ons and integra7on in the TLM model Two ways: 1. of HDL checkers, and PSL RTL 1 of HDL checkers Checker #1 RTL IP model Checker #2 3 RTL- to- TLM abstrac@on TLM IP model with integrated checkers 2 Checker integra@on 2. Genera@on of C++ checkers, abstrac@on, and integra@on PSL RTL asser@ons 1 Genera@on of C++ checkers RTL IP model 2 RTL- to- TLM abstrac@on 3 cp 1 cp 2 TLM IP model with integrated checkers Checker integra@on 6

7 2: Automa#c RTL- to- TLM abstrac#on of IPs in1 in2 Rising edge (δ- cycle 0) Scheduling: ps 1, ps 2, ps 3, ps 4 Execu@on: ps 1, ps 2, ps 3, ps 4 sig1 ps 1 pa 1 sig2 sig3 ps 2 Clock Cycle i (δ- cycle 1) Falling edge (δ- cycle 0) Scheduling: pa 1 Execu@on: pa 1 How the HDL scheduling works ps 3 RTL model Synchronous process ps 4 out2 Asynchronous process Clock Cycle i+1 Rising edge (δ- cycle 0) (δ- cycle 1) Falling edge (δ- cycle 0) Scheduling: ps 1, ps 2, ps 3, ps 4 Execu@on: ps 1, ps 2, ps 3, ps 4 Scheduling: pa 1 Execu@on: pa 1 How the TLM scheduling works Synchronous func@on Asynchronous func@on fa1() fs4() fs3() fs2() fs1() scheduler{ rising_edge(); while(events_triggered) { delta_cycle(); } falling_edge(); while(events_triggered) { delta_cycle(); } TLM model 7

8 1. Genera#on of C++ checkers Example of RTL assertion: An input A or B high is always followed by output C high - - psl P1: assert always A or B - > next C@(clk event and clk= 1 ); A B C if then if then if then Generally clocked asser@ons clk P1(){ } Checker invoca@ons 8

9 3: C++ checkers integra#on in the TLM model TLM model fs4() fa1() P1() P2() fs3() fs2() fs1() scheduler{ rising_edge(); while(events_triggered) { delta_cycle(); } falling_edge(); while(events_triggered) { delta_cycle(); } PSL asser@ons Genera@on of C++ checkers P1() P2() C++ checkers Integra@on of checkers consuming than HDL checkers integra@on Less overhead introduced than HDL checkers 9

10 Some experimental results: 10

11 Some experimental results IP model Checkers (#) RTL (s) Overhead (%) TLM (s) Overhead (%)2 Speedup (x) 0 24,19-11,61-2,08 UART 2 54,69 126,13 23,71 104,22 2, ,71 976,42 458, ,64 1, ,75-19,94-1,14 Root 2 97,44 328,32 37,00 85,55 2, , , , ,79 1, ,03-20,79-2,21 Div 2 125,43 172,51 23,05 10,87 5, , ,61 665, ,44 2, ,59-18,57-5,69 FDCT 2 209,65 98,55 34,58 86,24 6, ,88 973, , ,75 2, ,54-12,09-7,82 QNR 2 202,46 114,15 25,45 110,57 7, ,55 942,43 950, ,83 2, ,12-12,99-7,40 RLE 2 219,80 128,66 28,19 117,12 7, ,52 904,35 985, ,25 2, ,83-42,02-7,33 JPEG 2 622,94 102,37 82,96 97,42 7, ,01 904, , ,47 2, ,56-34,77-5,68 Error_corr ,73 95,76 70,02 101,38 5, ,00 926, , ,47 1, ,54-69,13-7,05 Lambda_err 2 791,15 62,27 121,79 76,18 6, ,19 836, , ,69 2, ,54-80,94-6,02 Omega- phy 2 935,10 Design 91,80 Automa@on 144,80 Conference (DAC) 78,91-6,46 June 6th ,88 856, , ,53 2,25 11

12 Conclusions Key idea of the proposed method: to recover RTL IP and make them suitable for ABV in SystemC TLM pla6orms Main a two steps methodology A checker generator is adopted to automa@cally generate checkers from exis@ng RTL asser@ons Checkers are integrated in the TLM IP models Observed results: The overhead introduced by asser@ons (checkers) automa@cally generated through the proposed approach is comparable to the overhead introduced by asser@ons (checkers) manually defined. The best results have been obtained with a limited number of asser@ons checked at TLM (10-15 per IP). More details and results offline. Thank you! 12