JL Gray July 30, 2008
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1 Santa Claus, the Tooth Fairy and SystemVerilog Interoperability JL Gray July 30,
2 2 Agenda Intro Looking Back: 1998 Present Methodology and Simulator Incompatibility Comparing the VMM and OVM Moving Forward
3 3 Agenda Intro Looking Back: 1998 Present Methodology and Simulator Incompatibility Comparing the VMM and OVM Moving Forward
4 4 Who is this guy, anyways? Associate Principal, Verilab, Inc. Author, Cool Verification Built testbenches for 8 different companies on 11 different projects over the last 8 years e, Vera, SystemC, SystemVerilog erm, SCV, VMM, OVM
5 5 Enquiring Minds Want To Know Interoperability
6 6 Lack of Interoperability Within Teams Within Companies Between Companies Between Simulators Between Methodologies
7 7 Why is Interoperability an Issue? Design complexity has increased Teams are geographically dispersed Difficult to verify complex chips without taking advantage of third party verification IP Without interoperability, difficult to deal with all of the above!
8 8 Agenda Intro Looking Back: 1998 Present Methodology and Simulator Incompatibility Comparing the VMM and OVM Moving Forward
9 9 Looking Back Testbenches written in Verilog, VHDL, or C No industry standard methodologies Verilog spec unclear - support not necessarily standardized between simulators But, chips were simpler 1996 Motorola StarTAC ( e:motorolastartac.jpg)
10 10 Moving Ahead Specman/e and Vera were adopted SystemVerilog on the horizon Standard verification methodologies under development Constrained random, coverage driven verification all the rage!
11 The Gathering Storm Many languages e Vera SystemC SystemVerilog Many methodologies erm RVM TLM VMM AVM URM SVM Much confusion!
12 12 Today Still many languages Simulators still incompatible Still many methodologies but... Some methodologies converging Some going head to head! Next up Simulator incompatibility
13 13 Agenda Intro Looking Back: 1998 Present Methodology and Simulator Incompatibility Comparing the VMM and OVM Moving Forward
14 14 What Common Language? No common language support Libraries don t run on all simulators Why bother with SV? Still disagreements on methodology
15 15 Simulator Incompatibility Examples Parameterizable classes Supported functional coverage constructs List support (including randomization) Random generation Function calls in constraints Task calls in functions Tool specific bugs Support for packages Next up Methodology incompatibilities and convergence
16 16 Methodology Incompatibility Simulation phases Layered stimulus generation Runtime configuration Test generation Communication infrastructure Logging Coverage Collection Exception Handling Use Model
17 17 Methodology Convergence AVM (TLM) OVM VMM RVM URM (erm)
18 18 Agenda Intro Looking Back: 1998 Present Methodology and Simulator Incompatibility Comparing the VMM and OVM Moving Forward
19 19 Logging (1/2) What happens when I print a message from a VMM component in an OVM testbench? What about error severity levels? How do you throttle the severity of messages? How do you extend the functionality of error reporting? Via Callbacks? June 9, 2008
20 20 Logging (2/2) OVM ovm_report_info(get_type_name(), Hello! ) `message(ovm_low, ( My message! )) VMM `vmm_note(env.log, "Interrupt asserted!");
21 21 Runtime Configuration (1/2) module top my_env topenv A inst1 C u1 C u2 B inst2 C u1
![22 Runtime Configuration (2/2) OVM set_config_string("*", "myaa[bar]", "bye"); set_config_string("*", "myaa[foo]", "hi"); VMM topenv.inst1.u1.myaa["foo"] = "hi"; topenv.inst1.u2.](/docs-images/87/95740491/images/22-2.jpg "myaa[\"foo\"] = \"hi\"; topenv.inst2.u1.myaa[\"foo\"] = \"hi\"; topenv.inst1.u1.myaa[\"bar\"] = \"bye\"; topenv.inst1.u2.myaa[\"bar\"] = \"bye\"; topenv.inst2.u1.myaa[\"bar\"] = \"bye\"; Of course, you d probably pass these around as a single object in both methodologies")
22 22 Runtime Configuration (2/2) OVM set_config_string("*", "myaa[bar]", "bye"); set_config_string("*", "myaa[foo]", "hi"); VMM topenv.inst1.u1.myaa["foo"] = "hi"; topenv.inst1.u2.myaa["foo"] = "hi"; topenv.inst2.u1.myaa["foo"] = "hi"; topenv.inst1.u1.myaa["bar"] = "bye"; topenv.inst1.u2.myaa["bar"] = "bye"; topenv.inst2.u1.myaa["bar"] = "bye"; Of course, you d probably pass these around as a single object in both methodologies
23 24 Agenda Intro Looking Back: 1998 Present Methodology and Simulator Incompatibility Comparing the VMM and OVM Moving Forward
24 25 What Engineers Want Compatibility of VIP Code and libraries that run on all simulators Long term stability Performance Motherhood and Apple Pie!
25 26 How to get there Open Source - Let the market decide Accellera - Force the vendors to agree Vendor driven vs. User driven
26 27 Elephant in the Room Simulators do not support the same SV language constructs! Even if a methodology existed that worked on all major simulators, there may be other issues
27 28 Dealing With Disparate Methodologies Pick one Manual Conversion Some harder than others! Wrapper Communication via API
28 29 Accellera Goals Short term Interoperability between VMM and the OVM? Long term Common standard (like the C++ STL)? Include support for other languages like e and SystemC?
29 30 In Summary My View Need standard for VIP communication Think financial transactions, web API Proprietary can also be a de facto standard (think Microsoft Office) Shouldn t force use of a common language Different problems benefit from different languages However, cost concerns may force the issue Testbenches of the future will include components from many different sources
30 31 And the verdict is Interoperability
31 32 How to get involved Accellera OVM World VMM Central
32 34 QUESTIONS?
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