A SystemC HDL Cosimulation Framework

Transcription

1 A SystemC HDL Cosimulation Framework Christian Bernard, CEA/LETI Nicolas Tribié, CEA/LETI Marcello Coppolla, ST/AST A systemc HDL cosimulation framework 1

2 Agenda Motivatio Cosimulation usages Framework Architecture C++ Code Generation Example : Performances Achieved Future Improvements Q & A A systemc HDL cosimulation framework 2

3 Motivatio Introduce SystemC for system-level specification, Lack of SystemC synthesis tools : RTL description still in /Verilog Validation : Check RTL / SystemC conformance. Simulation speed up : Testbench described at traaction level (SystemC) Need for a tool allowing cosimulation : Low cost (SystemC is free!), focus on cosimulation only Compatible with main RTL simulators (Modelsim, NCSim..) Minimize user-written additional code A systemc HDL cosimulation framework 3

4 Usage example Memory Controller Designer s view Focus on the memory controller implemented down to RTL using. Others modules are still described at traaction level Simulation speed up Testbench can be written in SystemC Eases developpement Benefits from C++ Easy to maintain & reuse CPU ISS eram Peripherals Bridge Video Decoder Bridge I/Os DSP ISS Traport I/F MEM CTRL RTL DDRAM SoC TestBench A systemc HDL cosimulation framework 4

5 Cosimulation Principles Assumptio : ASIC hierarchy described in / Verilog SystemC Hierarchy description is also possible Blocks described in SystemC are replaced by a image in the hierarchy Clocks are replicated both in the HDL simulator and SystemC scheduler Several clocks domai are allowed Restrictio : Blocks interfaces must be synchronous to a global clock Delta cycles are not supported Only one exchange between and SystemC models at each cycle No delays in combinatorial logic of the simulated RTL A systemc HDL cosimulation framework 5

6 SystemC blocks in a hierarchy Video Decoder Traport I/F TestBench Scheduler Cosimulation Interface CPU ISS eram Peripherals Bridge Video Decoder Bridge I/Os DSP ISS Traport I/F / Verilog Simulator MEM CTRL RTL SoC TestBench image A systemc HDL cosimulation framework 6

7 blocks in a SystemC hierarchy CPU ISS eram Peripherals Bridge Video Decoder SystemC Bridge I/Os DSP ISS Traport I/F SystemC MEM CTRL Cosimulation Interface Video Decoder I/F Traport Video Decoder RTL Traport I/F RTL SoC TestBench Scheduler / Verilog Simulator A systemc HDL cosimulation framework 7

8 Architecture Module A Module B Module C Module D Module A Module B Module C Module D Other Modules RTL Traaction Traaction Traaction Traaction / Verilog Simulator Cycle-based Clk1 Cycle-based Cycle-based Clk2 Cycle-based Cadence TestBuilder Library Clk1 Clk2 Shared memory driver UNIX shared memory Shared memory driver Libraries / Scheduler SystemC world HDL RTL world A systemc HDL cosimulation framework 8

9 Communication Flow SystemC simulation clock event HDL simulation clock event SystemC Clock domain master events Module Module Module Module Module Module Module Module Clock domain master SystemC-HDL sim Rendez-Vous Post signal values Get new signals values Shared memory Shared Shared Semaphores Data Shared Data structures Data structures structures Post signal values SystemC-HDL sim Rendez-Vous A systemc HDL cosimulation framework 9

10 C++ Code Generation Module A Module B Module C Module D TOP Level RTL Traaction Cycle-based Traaction Cycle-based Traaction Cycle-based Traaction Cycle-based Module A Module B Module C Module D / Verilog Simulator Other Modules RTL Cosimulation specific code is automatically generated Cadence TestBuilder Library Shared memory driver UNIX shared memory Shared memory driver Libraries / Scheduler SystemC world HDL RTL world A systemc HDL cosimulation framework 10

11 Design Database (HDL RTL) Browsing script script Toplevel Config file Code Generation Flow Modules Modules Modules RTL RTL RTL HDL HDL Parsing Parsing Script Script Shared signals tree Shared clocks list Shared modules tree SystemC Code Generator TestBuilder Code generator SystemC Code SystemC Code TestBuilder Code Shared Memory comm comm comm comm comm Shared Memory Data Structs. Shared Memory Data Structs. Shared Memory comm comm comm comm Modules s A systemc HDL cosimulation framework 11

12 Simple example 1/3 Example adapted from Synopsys s «simple_bus» SystemC model: A bus shared by N masters is described at traaction level Some masters perform blocking trafers Some others perform nonblocking trafers (polling) Three memories can be accessed as slaves One of them is described in RTL 1 2 N Simple Bus (SystemC channel) Arbiter Memory 1 (ROM) (traaction-cycle) RAM RTL Model Memory 3 (Flash) A systemc HDL cosimulation framework 12

13 Simple example 2/3 1 2 N Simple Bus (SystemC channel) Arbiter Memor y 1 (ROM) (traaction-cycle) RAM RTL Model Memor y 3 (Flash) mananbolo:output[352] time./systemc_cosim mananbolo:output[352] time./systemc_cosim SystemC Oct :00:44 Copyright SystemC (c) Oct by 29 all 2001 Contributors 10:00:44 Copyright ALL (c) RIGHTS RESERVED by all Contributors top.bus Registering ALL RIGHTS master RESERVED Nb 0 top.bus top.bus Registering Registering master master Nb Nb 1 0 top.bus top.bus Registering Registering master master Nb Nb 2 1 top.bus Registering master Nb 2 top.master_b_0 traaction : top.master_b_0 top.master_b_0 traaction traaction : : top.master_b_1 top.master_b_0 traaction traaction : : top.master_b_2 top.master_b_1 traaction traaction : : top.master_b_3 top.master_b_2 traaction traaction : : top.master_b_4 top.master_b_3 traaction traaction : : top.master_b_5 top.master_b_4 traaction traaction : : top.master_b_5 traaction : A systemc HDL cosimulation framework 13

14 Simple Example : Performances SystemC Only : 18.2 Kcycles / s Systemc : 2.5 Kcycles/s 9x slow-down (To be compared with a full RTL simulation) A systemc HDL cosimulation framework 14

15 Conclusion- Future developments Conclusion : A free tool allowing SystemC cosimulation has been developped Interfaces with main simulators Automated code generation : No additionnal code written by designers Needs to be tested in ur design flow Future directio : Verilog support Decrease the shared memory bandwidth (observe signals activity, synchronize only when required ) Perform SystemC-HDL communicatio at traaction level. Bus s library Integration with Cadence Signalscan to visualize traactio and ease debug A systemc HDL cosimulation framework 15

16 Questio Thank you for your attention.. Contacts : Nicolas.tribie@cea.fr Christian.bernard@cea.fr 17 Av Des Martyrs Grenoble, France A systemc HDL cosimulation framework 16