A mixed signal verification platform to verify I/O designs

Transcription

1 A mixed signal verification platform to verify I/O designs Dan Bernard Dhaval Sejpal 7/14/11

2 Introduction My group at IBM develops high-speed custom I/O interfaces for IBM's server processors. In the past, we used traditional analog simulation approaches for our circuit verification. However, as our interfaces became more complex, there was an increasing need to use mixed-signal approaches to verify the link operation. 2

3 Verification Overview At IBM a combination of software tools check the accuracy of designs. For formal verification, an internal tool called Verity is used to ensure that a schematic matches the corresponding VHD for each design. For VHD functional verification, our group uses an internally developed event simulation tool called Sim_Phy to verify that the logic is performing correctly. For higher level (chip) functional verification, cycle-sim based simulators verify only VHD, requiring it to be provided for all levels of the design. 3

4 Formal Verification imitations Verity establishes equivalence for digital structures, but falls short with analog structures, especially those where the circuits output value is an analog quantity (i.e. a DAC) Approaches available in Verity to correct that limitation involve one of the following: - A manually created replacement model of the analog schematic (usebox) The usebox modeling language is non-standard, and is limited to describing digital structures. Also, the equivalency of the model to the analog structure can not easily be established. - Ignoring the analog structure altogether through a blackbox Both of these methods create a verification coverage gap, which is undesirable 4

5 The Sim_Phy Tool The Sim_Phy tool was designed to provide functional event-sim verification for our logic designs. It utilizes Cadence ncsim as the simulator, and has a custom TC interface to orchestrate the compile/elaboration/simulation of each testcase. ach testcase is comprised of: - A VHD testbench enclosing the design under test, and a SystemC code block. The SystemC block provides stimulus and results checking, and can execute any desired testcase to cover the breadth of the design function. 5

6 Sim_Phy Testcase Structure VHD Top (Testbench) SystemC Block Testcases Stimulus TX (VHD) Sub-Phy Block (VHD) Sub-Block (VHD) esults Checking X (VHD) Sub-Phy Block (VHD) Sub-Block Under Test (VHD) 6

7 Need For nhanced Verification These two verification methods fell short when faced with increasingly complex interfaces containing channel equalization. These interfaces required interactions between digital state-machines and analog channel equalization circuits (i.e. DF) to achieve successful operation. Therefor a mixed signal approach was required to meet this challenge. 7

8 Approach To nhanced Verification To address these shortcomings we chose a targeted mixed-signal approach, covering only those structures that were unable to be verified by either the formal method (Verity) or the event-sim method (Sim_Phy). These structures would then be covered by behavioral models. With this targeted approach, model counts were minimized, and the existing verification infrastructure could be reused with some enhancement. The required behavioral models were written by the circuit designers in Verilog-A/AMS and tested in an AD testbench prior to release. These models were then pulled into the Sim_Phy compilation flow; where they selectively replaced existing VHD code. The model swap method utilized was compilation control; where the elaborator was forced to bind with the Verilog models due to the removal of the original VHD code. 8

9 Sim_Phy Testcase Structure With Swapped AMS Model VHD Top (Testbench) SystemC Block Testcases Stimulus TX (VHD) Sub-Phy Block (VHD) Sub-Block (VHD) esults Checking X (VHD) Sub-Phy Block (VHD) Sub-Block Under Test (Verilog-A/AMS) 9

10 Implementation Challenges anguage Training: With the circuit designers writing the behavioral models, training from Cadence was obtained for all circuit designers. This led to a long ramp-up as designers gradually became familiar with Verilog-A/AMS modeling. Custom VHD types: When replacing existing VHD with behavioral models, VHD wrappers were required between the logic side and the Verilog layer to allow for the elaboration of pins using custom VHD types (power pins). These wrapper files were generated by scripts, then later hand maintained as logic and schematic designs evolved. Hierarchical Separation of Models: Due to the requirement of the VHD top-level testbench, efforts were made to place analog structures adjacent to one another in the hierarchy as much as possible to minimize analog signals traversing the VHD. However in certain areas this was unavoidable and required the use of real signal routing 10

11 Implementation Challenges: eal Signal outing In VHD designs, ports are typically designated as type std_ulogic This is acceptable for mixed-signal uses where the digital edge is all that is required, and a 2 connect module can provide the required electrical connection to a behavioral model. To provide a real port to the behavioral model, and yet also maintain compatibility with logic simulation, a technique was required. A VHD package was written, that defined a subtype real_net as std_ulogic. In VHD where a real signal needed to be routed; the port type real_net was used instead of std_ulogic. A second VHD package was also written where the subtype real_net was defined as real. Thus by selectively compiling one of the VHD packages, the nets defined as real_net could be toggled between std_ulogic and real anywhere in the design. This method allowed hierarchically separated behavioral models, to be connected by a real port through VHD hierarchy. 11

12 Modeling anguage Selection Initial research indicated that Verilog-AMS provided the best capability to mix the simulation advantages of inherently digital portions of a model, with the ability to describe purely analog operation as well. From a circuit designer perspective however, Verilog-A had the benefit of being directly simulated by Spectre, along with a continuous modeling approach that more closely mimicked analog circuit operation. Using either modeling language with electrical pins however, drives the automatic insertion of either 2, or 2 connect modules. 12

13 Design xample: X Side Data_p Data_n Channel Model Pre- Amp Dp Dn Vhdl eal Control signals Control signals c2_0_p c2_0_n c2_90_p c2_90_n Phase ot c2r_0_p c2r_0_n c2r_90_p c2r_90_n Clk Buffer c2_00 c2_00b c2_90 c2_90b S a m p l e r D e s e r Data To MS (synthesized digital logic) Control signals Func Dacs Vhdl eal Control signals Diag Dacs Vhdl eal 13

14 Modeling Approach 1: Models With lectrical Ports Verilog-AMS Data_p Data_n Channel Model Pre-Amp Vhdl eal Samplat Data_out Verilog-A Verilog-A Vhdl eal Control Signals DAC Verilog-AMS 14

15 esults: Models With lectrical Ports The full Sim_Phy testcase of which a portion was shown, results in the use of 296 connect modules to convert between electrical/logic, and electrical/wreal port types. From a simulation time perspective, it required over an hour to execute a testcase sequence of roughly 26us. This was deemed far too long to be useful by our verification team. - Several runtime assessments pointed toward the connect modules as taking a disproportionate amount of the simulation time. This seemed to be due to the large number of analog time points required to track the analog waveforms. A tradeoff was observed between runtime and accuracy for the connect modules. Turning down the accuracy, resulted in some runtime improvement. But the resulting reduced accuracy was not acceptable. 15

16 Modeling Approach 2: Models With Wreal Ports During the runtime assessments, it was discovered that simulation speed could be greatly improved on several of the models, simply by changing their port types to wreal, and thus eliminating the connect modules. This method resulted in simulation speedups for the DAC, and sample latch; with the latter resulting in the greatest speedup due to the large number of switching events in the testcase. These successes led us to consider adopting real value modeling for the other more analog models in the design, and thus improve their performance and accuracy. The Preamp required a fundamental re-write for real modeling. At issue was the use of a Verilog-A channel model, that needed to be converted to a discrete time model. 16

17 Modeling Approach 2: Models With Wreal Ports Verilog-AMS eal Data_p Data_n Channel Model Pre-Amp Vhdl eal Samplat Data_out Verilog-AMS eal Verilog-AMS eal Vhdl eal Control Signals DAC Verilog-AMS eal 17

18 untime esults Summary Phaserot Samplat Dac Channel and Preamp Models Connect Modules Sim Time(us) lapsed Time(s) us/hr (*) AMS Digital AMS lectrical AMS lectrical AMS lectrical AMS Digital AMS Wreal AMS Wreal AMS Wreal * Test Setup: 3GHz Intel Xeon (4-core), H5; Incisiv 9.2, AMS Spectre Moving to real value modeling resulted in a ~10x runtime improvement 18

19 Conclusion In conclusion, the mixed-signal enhancement to our verification methodology has enabled a more complete functional verification of our I/O designs and helped us to achieve better design quality. With the real value modeling improvements, we are seeing a simulation speedup of about 10x over the original electrical port models. The real value modeling approach provides the necessary simulation speedup, and does not compromise on the accuracy required for functional verification. 19