DIGITAL SYSTEM DESIGN & DIGITAL IC APPLICATIONS UNIT-I DIGITAL DESIGN USING HDL

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1 DIGITAL SYSTEM DESIGN & DIGITAL IC APPLICATIONS UNIT-I DIGITAL DESIGN USING HDL 1) What are the Basic steps involved in the Designing of Digital System? Ans) Basic steps involved in the Designing of Digital System are: Specify the Desired behavior of the circuit. Synthesize the Circuit. Implement the Circuit. Test the Circuit to check whether the desired specifications meet. By the increase in size and complexity digital systems, they can t be designed manually. So CAD (Computer Aided Design) tools are used. 2) Explain in detailed about HDL based Design flow (Or) What is HDL? Why do you need it Ans) Hardware Description Languages: HDLs are used to describe the hardware for the purpose of modeling, simulation, testing, design, and documentation. Modeling: behavior, flow of data, structure Simulation: verification and test Design: synthesis Two widely-used HDLs today VHDL: VHSIC (Very High Speed Integrated Circuit ) Hardware Description Language Verilog : HDL based Design flow: Figure 1.1 VHDL Design flow The first four blocks are called Front-end process, remaining blocks are called back-end process. Block Diagram: It obtains basic approach of the system. Coding: It includes writing VHDL code for Hierarchical model. Any text editor can be used to write HDL code. By the following reasons we use specialized text editor. 1

2 HDL keywords are highlighted easily. Have built-in templates for frequency used program structure. Built-in syntax checking. Compiler can be accessed using single click. Compilation: During this syntax errors are detected and code is checked for compatibility with other modules. Simulation: It is a part of verification. The purpose is to verify that the circuit works as desired. i.e it describes the behavior of the circuit in terms of i/p and o/p signals. The operation of digital circuits can be verified fastly and accurately using logic simulation. We have two types of verification techniques Functional and Timing. When all functions of circuit are verified then it is referred as Functional simulation. When there is involvement of timing behavior of the circuit by including estimated delays, it is referred as Timing simulation. Synthesis: It is task of designing a digital system that implements a desired functional behavior. Simply it is the process of generating a logic diagram from a truth table. For performing this process automatically CAD tools are available. HDL program is input to the synthesis compiler. When HDL code passed through initial synthesis tool a lower level description of the circuit is generated as output. The task of synthesis tool to manipulate user s design to produce equivalent or better circuit Figure 1.2 Relation between Simulation and synthesis automatically called logic synthesis or logic optimization. In this process a list of components and their interconnections is derived from model of digital system described by HDL, is called netlist. 2

3 Fitting/ place + route : It uses fitting tool or fitter. This tool uses available device resources and maps synthesized components with resource devices. By using routing signals through Switch matrix or other interconnects in FPGA interconnections are made. Timing verification : It is the last step in HDL based design flow. In this state the Actual circuit delays due to wire lengths, electrical loads and other factors can be calculated with reasonable precision. 3) Discuss about some features of VHDL? Ans) VHDL Introduction: IEEE is the Institute of Electrical and Electronics Engineers The reference manual is called IEEE VHDL Language Reference Manual Draft Standard version 1076/B It was ratified in December 1987 as IEEE Note: The VHDL is standardized for system specification, But not for design VHDL is an acronym for VHSIC Hardware Description Language, where VHSIC is Very High Speed Integrated Circuit. VHDL Features: VHDL has powerful constructs. VHDL handles asynchronous as well as synchronous sequential circuits. In VHDL concurrency, timing and clocking can all be modeled. In VHDL, design is target independent. VHDL supports design library. VHDL is not case sensitive.(ex. = begin = begin) In VHDL simulation of logical operation and timing behavior of a design is possible. 4) Explain about the Structure of VHDL? Ans) VHDL structure has two parts. They are Entity: it is the Declaration of inputs and outputs signals to the external circuitry Architecture: It Specifies behavior, functionality, relation between inputs and outputs. Note: Architecture contains only Concurrent statements Figure 1.3 VHDL structure VHDL TERMS: Entity: All designs are expressed in terms of entities Basic building block in a design 3

4 Ports: Provide the mechanism for a device to communication with its environment Define the names, types, directions, and possible default values for the signals in a component's interface Architecture: All entities have an architectural description Describes the behavior of the entity A single entity can have multiple architectures (behavioral, structural, etc) Configuration: A configuration statement is used to bind a component instance to an entityarchitecture pair. Describes which behavior to use for each entity Generic: A parameter that passes information to an entity Example: for a gate-level model with rise and fall delay, values for the rise and fall delays passed as generics Process: Basic unit of execution in VHDL All operations in a VHDL description are broken into single or multiple processes Statements inside a process are processed sequentially Package: A collection of common declarations, constants, and/or subprograms to entities and architectures. Attribute: Data attached to VHDL objects or predefined data about VHDL objects Examples: maximum operation temperature of a device Current drive capability of a buffer ENTITY: In VHDL, the name of the system is the same as the name of its entity. Entity comprises two parts: o parameters of the system as seen from outside such as bus-width of a processor or max clock frequency o connections which are transferring information to and from the system (system s inputs and outputs) All parameters are declared as generics and are passed on to the body of the system Connections, which carry data to and from the system, are called ports. They form the second part of the entity. Figure 1.4 VHDL overall structure 4

5 Syntax: Entity Entity_Name is port ( Signal_name: mode signal_type; Signal_name: mode signal_type; Signal_name:modesignal_type); end Entity_Name; Example: Entity AND_GATE is port ( A: in std_logic; B: in bit; C: out std_logic); end AND_GATE; Architecture: Architecture body can specify in following modeling styles based on statement assignment Behavior: Assignment of sequential statements Dataflow: Assignment of Concurrent statements Structural: Assignment of component statements Combination of above three models. Architecture Syntax: Architecture Architecture_name of Entity_Name is Declarations; begin Concurrent statements; end Architecture_name; 5) Explain the modeling styles present in VHDL with suitable examples.? Ans) Architecture: Architecture body can specify in following modeling styles based on statement assignment Behavior: Assignment of sequential statements Dataflow: Assignment of Concurrent statements Structural: Assignment of component statements Combination of above three models. Behavioral Description Behavioral o High level, algorithmic, sequential execution o Hard to synthesize o Easy to write and understand (like high-level language code) 5

6 Example: Architecture Behavioral of AND_GATE is begin Process (A,B) begin If A= 1 and B= 1 then c <= 1 ; Else c<= 0 ; End if; End Process; End Behavioral; Dataflow Description Dataflow o Medium level, register-to-register transfers, concurrent execution o Easy to synthesize o Harder to write and understand (like assembly code) Example: Architecture Dataflow of AND_GATE is begin c<= A and B; End Dataflow; Structural Description Structural o Low level, net list, component instantiations and wiring o Trivial (Easy) to synthesize o Hardest to write and understand (very detailed and low level) Example 1: Architecture STRUCTURAL of AND_GATE is Component AND_GATE port (X, Y : in std_logic; Z : out std_logic); end Component; begin U1 : AND_GATE port map (X => A, Y => B, Z => C ); (or) U1 : AND_GATE port map ( A,B,C); end STRUCTURAL; 6

7 Example 2: Figure 1.5 Logic diagram of a perticular Boolean function Architecture Structural of MAJ3 is Component AND2 PORT( I1, I2: in BIT; O: out BIT); end Component ; Component OR3 PORT( I1, I2, I3: in BIT; O: out BIT); end Component ; SIGNAL A1, A2, A3: BIT; begin g1: AND2 PORT MAP (X(0), X(1), A1); g2: AND2 PORT MAP (X(0), X(2), A2); g3: AND2 PORT MAP (X(1), X(2), A3); g4: OR3 PORT MAP (A1, A2, A3, Z); end Structural; NOTE: A system (an entity) can be specified with different architectures 6) Write short notes on VHDL Design Libraries? Ans) VHDL supports the use of design libraries for categorizing components or utilities. Applications of libraries include Sharing of components between designers Grouping components of standard logic families Categorizing special-purpose utilities such as subprograms or types Two Types of Libraries Working Library (WORK) {A Predefined library into which a Design Unit is Placed after Compilation.}, Resource Libraries {Contain design units that can be referenced within the design unit being compiled}. Only one library can be the Working library Any number of Resource Libraries may be used by a Design Entity There is a number of predefined Resource Libraries The Library clause is used to make a given library visible The Use clause causes Package Declarations within a Library to be visible Library management tasks, e.g. Creation or Deletion, are not part of the VHDL Language Standard Tool Dependent 7

8 Exiting libraries STD Library o Contains the STANDARD and TEXTIO packages o Contains all the standard types & utilities o Visible to all designs WORK library o Root library for the user IEEE library Contains VHDL-related standards Contains the std_logic_1164 (IEEE ) package o Defines a nine values logic system o De Facto Standard for all Synthesis Tools To make a library visible to a design LIBRARY library_name; The following statement is assumed by all designs LIBRARY WORK; To use the std_logic_1164 package LIBRARY IEEE; USE IEEE.std_logic_1164. ALL; By default, every design unit is assumed to contain the following declarations: LIBRARY STD, work ; USE STD. Standard. All ; 7) Write short notes on VHDL Packages with suitable examples? Ans) A package is a common storage area used to hold data to be shared among a number of entities. Packages can encapsulate subprograms to be shared. A package consists of o Declaration section o Body section The package declaration section contains subprogram declarations, not bodies. The package body contains the subprograms bodies. The package declaration defines the interface for the package. All items declared in the package declaration section are visible to any design unit that uses the package. A package is used by the USE clause. The interface to a package consists of any subprograms or deferred constants declared in the package declaration. The subprogram and deferred constant declarations must have a corresponding subprogram body and deferred constant value in the package body. Package body May contain other declarations needed solely within the package body. o Not visible to external design units. Package Declaration: The package declaration section can contain: Subprogram declaration Type, subtype declaration Constant, deferred constant declaration Signal declaration creates a global signal File declaration Alias declaration Component declaration Attribute declaration, a user-defined attribute 8

9 Attribute specification Use clause Package Body: The package body main purpose is Define the values of deferred constants Specify the subprogram bodies for subprograms declared in the package declaration The package body can also contain: Subprogram declaration Subprogram body Type, subtype declaration Constant declaration, which fills in the value for deferred constants File declaration Alias declaration Use clause Existing Packages: Standard Package o Defines primitive types, subtypes, and functions. o e.g. Type Boolean IS (false, true); o e.g. Type Bit is ( 0, 1 ); TEXTIO Package o Defines types, procedures, and functions for standard text I/O from ASCII files. Package Example1: Package simple_gates is COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n2 PORT (i1,i2: IN BIT;o1:OUT BIT);END COMPONENT; COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT; end simple_gates; Use work.simple_gates.all; ENTITY bit_comparator IS PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END bit_comparator; ARCHITECTURE gate_level OF bit_comparator IS FOR ALL : n1 USE ENTITY WORK.inv (single_delay); FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay); FOR ALL : n3 USE ENTITY WORK.nand3 (single_delay); --Intermediate signals SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT; BEGIN -- description of architecture END gate_level; Package Example2: Package Shifters IS Subtype Byte IS Bit_Vector (7 Downto 0); Function SLL (V: Byte; N: Natural; Fill: Bit := 0 ) Return Byte; Function SRL (V: Byte; N: Natural; Fill: Bit := 0 ) Return Byte; Function SLA (V: Byte; N: Natural; Fill: Bit := 0 ) Return Byte; Function SRA (V: Byte; N: Natural) Return Byte; Function RLL (V: Byte; N: Natural) Return Byte; Function RRL (V: Byte; N: Natural) Return Byte; End Shifters; Package Body Shifters IS 9

10 Function SLL (V: Byte; N: Natural; Fill: Bit) Return Byte is Variable Result: Byte := V; If N >= 8 Then Return (Others => Fill); For I IN 1 To N Loop Result := Result (6 Downto 0) & Fill; End Loop; Return Result; End SLL; End Shifters; USE WORK. Shifters. ALL Architecture Functional of LeftShifter IS Sout <= SLL(Sin, 1, 0 ) After 12 ns; End Functional; 8) What are the different types of objects in VHDL? Explain Something that can hold a value of a given Data Type. VHDL has 3 classes of objects o CONSTANTS Figure 1.6 VHDL Data Objects o VARIABLES o SIGNALS Every object & expression must unambiguously belong to one named Data Type Every object must be Declared. Value of Constants must be specified when declared. Initial values of Variables or Signals may be specified when declared. If not explicitly specified, Initial values of Variables or Signals default to the value of the Left Element in the type range specified in the declaration. Examples: o Constant Rom_Size : Integer := 2**16; o Constant Address_Field : Integer := 7; o Constant Ovfl_Msg : String (1 To 20) := ``Accumulator OverFlow``; o Variable Busy, Active : Boolean := False; o Variable Address : Bit_Vector (0 To Address_Field) := `` ``; o Signal Reset: Bit := `0`; Signal Assignments: Syntax: o Target Signal <= [ Transport ] Waveform ; o Waveform := Waveform_element {, Waveform_element } o Waveform_element := Value_Expression [ After Time_Expression ] Examples: o X <= 0 ; -- Assignment executed After d delay o S <= 1 After 10 ns; o Q <= Transport 1 After 10 ns; o S <= 1 After 5 ns, 0 After 10 ns, 1 After 15 ns; Signal assignment statement o mostly concurrent (within architecture bodies) can be sequential (within process body) Concurrent signal assignments are order independent Sequential signal assignments are order dependent 10

11 Concurrent signal assignments are executed o Once at the beginning of simulation o Any time a signal on the right hand side changes If no Time Delay is explicitly specified, Signal assignment is executed after a d- delay o Delta is a simulation cycle, and not a real time o Delta is used for scheduling o A million deltas do not add to a femto second Signal Attributes: Attributes are named characteristics of an Object (or Type) which has a value that can be referenced. Signal Attributes o S`Event -- Is TRUE if Signal S has changed. o S`Stable(t)-- Is TRUE if Signal S has not changed for the last ``t`` period. If t=0; it is written as S`Stable o S`Last_Value -- Returns the previous value of S before the last change. o S`Active -- Is TRUE if Signal S has had a transaction in the current simulation cycle. o S`Quiet(t)-- Is TRUE if no transaction has been placed on Signal S for the last ``t`` period. If t=0; it is written as S`Quiet o S`Last_Event -- Returns the amount of time since the last value change on S. 9) Differentiate variables with signals? Ans) S. No Variables Signals 1 Variables are only local and may Signals may be local or global only appear within the body of a process or a subprogram 2 Variable declarations are not allowed in the declarative parts of Signals may not be declared with in the process or subprogram bodies Architecture bodies or blocks 3 A Variable has no hardware correspondence A signal represents a wire or group of wires(bus) 4 Variables have no time dimension Signals have time dimension associated with them 5 Variable assignment occurs A Signal assignment is never instantaneously 6 Variable assignment is always sequential instantaneous(minimum delay) Signal assignment is mostly Concurrent within architecture body and sequential within process body 7 Variables within process body are static, within subprogram are dynamic 8 Variable assignment operator is := Signal assignment operator is <= 10) Discuss Data Types present in VHDL in detailed? A Data Type defines a set of values & a set of operations. VHDL is a strongly-typed Language. Types cannot be mixed in Expressions or in assigning values to Objects in general 11

12 Figure 1.7 VHDL Data types SCALAR DATA TYPES: SYNTAX TYPE Identifier IS Type-Definition Numeric Data Type o Type-Definition is a Range_Constraint as follows o Type-Definition := Range Initial-Value < To DownTo> Final-Value Examples o TYPE address IS RANGE 0 To 127; o TYPE index IS RANGE 7 DownTo 0; o TYPE voltage IS RANGE -0.5 To 5.5; Number formats: Integers have no Decimal Point. Integers may be Signed or Unsigned (e.g ) A Real number must have either a Decimal Point, a -ive Exponent Term (Scientific Notation), or both. Real numbers may be Signed or Unsigned (e.g E-9 1.5E-12 ) Based Numbers: o o o o Numbers Default to Base 10 (Decimal) VHDL Allows Expressing Numbers Using Other Bases Syntax B#nnnn# -- Number nnnn is in Base B Examples 16#DF2# -- Base 16 Integer (HEX) 8#7134# -- Base 8 Integer (OCTAL) 2#10011# -- Base 2 Integer (Binary) 16#65_3EB.37# -- Base 16 REAL (HEX) Predefined Numeric Data Types: INTEGER -- Range is Machine limited but At Least -(2 31-1) To (2 31-1) POSITIVE -- INTEGERS > 0 NATURAL -- INTEGERS >= 0 REAL -- Range is Machine limited Enumeration Data Type: Parenthesized ordered list of literals. o Each may be an identifier or a character literal. o The list elements are separated by commas A Position # is associated with each element in the List Position #`s begin with 0 for the Leftmost Element Variables & Signals of type ENUMERATION will have the leftmost element as their Default (Initial) value unless, otherwise explicitly assigned. Examples o TYPE Color IS ( Red, Orange, Yellow, Green, Blue, Indigo, Violet); 12

13 o TYPE Tri_Level IS ( `0`, `1`, `Z`); o TYPE Bus_Kind IS ( Data, Address, Control); o TYPE state IS ( Init, Xmit, Receive, Wait, Terminal); Predefined Enumerated Data Types TYPE BIT IS ( `0`, `1`) ; TYPE BOOLEAN IS ( False, True) ; TYPE CHARACTER IS (128 ASCII Chars...) ; TYPE Severity_Level IS (Note, Warning, Error, Failure) ; TYPE Std_U_Logic IS ( `U`, -- Uninitialized `X`, -- Forcing Unknown `0`, -- Forcing 0 `1`, -- Forcing 1 `Z`, -- High Impedence `W`, -- Weak Unknown `L`, -- Weak 0 `H`, -- Weak 1 `-`, -- Don`t Care) ; SUBTYPE Std_Logic IS resolved Std_U_Logic ; Physical Data Type: Specifies a Range Constraint, one Base Unit, and 0 or more secondary units. Base unit is indivisible, i.e. no fractional quantities of the Base Units are allowed. Secondary units must be integer multiple of the indivisible Base Unit. Examples TYPE Resistance IS Range 1 To Integer High Units Ohm; -- Base Unit Kohm = 1000 Ohm; -- Secondary Unit Mohm = 1000 Kohm; -- Secondary Unit end Units ; Predefined Physical Data Types Time is the ONLY predefined Physical data type TYPE Time IS Range 0 To 1E20 Units fs; -- Base Unit (Femto Second = 1E-15 Second) ps = 1000 fs; -- Pico_Second ns = 1000 ps; -- Nano_Second us = 1000 ns; -- Micro_Second ms = 1000 us; -- Milli_Second sec = 1000 ms; -- Second min = 60 sec; -- Minuite hr = 60 min; -- Hour end Units ; COMPOSITE DATA TYPES: Arrays Elements of an Array have the same data type Arrays may be Single/Multi - Dimensional Array bounds may be either Constrained or Unconstrained. Constrained Arrays o Array Bounds Are Specified o Syntax: TYPE id Is Array ( Range_Constraint) of Type; Examples 13

14 o TYPE word Is Array ( 0 To 7) of Bit; o TYPE pattern Is Array ( 31 DownTo 0) of Bit; o 2-D Arrays TYPE col Is Range 0 To 255; TYPE row Is Range 0 To 1023; TYPE Mem_Array Is Array (row, col) of Bit; TYPE Memory Is Array (row) of word; Unconstrained Arrays Array Bounds not specified through using the notation RANGE<> Type of each Dimension is specified, but the exact Range and Direction are not Specified. Useful in Interface_Lists Allows Dynamic Sizing of Entities, e.g. Registers. Bounds of Unconstrained Arrays in such entities assume the Actual Array Sizes when wired to the Actual Signals. Example o TYPE Screen Is Array ( Integer Range<>, Integer Range<>) of BIT; Predefined Array Types: Two UNCONSTRAINED Array Types are predefined BIT_VECTOR o TYPE Bit_Vector Is Array ( Natural Range<> ) of Bit; String o TYPE String Is Array ( Positive Range<> ) of Character; Example o SUBTYPE Pixel Is Bit_Vector (7 DownTo 0); 11) Explain about Statements in VHDL with suitable examples? (Or) What is binding? Explain about binding between entity and architecture. Ans) We have three types of statement assignment in VHDL as 1. Sequential Statements 2. Concurrent Statements 3. Component Statements Sequential Statements: Sequential Statements executes one after another as per writing order. Ordering of the statements is important. They must be placed inside a process statement. Variables are only used in these statements. Process statement: It is the main concurrent statement in VHDL code describes the sequential behavior of design. All the statements with in the process are executes sequentially in zero time. It contains Sensitivity List, which is list of signals on which process should execute after changing its state. Only static signal names are allowed in it. Syntax: Process_Label (optional): PROCESS (Sensitivity_List) Process_Declarations; (constants/variables no signals declarations allowed ) Sequential Statements; END Process; Process Types: 14

15 a) Combinational Process Generate a combinational logic. All inputs must be present in sensitivity list. b) Clocked Process Generates a register logic. Input under clock transition may not be included in sensitivity list. IF Statement: It selects sequence of statements for execution based on the value of condition. Syntax: IF condition1 then Sequential statement; ELSIF condition2 then Sequential statement; ELSE Sequential statement; END IF; CASE Statement: It Selects one of the branches for execution based on the values of the expression The expression value must be of a discrete type of a one dimensional array type. Syntax: CASE expression is When choice1 => (statements); End CASE; When choice1 => (statements); When others => (statements) CONCURRENT STATEMENTS: a) Simple assignment statements: A logic or arithmetic expression is called a simple assignment statement. Example: F<= A and B; b) Selected signal assignment: It allows a signal to be assigned to one of multiple values. It begins with a keyword WITH. Example: WITH S select F<= W0 when 0 ; W1 when 1 ; Wn when others; c) Conditional signal assignment: It is similar to Selected signal assignment. Example: F<= w0 when s= 0 ELSE w1; WHEN Statement: WITH Select: Syntax: With expression select 15

16 Target <= Expression1 when choice1, Loop Control: Expression2 when choice2, Expressionn when choicen; Simple Loops Syntax: [Loop_Label:] LOOP statements; End LOOP [Loop_Label]; The Loop_Label is Optional. The exit statement may be used to exit the Loop. It has two possible Forms: exit [Loop_Label]; -- This may be used in an if statement exit [Loop_Label] when condition; FOR Loop Syntax: [Loop_Label]: FOR Loop_Variable in range LOOP statements; End LOOP Loop_Label; WHILE Loop Syntax: [Loop_Label]: WHILE condition LOOP statements; End LOOP Loop_Label; COMPONENT SATEMENTS: The most basic concurrent statement in VHDL is component statement. Syntax: Label: Component_name port map(signal1, signal2,.. signal n); Label: Component_name port map(port1=>signal1, port2=>signal2,.. portn=>signal n); Example: Architecture STRUCTURAL of AND_GATE is Component AND_GATE port (X, Y : in std_logic; Z : out std_logic); end Component; begin U1 : AND_GATE port map (X => A, Y => B, Z => C ); (or) U1 : AND_GATE port map ( A,B,C); end STRUCTURAL; 12) Write short notes on Subprograms? Subprograms consist of functions and procedures. Subprograms are used to o Simplify coding, o Achieve modularity, o Improve readability. 16

17 Functions return values and cannot alter values of their parameters. Procedures used as a statement and can alter values of their parameters. All statements inside a subprogram are sequential. Types of Subprograms o Concurrent o Sequential Concurrent subprograms exist outside of a process or another subprogram. Sequential subprograms exist in a process statement or another subprogram. A procedure exists as a separate statement in architecture or process. A function usually used in assignment statement or expression. 13) Write short notes on Functions and procedures in VHDL? Ans) FUNCTION SPECIFICATION: Name of the parameter Type of the parameter Mode IN is default & only allowed mode Class constant is default o Return type of the function o Local declarations A function body o Must contain at least one return statement o May not contain a wait statement PROCEDURE SPECIFICATION Name of the procedure Formal parameters of the procedure o Class of the parameter optional defaults to constant o o Name of the parameter Mode of the parameter optional defaults to IN o Type of the parameter Local declarations 14) Discuss briefly on Verilog HDL? Ans) o Developed by Gateway Design Automation (1980) Later acquired by Cadence Design(1989) who made it public in 1990 Became a standardized in 1995 by IEEE (Std 1364) regulated by Open Verilog International (OVI) Verilog only has one building block o o o o Example: Module: modules connect through their port similarly as in VHDL Usually there is only one module per file. A top level invokes instances of other modules. Modules can be specified behaviorally or structurally. Behavioral specification defines behavior of digital system Structural specification defines hierarchical interconnection of sub modules Module and1(c,a,b) Output c; Input a,b; Assign c= a & b; Endmodule 17

18 15) Cmopare VHDL with Verilog? Ans) Comparison between VHDL and Verilog: S. No Parameter VHDL Verilog 1 Strong typing Yes No 2 User defined types Yes No 3 Dynamic memory allocation Yes No 4 Physical types Yes No 5 Enumerated types Yes No 6 Records/Structs Yes No 7 Bit (vector) / integer equivalence Partial (by libraries) Yes 8 Subprograms Yes Yes 9 Separate Packaging Yes Packages Yes include files 10 Gate level modeling Yes VITAL Yes Builtin primitives 11 Conditional statements 12 Iteration Yes If-then-else/elsif (priority) Case (mux) Selected assign (mux) Conditional assign (priority) No don t care matching capability Yes Loop while-loop for-loop exit next Yes if-else (priority) case (mux) casex (mux)?: (conditional used in concurrent assignments) Yes repeat for while Example Programs: Example: ALL LOGIC GATES Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Use IEEE STD_LOGIC_ARITH.ALL; Use IEEE STD_LOGIC_UNSIGNED.ALL; Entity GATES is Port ( a : IN STD_LOGIC; b: IN STD_LOGIC; c: OUT STD_LOGIC; sel: IN STD_LOGIC_VECTOR(2 downto 0)); End GATES; Architecture behavioural of GATES is Process(a,b,sel) Case sel is When 000 => c <= a and b; When 001 => c <= a or b; When 010 => c <= not a ; 18

19 When 011 => c <= a nand b; When 100 => c <= a nor b; When 101 => c <= a xor b; When 110 => c <= a xnor b; When others => null ; End Case; End Process; End behavioural; Example: Full adder circuit: Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Entity fulladder is Port ( a,b,c : IN STD_LOGIC; S,C0: OUT STD_LOGIC); End fulladder; Architecture behavioural of GATES is S<= (a xor b) xor c; C0<= (a and b) or (b and c) or (a and c); End behavioural; Example: Full adder circuit (Structural model): Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Entity fulladder is Port ( a,b,c : IN STD_LOGIC; S,C0: OUT STD_LOGIC); End fulladder; Architecture structural of GATES is x1,x2,x3: STD_LOGIC; component xorgate port(a1,a2,a3 : IN STD_LOGIC; y1: OUT STD_LOGIC); end component; component andgate port (b1,b2: IN STD_LOGIC; c1: OUT STD_LOGIC); end component; component orgate port (d1,d2,d3: IN STD_LOGIC; y2: OUT STD_LOGIC); end component; begin U1:xorgate portmap(a1=>a,a2=>b,a3=>c,y1=>s); U2:andgate portmap(b1=>a,b2=>b,c1=>x1); U3:andgate portmap(b1=>b,b2=>c,c1=>x2); U4:andgate portmap(b1=>a,b2=>c,c1=>x3); U5:xorgate portmap(d1=>x1,d2=>x2,d3=>x3,y2=>c0); End structural; 19

20 Example: D-FLIP FLOP Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Use IEEE STD_LOGIC_ARITH.ALL; Use IEEE STD_LOGIC_UNSIGNED.ALL; Entity DFF is Port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din : IN STD_LOGIC; dout : OUT STD_LOGIC ); End DFF; Architecture behavioural of DFF is Process(clk,reset) If(reset= 1 ) then dout <= 0 ; Elsif(clk = 1 and clk event ) then dout <= din; End Process; End behavioural; Example: 3 TO 8 BINARY DECODER Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Use IEEE STD_LOGIC_ARITH.ALL; Use IEEE STD_LOGIC_UNSIGNED.ALL; Entity DECODER is Port ( a: IN STD_LOGIC; x: IN STD_LOGIC_VECTOR(2 downto 0); y: OUT STD_LOGIC_VECTOR(0 to 7)); End DECODER; Architecture behavioural of DECODER is Signal y1: STD_LOGIC_VECTOR(0 to 7); Process(a,x,y1) Case x is When 000 => y1 <= ; When 001 => y1 <= ; When 010 => y1 <= ; When 011 => y1 <= ; When 100 => y1 <= ; When 101 => y1 <= ; When 110 => y1 <= ; When 111 => y1 <= ; When others => y1 <= ; End Case; If a= 1 then y <= y1; Else y <= ; 20

21 End Process; End behavioural; Example: 4 BIT COMPARATOR Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Use IEEE STD_LOGIC_ARITH.ALL; Use IEEE STD_LOGIC_UNSIGNED.ALL; Entity COMPARATOR is Port ( a : IN STD_LOGIC_VECTOR(3 downto 0); b : IN STD_LOGIC_VECTOR(3 downto 0); clk : IN STD_LOGIC; E,G,L : OUT STD_LOGIC ); End COMPARATOR; Architecture behavioural of COMPARATOR is Process(a,b) E <= 0 ; G <= 0 ; L <= 0 ; If a = b then E <= 1 ; If a > b then G <= 1 ; If a < b then L <= 1 ; End Process; End behavioural; Example: ALU Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Use IEEE STD_LOGIC_ARITH.ALL; Use IEEE STD_LOGIC_UNSIGNED.ALL; Entity ALU is Port ( a,b : IN STD_LOGIC_VECTOR(3 downto 0); s: IN STD_LOGIC_VECTOR(3 downto 0); y: OUT STD_LOGIC_VECTOR(3 downto 0)); End ALU; Architecture behavioural of ALU is Signal y1: STD_LOGIC_VECTOR(3 downto 0); Process(a,b,s,y1) Case s is When 0000 => y1 <= not a; 21

22 When 0001 => y1 <= a + b; When 0010 => y1 <= a or b; When 0011 => y1 <= a and b; When 0100 => y1 <= a + 1; When 0101 => y1 <= a nor b; When 0110 => y1 <= a(2 downto 0) & a(3); When 0111 => y1 <= not(a xor b); When 1000 => y1 <= not b; When 1001 => y1 <= a - b; When 1010 => y1 <= a nand b ; When 1011 => y1 <= a - 1; When 1100 => y1 <= b + 1; When 1101 => y1 <= b 1; When 1110 => y1 <= a(0) & a(3 downto 1); When 1111 => y1 <= a xor b; When others => null; End Case; y <= y1; End Process; End behavioural; Example: 8 X 1 MULTIPLEXER Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Use IEEE STD_LOGIC_ARITH.ALL; Use IEEE STD_LOGIC_UNSIGNED.ALL; Entity MUX is Port ( en : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(7 downto 0); x : IN STD_LOGIC_VECTOR(2 downto 0); y : OUT STD_LOGIC ); End MUX; Architecture behavioural of MUX is Signal y1: STD_LOGIC; Process(en,x,din,y1) If (en= 0 ) then y1<= 0 ; Elsif(en= 1 ) then Case x is When 000 => y1 <= din(0) ; When 001 => y1 <= din(1) ; When 010 => y1 <= din(2) ; When 011 => y1 <= din(3) ; When 100 => y1 <= din(4) ; When 101 => y1 <= din(5) ; When 110 => y1 <= din(6) ; When 111 => y1 <= din(7); End Case; 22

23 y<=y1; End Process; End behavioural; Example: 4 BIT COUNTER Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Use IEEE STD_LOGIC_ARITH.ALL; Use IEEE STD_LOGIC_UNSIGNED.ALL; Entity COUNTER is Port ( clk,clr : IN STD_LOGIC; q: OUT STD_LOGIC_VECTOR(3 downto 0)); End COUNTER; Architecture behavioural of COUNTER is Signal q1: STD_LOGIC_VECTOR(3 downto 0); Process (clk,clr,q1) If (clk event and clk= 1 ) then If (clr= 1 ) then q1 <= 0000 ; Else q1 <= q1+1; If(q1 = 1111 ) then q1 <= 0000 ; q <= q1 End Process; End behavioural; Example: DECADE COUNTER Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Use IEEE STD_LOGIC_ARITH.ALL; Use IEEE STD_LOGIC_UNSIGNED.ALL; Entity DCOUNTER is Port ( clk,clr : IN STD_LOGIC; q: OUT STD_LOGIC_VECTOR(3 downto 0)); End DCOUNTER; Architecture behavioural of DCOUNTER is Signal q1: STD_LOGIC_VECTOR(3 downto 0); Process (clk,clr,q1) If (clk event and clk= 1 ) then If (clr= 1 ) then q1 <= 0000 ; Else q1 <= q1+1; 23

24 If (q1 = 1001 ) then q1 <= 0000 ; q <= q1; End Process; End behavioural; Example: SHIFT REGISTER Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Use IEEE STD_LOGIC_ARITH.ALL; Use IEEE STD_LOGIC_UNSIGNED.ALL; Entity SHR is Port ( clk,reset : IN STD_LOGIC; s: IN STD_LOGIC_VECTOR(1 downto 0); d: IN STD_LOGIC_VECTOR(7 downto 0); y: OUT STD_LOGIC_VECTOR(7 downto 0)); End SHR; Architecture behavioural of SHR is Process(clk,reset) If(reset= 1 ) then y <= ; Elsif(clk = 1 and clk event ) then Case s is When 00 => y <= d; When 01 => y <= d(6 downto 0) & 0 ; When 10 => y <= 0 & d(7 downto 1); When others => null; End Case; End Process; End behavioural; Example: UNIVERSAL SHIFT REGISTER Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Use IEEE STD_LOGIC_ARITH.ALL; Entity USHR is Port ( clk,reset : IN STD_LOGIC; s: IN STD_LOGIC_VECTOR(2 downto 0); d: IN STD_LOGIC_VECTOR(7 downto 0); y: OUT STD_LOGIC_VECTOR(7 downto 0)); End USHR; Architecture behavioural of USHR is Process(clk,reset) 24

25 If(reset= 1 ) then y <= ; Elsif(clk = 1 and clk event ) then Case s is When 000 => y <= d; When 001 => y <= d(6 downto 0) & 0 ; When 010 => y <= 0 & d(7 downto 1); When 011 => y <= d(6 downto 0) & d(0); When 100 => y <= d(7) & d(7 downto 1); When 101 => y <= d(6 downto 0) & d(7); When 110 => y <= d(0) & d(7 downto 1); When others => y <= ; End Case; End Process; End behavioural; Example: RAM Library IEEE; Use IEEE STD_LOGIC_1164.ALL; Use IEEE STD_LOGIC_ARITH.ALL; Use IEEE STD_LOGIC_UNSIGNED.ALL; Entity RAM is Port ( addr : IN INTEGER; rd,wr,cs : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(3 downto 0); dout : OUT STD_LOGIC_VECTOR(3 downto 0) ); End RAM; Architecture behavioural of RAM is type memory is array(0 to 15) of STD_LOGIC_VECTOR(3 downto 0); signal mem : memory; Process(cs,rd,wr,addr,din) If cs = 1 then If rd = 1 and wr = 0 then dout <= mem (addr); Elsif rd = 0 and wr = 1 then mem (addr) <= din; Else dout <= 0000 ; End Process; End behavioural; Example: N bit ripple carry adder. library IEEE; use ieee.std_logic_1164.all; entity ripple_carry is generic(n:natural:=4); port( e, f : in std_logic_vector( n1 downto 0); carry_in : in std_logic; S : out std_logic_vector( n1downto 0); 25

26 carry_out : out std_logic); end ripple_carry; architecture RTL of ripple_carry is begin process(e, f, carry_in) variable tempc : std_logic_vector( n downto 0 ); variable P : std_logic_vector( n1 downto 0 ); variable G : std_logic_vector(n1 downto 0 ); begin tempc(0) := carry_in; for i in 0 to n1 loop P(i):=e(i) xor f(i); G(i):=e(i) and f(i); S(i)<= P(i) xor tempc(i); tempc(i+1):=g(i) or (tempc(i) and P(i)); end loop; carry_out <= tempc(n); end process; end RTL; 26