Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips 1

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1 Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen and Krishnendu Chakrabarty Advanced Micro Devices Philips Research Labs Duke University Sunnyvale, CA 9485, USA 5656 AA Eindhoven, The Netherlands Durham, NC 2778, USA Abstract Multiple levels of design hierarchy are common in currentgeneration system-on-chip (SOC) integrated circuits However, most prior work on test access mechanism (TAM) optimization and test scheduling is based on a flattened design hierarchy We investigate hierarchy-aware test infrastructure design, wherein wrapper/tam optimization and test scheduling are carried out for hierarchical SOCs for two practical design scenarios In the first scenario, the wrapper and TAM implementation for the embedded child cores in hierarchical (parent) cores are delivered in a hard form by the core provider In the second scenario, the wrapper and TAM architecture of the child cores embedded in the parent cores are implemented by the system integrator Experimental results are presented for the ITC 2 SOC test benchmarks Introduction The integration of a complete electronic system on a single chip is now commonplace A system-on-chip (SOC) typically integrates a heterogeneous mix of digital logic, embedded memories, and analog blocks To reduce test cost, SOCs are being increasingly tested in a modular fashion, ie, their various design modules are tested separately [, 2] Such an approach is mandatory for embedded non-logic components such as memories and analog modules, as well as for black-boxed third-party cores However, also for other parts of the SOC, modular testing brings advantages, including reduced ATPG complexity and greater test reuse Modular testing uses an on-chip test access infrastructure, which consists of test wrappers and test access mechanisms (TAMs) [] Test wrappers isolate the various modules from their surrounding circuitry during test TAMs transport test stimuli between SOC pins and module terminals, and test responses vice versa Multiple levels of design and test hierarchy in currentgeneration SOCs are quite common A parent core may contain several child cores, which in turn may contain their own embedded ( grandchild ) cores For example, [3, 4] describe SOCs for digital video, where the SOC design is partitioned into chiplets, which in turn consist of embedded cores Despite this, most prior research on SOC testing (unrealistically) assumed that there is no design and test hierarchy, ie, that all cores are at the same hierarchy level [6, 7, 2] Test wrappers, TAMs, and This research was supported in part by the National Science Foundation under grants CCR and CCR-2477 This work was carried out whle Anuja Sehgal was a PhD student at Duke University test schedules designed for non-hierarchical SOCs are typically not valid for SOCs with hierarchical cores The hierarchy imposes a number of constraints on the manner in which tests must be applied to parent cores and their embedded child cores [8]; hierarchy-oblivious methods make no attempt to satisfy these constraints In this paper, we describe a test infrastructure design approach for hierarchical SOCs; our approach is based on hierarchy-aware wrapper design for parent cores, TAM optimization techniques for the SOC and the parent cores, and chip-level test scheduling We consider two different test infrastructure design scenarios In Scenario, we assume that the wrappers and TAM architectures for the child cores are given and fixed (hard), while the wrappers and TAM architectures for the parent cores are to be determined by our approach (soft) In Scenario 2, the wrapper and TAM for both parent and child cores are assumed to be soft The sequel of this paper is organized as follows In Section 2, we review the limitations of prior work In Section 3, we discuss various DfT techniques that can be used to reduce test length Section 4 describes our approach for Scenario, while Section 5 addresses Scenario 2 We derive lower bounds on the test time in Section 6 In Section 7, we present test application times and lower bounds for the ITC 2 SOC test benchmarks [5] Finally, Section 8 concludes the paper 2 Limitations of Prior Work Most prior work on wrapper/tam optimization for SOCs has assumed a non-hierarchical test infrastructure [2, 6, 7,, ] In comparison, only a limited amount of work has been done on wrapper design and TAM optimization for hierarchical SOCs Recently in [8], the issue of wrapper design for hierarchical cores has been addressed, and in [9, 2, 3], wrapper design and TAM optimization techniques for hierarchical cores have been explored 2 Wrapper Design Issues To understand the differences between the testing of nonhierarchical and hierarchical SOCs, it is important to understand the functionality of some elements of the IEEE P5 Wrapper architecture [] The main difference between testing nonhierarchical and hierarchical SOCs arises due to the functionality of the wrapper cells that buffer the functional inputs and outputs of the core The input wrapper cell shifts and applies test stimuli in the INTEST mode, and captures and shifts test responses in the EXTEST mode The operation of the output wrapper cells is the reverse of the input wrapper cells in the two modes /DATE6 26 EDAA

2 CFI m CTO FF m CFI CFO m CTO FF m CFO CFI m CTO FF m CFO Mode INTESTapply EXTESTm m capture CTI CTI (a) (b) (c) (d) Figure (a) Default IEEE P5 input wrapper cell; (b) Modified IEEE P5 wrapper cell in INTEST-apply cycle; (c) Modified IEEE P5 wrapper cell in EXTEST-capture cycle; (d) Control signals for the multiplexers in the two modes CTI Figure (a) shows a basic default IEEE P5 wrapper cell; CFI and CFO are the functional input and output of the wrapper cell respectively, and CTI and CTO are the test data inputs and outputs respectively During the INTEST mode, the path from CTI to CFO through the flip-flop and the two multiplexers is used, and during EXTEST mode, the path from CFI to the flip-flop is used to capture the test response from the chip interconnect Consequently, the path from CFI to CFO through the upper selection of the Mux when m= remains untested This is a drawback of this wrapper cell, which is highly undesirable since the untestable path is used in functional mode Hence an alternative P5-compliant wrapper cell configuration, as shown in Figure (b), is more commonly used in practice, eg, at Philips The paths used during INTEST-apply and EXTESTcapture cycles are highlighted in Figure (b) and (c) respectively Both paths of the second multiplexer are exercised in the test mode, thereby allowing better testability of the cell Also, during INTEST-apply cycle, the feedback path causes the test data bit of the previous cycle to be fed back into the flip-flop This is an added advantage of this cell, since it can prevent data corruption due to clock skew in back to back wrapper cells However, in this wrapper cell configuration, the feedback path also implies that the apply cycle of the INTEST mode cannot coincide with the capture cycle of the EXTEST mode The multiplexer control signal values for the two modes are conflicting, as shown in Figure (d) In this paper, and in [8], the use of the wrapper cell configuration of Figure (b) is assumed For a hierarchical core, suppose that the parent core and the child cores are tested on different TAM partitions When the parent core is in the INTEST mode, the embedded child cores have to be in EXTEST mode to ensure complete internal testing of the parent core [8, 9] Thus, the parent and the child INTEST testing cannot be done concurrently, since the child cores cannot be configured simultaneously in INTEST and EXTEST mode Due to this added constraint, the wrapper/tam optimization techniques that are used for nonhierarchical SOCs cannot be directly used for hierarchical SOCs that rely on the wrapper cell configuration shown in Figure (b) Nevertheless, the design in Figure (b) is still the preferred wrapper cell due to its better testability 22 Wrapper/TAM Optimization In [2], a wrapper/tam optimization approach is presented, which uses an existing hierarchy-oblivious TAM optimization approach iteratively to solve the problem of TAM optimization for hierarchical SOCs However, in this approach, the constraint of child and parent INTEST testing being time multiplexed is ignored In [3], a TAM design technique for hierarchical SOCs is presented in which the hierarchical cores are assumed to be hard wrapped cores This approach requires large area overhead due to the added registers for bandwidth matching, and it also requires synchronization of the clock signals In [9], modified input and output wrapper cells are used to allow concurrent INTEST testing of the parent and child cores An extra flip-flop and a multiplexer are used in this configuration Therefore, the wrapper cells used in this approach have larger area compared to the conventional IEEE P5 wrapper cells; thus they may not always be feasible In [8], the problem of designing an IEEE P5-compliant wrapper for hierarchical cores has been addressed The IEEE P5-compliant wrapper for hierarchical cores has a new set of terminals, called the CTAM terminals, which are used to access the child cores embedded in a parent core The wrapper for the parent core operates in two complementary test modes In the INTEST P mode, internal testing of the parent core is carried out Test data is scanned through the parent core scan chains, the parent core wrapper cells, and the child core wrapper cells The child cores have to be in the EXTEST mode to ensure complete core-internal testing of the parent core Hence, in the INTEST P mode, the available TAM wires are distributed between the parent core scan chains and wrapper cells, as well as the child core TAM architecture This was ignored in the prior work on TAM optimization for hierarchical cores in [2] In the INTEST C mode, child core internal testing is carried out; all child cores are in INTEST mode In this mode, the available TAM width at the wrapper interface can be utilized for child core testing alone Since the two modes operate independently, they are timemultiplexed using multiplexers The wrapper design approach presented in [8] is suitable only for hierarchical cores with a hard TAM architecture Moreover, the wrapper design approach of [8] has not been used for TAM optimization In this paper, we solve the wrapper and TAM optimization problem in conjunction for two different design scenarios and evaluate the approach using the metrics of area impact and test application time

3 3 DfT Techniques for Test Length Reduction In this section, we discuss the impact of using (a) scan chain bypass, (b) core bypass, and (c) scan chain reordering, on the test time for a hierarchical core We also discuss the impact of these DfT techniques on chip area Scan chain bypass and core bypass have been studied in prior work [4], but they have not been discussed in the context of hierarchical cores Scan chain bypass : The test time T i (w) for a core C i is defined as:t i (w) =(+max(si i,so i )) p i +min(si i,so i ), where si i and so i are the maximum scan-in and scan-out length of core C i for a TAM width of w, and p i is the number of test patterns Typically, it is assumed that for any given core, the test data volume in the INTEST mode is much greater than the test data volume in the EXTEST mode Thus, the child core architecture, which consists of the child cores wrapper and the embedded TAM, is optimized for the INTEST mode only During INTEST, the test stimuli are scanned into the input wrapper cells and scan chains, and the test responses are scanned out of the scan chains and the output wrapper cells Hence, the scan chains are sandwiched between the input and output wrapper cells This ensures smaller scan-in and scan-out lengths during INTEST, compared to the scan chains being ordered before or after the wrapper cells However, in the EXTEST mode, the scan chains of the child cores add to the scan-in and scan-out length even though they do not participate in the test This additional contributer to the scan length can be eliminated by using a scan chain bypass A flip-flop or register is not required in the bypass path if the scan-chains are local to the same module Typically, a scan chain bypass has an area overhead of one multiplexer Thus, this trade-off between scan length reduction and increased DfT overhead has to be carefully evaluated In the case of a hierarchical core, the scan length reduction in child core EXTEST mode pays off only if the scan chain for the child core architecture is long enough to be the maximum scan-in and scan-out length of the parent core Core bypass: The core bypass feature allows the bypass of an entire core in one clock cycle by means of a bypass register or flip-flop across the core It has been shown that this feature can reduce the test time significantly in a TestRail architecture [2] In [8], it is shown that core bypasses can reduce the test time of hierarchical cores as well If the TAM width at the parent core s interface is less than the number of CTAMs, test length is likely to be reduced if one or more CTAM chains of the child core architecture are daisy-chained This results in an increase in the scan-in and scan-out lengths of all the cores A core bypass can reduce the impact of daisy-chaining on the scan lengths of the cores Scan chain bypasses can also reduce the scan-in and scanout lengths in this example; however, core bypasses are more effective in the INTEST C mode since they eliminate the wrapper cells in the scan path as well Scan chain bypasses are more useful for the INTEST P mode, because the scan chains are excluded from the scan path without excluding wrapper cells, which are essential for the INTEST P mode Scan chain reordering: This is another technique that can be explored to reduce the CTAM scan length of the child cores during the INTEST P mode Compared to the INTEST mode, the roles of the input and output wrapper cells in the EXTEST mode are reversed Ideally, in the EXTEST mode, the output wrapper cells should precede the input wrapper cells to minimize the scan-in and scan-out lengths By using additional hardware, it is possible to make the wrapper reconfigurable in the EXTEST mode, such that the order of the wrapper cells is reversed This technique requires three two-input multiplexers for each scan path of the core The benefits of using this type of design optimization, as in the case of scan chain and core bypasses, depends on the child core TAM architecture available The improvements in the CTAM lengths depends on the difference in the number of input and output wrapper cells of the cores that interface directly with the CTAM terminals 4 Design Scenario I In this scenario, the parent core provider implements the wrapper and TAM architecture for the child cores before core delivery The system integrator designs the overall wrapper/tam architecture for the hierarchical SOC The information provided for the hierarchical core by the core provider includes information about the test infrastructure for the child cores This information is used for wrapper design of the hierarchical core in the INTEST P and INTEST C modes The problem of wrapper/tam optimization for this scenario is stated as follows Problem P I : Given (i) a hierarchical SOC with N top-level cores, where one or more top-level core may be a parent core with embedded child cores, (ii) the wrapper and TAM architecture for each embedded child core, (iii) the test set parameters for each top-level core C i, i N, and (iv) the SOC-level TAM width W, determine: The number of TAM partitions and the partition widths; 2 Wrapper design for each top-level core C i, i N; 3 Assignment of top-level cores to TAM partitions, such that the testing time for the SOC is minimized The test set parameters for each core C i, i N, includes the number of primary inputs fi i, primary outputs fo i, bidirectional I/Os b i, test patterns p i, scan chains k i, and the different scan chain lengths The cores are assumed to have hard scan chains, ie, the number and length of scan chains are fixed IfC i is a hierarchical (parent) core, the test data for it also includes the test data and test infrastructure parameters for its child cores For any given parent core C i, the test data and test infrastructure for its embedded child core includes the following: (i) the set M i of CTAM chains; (ii) the set CC i of embedded child cores; (iii) for each child core c CC i,the number of test patterns p c, the total scan length, scan-in length, and scan-out length on CTAM chain k, k M i, denoted by sl c,k, si c,k, and so c,k, respectively If core C i is not hierarchical, M i = and CC i = If all cores in the SOC are non-hierarchical, ie, M i =, i N, P I reduces to Problem P NPAW, the wrapper/tam optimization problem for non-hierarchical SOCs from [6] Since

4 P NPAW was shown to be NP-hard in [6], P I is also NP-hard Hence, we resort to efficient heuristics to solve this problem In the IEEE P5-compliant wrapper design technique presented in [8], wrapper design allows a hierarchical core to interface with a TAM partition of any width Thus, using this wrapper design technique, hierarchical cores can be integrated into an existing wrapper/tam optimization technique for non-hierarchical SOCs We implement wrapper/tam optimization for this scenario using the TR-ARCHITECT tool [2] The TR-ARCHITECT tool includes four main procedures, namely: () CREATESTARTSOLUTION; (2) OPTIMIZE- BOTTOMUP; (3) OPTIMIZE-TOPDOWN; (4) RESHUFFLE In CREATESTARTSOLUTION, an initial TAM partition is created by assigning to each core, at least one TAM wire based on its test data volume The other procedures optimize the initial solution The procedure OPTIMIZE-BOTTOMUP attempts to minimize the test time for a given test architecture by merging the TAM partition with the shortest test time with another TAM partition, such that the current test time of the SOC is not exceeded The wires that are thus freed up can be used for overall test time reduction In OPTIMIZE-TOPDOWN, first, the TAM partition with the largest test time is merged in an iterative manner with another TAM partition If the first step does not reduce the test time any more, two TAM partitions that are not the partitions with the largest test time are merged to free up wires, provided the test time does not increase The freed up wires are then used to reduce the overall SOC time further The procedure RESHUFFLE minimizes the test time for a given test architecture by moving individual cores assigned to the TAM partition with the largest test time to another TAM partition, such that the current time of the SOC is not exceeded The test times for the cores, for any given TAM width, is obtained using procedure WRAPPERDE- SIGN In our work, the wrapper design technique from [8] is used for hierarchical cores and WRAPPERDESIGN is used for non-hierarchical cores For our experimental setup, we use TR-ARCHITECT to create a TAM architecture for the child cores embedded in the parent cores in the ITC 2 SOC benchmarks We assume an internal CTAM width for the hard TAM architectures of the child cores, and use TR-ARCHITECT to design the wrapper and TAM architectures for the child cores The TAM architecture is designed to minimize the overall test length of the child cores From the results thus obtained, it is possible to determine the scan-in, scanout and scan-lengths of the cores on each CTAM chain This information is sufficient for the wrapper design procedure used in the overall design flow of the hierarchical SOC We present experimental results for two of the ITC 2 benchmark SOCs in Section 7 5 Design Scenario II In this scenario, since the embedded child core test infrastructure is soft, the system integrator can design the wrapper and TAM architecture of the child cores in accordance with the TAM width available at the parent core interface Thus, if w TAM wires are available at the parent core level, the child core architecture can be designed to have up to w CTAM terminals Thus, the CTAM terminals can be directly connected to the available TAM width, and external daisy chaining of the CTAM chains is not required In this case, the problem of designing the wrapper and TAM architecture for the child cores corresponds to that of designing the wrapper and TAM architecture for an SOC; the TAM architecture is designed for an SOC-level TAM width of w However, wrapper design for the parent core and the overall wrapper/tam optimization problems for the hierarchical SOC are still different from the corresponding problem for non-hierarchical cores The problem statement for this scenario is as follows Problem P II : Given (i) a hierarchical SOC S with a set C of N cores, ie, C = N,(ii) the test parameters and the parent core PC i for each core C i, where i N, C i C,and PC i {S} C\{C i },and (iii) the total SOC-level TAM width W, determine: The number of TAM partitions and the partition widths; 2 Wrapper design for each core C i ; 3 Assignment of cores to TAM partitions, such that the total testing time for the SOC is minimized The test parameters for each core C i, i N includes the number of primary inputs fi i,primary outputs fo i,bidirectional I/Os b i, test patterns p i, scan chains k i, and the different scan chain lengths The cores are assumed to have hard scan chains, ie, the number and lengths of scan chains are fixed The hierarchy tree is determined from the parent module information given for each core The parent for the top-level modules is the SOC itself If the parent module for every core in an SOC is the SOC itself, ie, PC i = S, i N,then P II for that SOC reduces to Problem P NPAW from [6] Thus, by the method of restriction, Problem P II is also an NP-hard problem We extend TR-Architect in two main ways to solve P II : (a) we pre-process the SOC specifications, such that only the toplevel cores are presented to the TR-ARCHITECT tool as described in [2], and (b) we replace WRAPPERDESIGN with another procedure called HIERWRAPPER The HIERWRAPPER procedure makes use of TR-ARCHITECT, WRAPPERDESIGN, and WRAPP, where WRAPP is the wrapper design technique for INTEST P mode, as presented in [8] 6 Lower Bounds on Test Time For each hierarchical core C i, a lower bound on test time LB i can be defined aslb i = LBC i + LBP i, where LBC i is the lower bound on test time in the INTEST C mode, and LBP i is the lower bound on test time in the INTEST P mode For the case of hard embedded child cores in hierarchical cores, LBC i corresponds to the test time for the hard child core TAM architecture in clock cycles For soft embedded child core architectures in hierarchical cores, the lower bound on test time LBC i for Core C i can be determined using a lower bound expression defined for non-hierarchical SOCs, as presented in [2] Thus, LBC i = min{lbt,lb2 T }, where LB T is an architectureindependent lower bound based on the maximum test time of

5 the wrapped cores, and LBT 2 is a lower bound based on the test data volume of the SOC The formulation for LBP i is based on the test data volume for the INTEST P mode For the case of soft embedded child core architectures, the scan-in and scan-out lengths of the parent core used for calculating test data volume are defined as nc i si i = nff i + fi i +b i + (nff j + fi j +fo j +b j ) (6) j= nc i so i = nff i + fo i +b i + (nff j + fi j +fo j +b j ) (62) j= where the various parameters in () and (2) are defined as follows: si i is the scan-in length for core C i ; 2 so i is the scan-out length for core C i ; 3 nff i is the number of flip-flops for corec i ; 4 fi i is the number of functional inputs for core C i ; 5 fo i is the number of functional outputs for core C i ; 6 b i is the number of bidirectional terminals for core C i ; 7 nc i is the number of child cores in core C i If child core scan chain bypasses are enabled, we disregard the number of flip-flops in the child cores in () and (2) For a hard implementation of the child core architecture, the scanin and scan-out lengths of the parent core are defined assi i = FF i +fi i +b i +Tsi,and si i = FF i +fi i +b i +Tso,where Tsi and Tso are the maximum scan-in and scan-out lengths of the child core architecture, respectively, in the EXTEST mode of the child core wrappers The test data volume of Core C i is defined as v i = max{si i,so i } p i +min{si i,so i }, where p i is the number of test patterns Thus, a lower bound (in clock cycles) on the test time of parent core C i for a SOC level TAM width of W is defined as LBP i = v i /W + p i (63) Using Equation (63), a lower bound on test time can be calculated for each parent core for both design scenarios The sum of the lower bounds for all the individual cores in the SOC provides a lower bound on the test time for the SOC However, if the SOC has multiple TAM partitions, the TAM partition with the maximum test time can have only one core with the minimum number of test patterns Hence, only the minimum number of test patterns among all cores is used in the lower bound expression for SOC test time Also, we assume that the scan-out of the responses of the last test pattern of a core is not overlapped with the scan-in of the stimuli of the first test pattern of another core on the same level of hierarchy Thus, a lower bound LB H for hierarchical cores can be defined as LB H = N i= v i /W + min i N {p i}+ N LBC i (64) We also obtain another lower bound LB2 H from [5] as follows: LB2 H =max i N{T i (W)},where T i (W ) is the test time for core C i at core-level TAM width of W The bound LB 2 H is more i= p228 p34392 Module name # CTAMs Module name # CTAMs Module 5 Module 2 2 Module 5 6 Module 2 Module 8 6 Table Number of CTAMs specified for the hierarchical modules in p228 and p34392 p228 W LB H T T T byp T (%) p34392 W LB H T T T byp T (%) LBH T : Lower bound on test time in clock cycles; T: Test application time (in clock cycles) without core bypass; T byp : Test application time(in clock cycles) with core bypass; T : T byp T T Table 2 Experimental results for Design Scenario I accurate for larger TAM widths (W >32) However, for smaller values of W, LB H is tighter Hence, the overall lower bound is determined as LB H =max{lb H,LBH 2 } 7 Experimental Results We first present experimental results for p228 and p34392 for Design Scenario I For the experimental setup, the TAM optimization design tool TR-ARCHITECT is used to create a hard implementation of the child core architectures The child core architecture for the two hierarchical cores in p228 is the same as that presented in [8] The CTAM widths used for the various hierarchical cores in p228 and p34392 are shown in Table We present results on test times obtained for different values of TAM width for the two benchmark SOCs in Table 2 The test times are presented for two cases: (a) when child core architectures in hierarchical cores are equipped with core bypasses, and (b) when core bypasses are not implemented Lower bounds on test time are also listed in Table 2 From Table 2, we observe that the lower bounds on test time do not decrease any further for TAM widths greater than 32 This is due to the presence of a bottleneck core that dominates the SOC test time In SOC p228, hierarchical Core dominates the test time due to long scan lengths in its child core architecture As a result, the test time reaches the lower bound value of clock cycles for W > 32 Similarly, hierarchical Core 8 dominates the test time for p34392 for W > 32 Note that the test time of any hierarchical core cannot decrease below the test time of it s child core architecture, once the CTAM width of the child core architecture is equal to the parent-core level TAM width In both SOCs, for W>32, the CTAM width of the child core architectures is matched with the available TAM width at the

6 [9] Proposed Approach T NG W T o NG o LB H T T n NG n % % p p p T = Tn To To ; NG = NGn NGo NGo ; Table 3 Comparison of the test time and area overhead of the proposed approach with the approach from [9] parent core level for the bottleneck core Table 2 also shows the test time results with and without core bypasses As expected, for many values of W, the test time for the TAM architecture with core bypasses is less than that for the TAM architecture without core bypasses The reduction in test time with the use of core bypasses decreases with an increase in W This happens because the daisy chaining of the child core CTAM lengths typically reduces with an increase in TAM width The core bypass implementation requires 46 and 96 additional 2-to- multiplexers in p228 and p34392, respectively If N c is the set of child cores in an SOC, and w i is the TAM width available to each child core C i i N c, the number of extra multiplexers required for the implementation of core bypasses is given by N c i= w i Since the child core architecture is fixed, this number is independent of the SOC-level TAM width W Thus, core bypasses can reduce the test time of an SOC significantly for smaller TAM width values at the expense of a small increase in chip area Next, we present results for Design Scenario II In Table 3, we compare the test application time and chip area of the proposed approach to that of the method presented in [9] In [9], modified wrapper cells are used, which allow parallel INTEST testing of the child cores and the parent cores, at the expense of an extra flip-flop and an extra multiplexer in each wrapper cell The chip area is quantified in terms of the total number of NAND2 gates used in the wrapper cells of the SOC It is assumed that a 2- to- multiplexer and a flip-flop is equivalent in area to 3 and 7 NAND2 gates, respectively The derived lower bounds on test time are also presented for the proposed approach in Table 3 In Table 3, the increase in test time for the proposed approach is accompanied by a decrease in the chip area compared to [9] for all the SOCs In SOC p228, the test time does not decrease as much with an increase in W due to hierarchical Core Although, the SOC-level TAM width increases, the increase in the TAM width of Core is not sufficient to reduce the test time of its child core architecture significantly As a result, Core dominates the test time of p228 In p34392, the lower bounds on test time are reached for several TAM width values due to the bottleneck Core 8 that dominates the SOC test time In this SOC, the reduction in chip area is significant compared to the increase in test time for all TAM width values From these results, we conclude that for most SOCs, the gains in area are much higher compared to [9], and these gains can be achieved at the expense of a small increase in the overall SOC test application time 8 Conclusion We have addressed the problem of test infrastructure design for hierarchical SOCs We have shown how a hierarchy-aware test planning method can be used for TAM optimization and test scheduling for hierarchical SOCs in two practical design scenarios We have derived lower bounds on test time and presented experimental results for four ITC 2 SOC test benchmarks We have shown that, in the first design scenario, core bypasses can reduce the test time of hierarchical SOCs significantly with a small increase in chip area We have also shown that for the second design scenario, the wrapper area is much less compared to [9], but there is only a small increase in test application time References [] Y Zorian et al Testing Embedded-Core Based System Chips In Proc ITC, pp 3 43, 998 [2] S K Goel and E J Marinissen SOC Test Architecture Design for Efficient Utilization of Test Bandwidth ACM Trans Design Automation of Electronic Systems, 8(4): , October 23 [3] S Dutta et al VIPER: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems IEEE Design & Test of Computers, 8(5):2 3, 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