Jin-Fu Li. Department of Electrical Engineering. Jhongli, Taiwan
|
|
|
- Muriel Perry
- 6 years ago
- Views:
Transcription
1 Chapter 9 Basics of SOC Testing Jin-Fu Li Advanced Reliable Systems (ARES) Lab Department of Electrical Engineering National Central University Jhongli, Taiwan
2 Outline Introduction SOC Test Challenge SOC Test Access Mechanisms SOC Test Control Architectures t Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
3 What is an SOC? Definition Integration of multiple cores (e.g., microprocessor, digital signal processor, RAM, ROM, flash memory, I/Os, and analog components which make a complete system) onto a single chip ADC FPGA Flash Memory CPU UDL DSP MPEG SRAM SRAM DRAM Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
4 What are Cores? Definition Predefined, pre-verified complex functional blocks, also known as IPs, virtual components Examples Processor Cores: ARM, MIPS, IBM PowerPC PC Peripherals: MMU, DMA Controller Interface: PCI, USB, UART Multimedia: JPEG compression, MPEG decoder Networking: Ethernet Controller, MAC Various core description levels Soft cores: register-transfer level (synthesizable HDL) Firm cores: gate-level netlist (Verilog netlist) Hard cores: layout (GDS2) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
5 Traditional & Core-Based IC Design Traditional IC design IC is designed from scratch Reuse of small modules: standard-cell library and memory modules Core-based IC design Reuse of large modules: cores, IP, virtual components Divide-and-conquer design methodology Definition of standards to make reuse easy Reduce time-to-market Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
6 Difference Between SOB and SOC System-on-Board (SOB) IC Design IC Verification System-on-Chip (SOC) Core Design Core Verification IC Manufacturing IC Test Analogy Reuse of predeisgned components in a system SOB Design SOB Verification SOB Manufacturing SOB Test SOC Design SOC Verification SOC Manufacturing SOC Test Difference Cores in SOC are fabricated and tested in the final system [Zorian, et al.-itc97] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
7 What are The Test Challenges? Distributed design and test development Mixed technologies: logic, processor, memory, analog Need various ATPG/DFT/BIST/other techniques Multiple hardware description levels for cores Need test plan for the various levels Different core providers and SOC test t developers Need standard for test integration Deeply embedded cores Need electronic test access mechanism Core/test reuse Need plug-and-play l test t mechanism Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
8 What are The Test Challenges? Hierarchical core reuse Need hierarchical test management SOC-level test optimization Test time can be extremely large Need parallel testing or test scheduling Test power must be considered Need low-power design or test t scheduling Testable design automation Need new testable design tools and flow Test economic consideration Need to determine e test strategy and overall test plan SOC yield improvement Large amount of defect-sensitive memory cores Need cost-effective repair techinques Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
9 Generic Test Access Structure ADC FPGA Wrapper Flash Memory Source CPU UDL Test Access Mechanism (TAM) DSP TAM Sink MPEG SRAM SRAM DRAM [Y. Zorian, et al.-itc98] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
10 1500 Test Scalable Structure Source User Defined Parallel TAM Sink TAM-in TAM-out TAM-in TAM-out 1500 Wrapper 1500 Wrapper Fin Core1 Fout Fin CoreN Fout WSI WIR WSO WSC WSI WIR WSO User-Defined Test Controller Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
11 1500 Parallel TAM Configuration WPC Daisychained TAM WPI WPO ENA WPP ENA WPP ENA WPP Core Core Core WSI Wrapper WSP Wrapper WSP Wrapper WSP WSO WSC Standardized Plug & Play Wrapper Serial Ports Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
12 1500 Parallel TAM Configuration WPC Bussed TAM WPI WPO ENA WPP ENA WPP ENA WPP Core Core Core WSI Wrapper WSP Wrapper WSP Wrapper WSP WSO WSC Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
13 1500 Parallel TAM Configuration WPC WPI WPO WPC WPI Direct Access TAM WPO WPO WPC WPI ENA WPP ENA WPP ENA WPP Core Core Core WSI Wrapper WSP Wrapper WSP Wrapper WSP WSO WSC Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13
14 TAM Implementations Many TAM implementation have been reported Examples: Multiplexed access Reused system bus (AMBA) Transparency Boundary Scan Scalable TAMs (Test bus, TestRail) On one SOC, different TAMs may co-exist Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
15 Multiplexed Access [E. J. Marinissen, ITC98] (a): Multiplexing architecture; (b) daisy-chain architecture; (c) Distributed architecture Core A N Core A na Core A N Core B Core B Core B nb Core C Core C nc Core C IC IC IC (a) (b) (c) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
16 Test Shell/TestRail [E. J. Marinissen, ITC98] Every core is wrapped with a TestShell The TestShell is the test data transport mechanism TCM is a standardized test control mechanism in the TestShell The host is the environment in which the core is embedded TCM host TestShell TCM TestShell TCM TestRail IP A IP B Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
17 Test Shell/TestRail [E. J. Marinissen, ITC98] host Shell TCM TCM TestRail Core A 16 Shell TCM Shell TCM Core B Core C Shell TCM Shell TCM 2 Core E Shell TCM TestRail 2 10 Core D 8 Core F 10 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
18 SOC Test Control Architectures TAP Linking Module (TLM) architecture I C B S R NTC CBSR CBSR CBSR NTC NTC TAP1 TAP ed Core TAP ed Core TAP ed Core X Y Z TAP2 TAP3 TAP4 SEL ENA SEL ENA SEL ENA SEL ENA TAP Linking Module (TLM) I C B S R TDI TCK TMS TRST* TDO [Lee Whetsel, ITC97] The TLM operates to enable and connect one or more TAPs to be accessed via the IC s test pins Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
19 SOC Test Control Architectures TLM architecture [Lee Whetsel, ITC97] TAP TLM: SEL TAP1 LC2 TAP2 LC3 TAP3 LC4 TAP4 Enable 1,2,3,4 TLM TAP: LC ENA SEL1 SEL2 SEL3 SEL4 TAP Linking Module (TLM) TDO4 TDO3 TDO2 TDO1 ENA1 ENA2 ENA3 ENA4 Reset* TDO TAPSEL0,1 TLM-Select M U X 3 S M U X Enable TDI TCK TMS TRST* TDO The TLM communicates with TAPs via select (SEL), enable (ENA) and Link Control (LC). After power up, or test reset, the TLM defaults to connecting TAP1 to the test pins Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
20 SOC Test Control Architectures Modified state diagram TMS=1 Test Logic Reset ENA:TMS=1:0 Or TMS=0 ENA:TMS=0:x Run Test/ ENA:TMS=1:1 Idle Unlinked Stroble State ENA=0,TAP disable ENA=1,TAP enable ENA:TMS=1:1 Data Register Scan ENA:TMS=1:0 Or ENA:TMS=0:x Select DRS Capture DR Shift DR Update DR Instruction Register Scan TMS=1 Select IRS Link change state TMS=1 Capture IR Shift IR Update IR TMS=0 TMS=1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20
21 Hierarchical Test Methodology [J.-F. Li, et al., IEEE Micro 02] TDI_UP TMS_UP TRST_UP TCK_UP TDO_UP HTM1 TDI_C ECS TDI_H TCS_DN TDO_H TDO_C WCI Core 1 (P1500) WCI MBI Core 2 (BISTed RAM) WCI Core 3 (P1500) HTM2 TAM 2 WCI Core 4 (P1500) TAP Core 5 (JTAG) TAM 1 TAM input TAM output Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21
22 Hierarchical Test Procedure [J.-F. Li, et al., IEEE Micro 02] Test Configuration Load the instructions for the wrappers and memory BIST interfaces (MBIs) TAM Specification Specify the cores to be tested by the TAM Test Transportation Import the test patterns and export the test responses Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
23 An Example TDI_UP TMS_UP TRST_UP TCK_UP TDO_UP HTM1 TDI_C ECS TDI_H TCS_DN TDO_H TDO_C WCI Core 1 (1500) WCI MBI Core 2 (BISTed RAM) WCI Core 3 (1500) HTM2 TAM 2 WCI Core 4 (1500) TAP Core 5 (JTAG) TAM 1 TAM input TAM output Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23
24 Hierarchical Test Manager Test Manager Boundary Register Selection Register Bypass Register Instruction Decoder Instruction Register FSM WCS Encoder ECS0 ECS1 ECS2 TMS TCK TRST TDI TMS TCK TRST TDI TMS_N TCK_N TRST_N TDI_UP TDO_UP Hierarchical Test Interface Switch Box TDI_C TDI_H TDO_C TDO_H Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24
Chapter 8 Test Standards. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 8 Test Standards Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline 1149.1 standard for system-on-board 1500 standard for system-on-chip Advanced
Testable SOC Design. Sungho Kang
Testable SOC Design Sungho Kang 2001.10.5 Outline Introduction SOC Test Challenges IEEE P1500 SOC Test Strategies Conclusion 2 SOC Design Evolution Emergence of very large transistor counts on a single
Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab. Embedded Core Testing (ΙΕΕΕ SECT std) 2
CMOS INTEGRATED CIRCUIT DESIGN TECHNIQUES University of Ioannina Embedded Testing (ΙΕΕΕ 1500 Std. SECT) Dept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit Design Techniques
SoC Design Flow & Tools: SoC Testing
SoC Design Flow & Tools: SoC Testing Jiun-Lang Huang Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Outline l SoC Test Challenges l Test Access
Programovatelné obvody a SoC. PI-PSC
Evropský sociální fond Praha & EU: Investujeme do vaší budoucnosti Programovatelné obvody a SoC. PI-PSC doc. Ing. Hana Kubátová, CSc. Katedra číslicového návrhu Fakulta informačních technologií ČVUT v
IEEE P1500 Core Test Standardization
Technical Proposals for IEEE P1500 Core Test Standardization Erik Jan Marinissen Research Laboratories Eindhoven, The Netherlands P1500 Meeting ITC Test Week, Washington D.C., November, 1997 Technical
IEEE P1500, a Standard for System on Chip DFT
page 1(6) IEEE P1500, a Standard for System on Chip DFT Kim Petersén HDC, Hardware Design Center 723 50 Västerås Sweden Email: kim.petersen@hdc.se key words: IP, DFT, SoC, BIST, BISR ABSTRACT This document
ECE 111 ECE 111. Advanced Digital Design. Advanced Digital Design Winter, Sujit Dey. Sujit Dey. ECE Department UC San Diego
Advanced Digital Winter, 2009 ECE Department UC San Diego dey@ece.ucsd.edu http://esdat.ucsd.edu Winter 2009 Advanced Digital Objective: of a hardware-software embedded system using advanced design methodologies
Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism Λ
Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism Λ Mounir Benabdenbi y Walid Maroufi z Meryem Marzouki LIP6 Laboratory Couloir 55-65, 4 Place Jussieu, 75252 Paris Cedex 5, France
SoC Design Lecture 14: SoC Testing. Shaahin Hessabi Department of Computer Engineering Sharif University of Technology
SoC Design Lecture 14: SoC Testing Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Outline Introduction to Testing Importance of SoC Testing Challenges of SoC Testing
Overview the Proposed IEEE P1500 Scaleable Architecture for Testing Embedded Cores
Unapproved Working Document Overview the Proposed Scaleable Architecture for Testing Embedded Cores Presented on behalf of the CTAG Team by Mike Ricchetti June 7th, at DAC 2000 Architecture Task Force,
Graduate Institute of Electronics Engineering, NTU Advanced VLSI SOPC design flow
Advanced VLSI SOPC design flow Advisor: Speaker: ACCESS IC LAB What s SOC? IP classification IP reusable & benefit Outline SOPC solution on FPGA SOPC design flow pp. 2 What s SOC? Definition of SOC Advantage
Embedded Quality for Test. Yervant Zorian LogicVision, Inc.
Embedded Quality for Test Yervant Zorian LogicVision, Inc. Electronics Industry Achieved Successful Penetration in Diverse Domains Electronics Industry (cont( cont) Met User Quality Requirements satisfying
IP CORE Design 矽智產設計. C. W. Jen 任建葳.
IP CORE Design 矽智產設計 C. W. Jen 任建葳 cwjen@twins.ee.nctu.edu.tw Course Contents Introduction to SoC and IP ARM processor core and instruction sets VCI interface, on-chip bus, and platform-based design IP
Digital Integrated Circuits
Digital Integrated Circuits Lecture Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University Design/manufacture Process Chung EPC655 2 Design/manufacture Process Chung EPC655 3 Layout
Boundary Scan. Sungho Kang. Yonsei University
Boundary Scan Sungho Kang Yonsei University Outiline Introduction TAP Controller Instruction Register Test Data Registers Instructions Hardware Test Innovations PCB Test Conclusion 2 Boundary Scan Improve
IEEE JTAG Boundary Scan Standard
IEEE 1149.1 JTAG Boundary Scan Standard Bed-of-nails tester Motivation System view of boundary scan hardware Elementary scan cell Test Access Port (TAP) controller Boundary scan instructions Example *Joint
Chapter 0 Introduction
Chapter 0 Introduction Jin-Fu Li Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan Applications of ICs Consumer Electronics Automotive Electronics Green Power
A Test Integration Methodology for 3D Integrated Circuits
2 9th IEEE Asian Test Symposium A Test Integration Methodology for 3D Integrated Circuits Che-Wei Chou and Jin-Fu Li Department of Electrical Engineering National Central University Jhongli, Taiwan 32
Automating IEEE 1500 Core Test An EDA Perspective
IEEE Std 1500 and Its Usage Automating IEEE 1500 Test An EDA Perspective Krishna Chakravadhanula and Vivek Chickermane Cadence Design Systems Editor s note: Standardized design and test practices enable
An Industrial Approach to Core-Based System Chip Testing
An Industrial Approach to Core-Based System Chip Testing Erik Jan Marinissen Philips Research Abstract: Key words: System chips are increasingly being designed by embedding reusable predesigned and pre-verified
Preliminary Outline of the IEEE P1500 Scaleable Architecture for Testing Embedded Cores
Preliminary Outline of the Scaleable Architecture for Testing Embedded Cores Mike Ricchetti and Fidel Muradali VTS99 Dana Point, CA April 28, 1999 Architecture Task Force, 1999 Presentation Outline Introduction
Using Mentor Questa for Pre-silicon Validation of IEEE based Silicon Instruments by CJ Clark & Craig Stephan, Intellitech Corporation
Using Mentor Questa for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments by CJ Clark & Craig Stephan, Intellitech Corporation INTRODUCTION IEEE 1149.1-2013 is not your father s JTAG.
Abstract. 1 Introduction. 2 Time Domain Multiplexed TAM
Time Domain Multiplexed TAM: Implementation and Comparison Zahra sadat Ebadi and Andre Ivanov Department of Electrical and Computer Engineering University of British Columbia Vancouver, BC, Canada V6T
Boundary Scan Implementation
OpenCORES s Boundary Scan Implementation Abstract This document describes Boundary Scan Implementation (software and hardware solution. It is fully IEEE 1149.1 compliant. Date : August 6, 2000 Version:
Boundary-scan test for structural fault detection
Boundary-scan test for structural fault detection J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias 42-537 Porto - PORTUGAL Tel. 351 225 81 889 / Fax: 351 225 81 443 [ jmf@fe.up.pt ] Tallinn Technical
Nexus Instrumentation architectures and the new Debug Specification
Nexus 5001 - Instrumentation architectures and the new Debug Specification Neal Stollon, HDL Dynamics Chairman, Nexus 5001 Forum neals@hdldynamics.com nstollon@nexus5001.org HDL Dynamics SoC Solutions
A Research Paper on Designing a TAP(Test Access Port)
A Research Paper on Designing a TAP(Test Access Port) 1 Mr. VISHWAS K. CHAUDHARY, 2 Mr. MANISH J. PATEL 1, 2 P. G. Students in M.E.(VLSI & ESD) Gujarat Technological University & Seer-Akademi Ahmedabad,
EMERGING STRATEGIES FOR RESOURCE-CONSTRAINED TESTING OF SYSTEM CHIPS Resource-constrained system-on-a-chip test: a survey
EMERGING STRATEGIES FOR RESOURCE-CONSTRAINED TESTING OF SYSTEM CHIPS Resource-constrained system-on-a-chip test: a survey Q. Xu and N. Nicolici Abstract: Manufacturing test is a key step in the implementation
DESIGN OF IEEE TAP CONTROLLER IP CORE
DESIGN OF IEEE 1149.1 TAP CONTROLLER IP CORE Shelja A S 1, Nandakumar R 2 and Muruganantham C 3 1 Department of Electronics and Communication Engineering, NCERC. sheljaas@gmail.com 2 Assistant scientist/engineer,
Fujitsu SOC Fujitsu Microelectronics America, Inc.
Fujitsu SOC 1 Overview Fujitsu SOC The Fujitsu Advantage Fujitsu Solution Platform IPWare Library Example of SOC Engagement Model Methodology and Tools 2 SDRAM Raptor AHB IP Controller Flas h DM A Controller
Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost
IEEE TRANSACTIONS ON COMPUTERS, VOL. 67, NO. 12, DECEMBER 2018 1835 Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost Inhyuk Choi, Hyunggoy Oh, Young-Woo Lee, and Sungho Kang, Senior
IEEE Std : What? Why? Where?
Proceedings of DCIS 2012: xxvii th conference on design of circuits and integrated systems IEEE Std 1149.7: What? Why? Where? Francisco R. Fernandes 1, Ricardo J. S. Machado 1, José M. M. Ferreira 1,2,
Glossary. AHDL A Hardware Description Language, such as Verilog-A, SpectreHDL, or VHDL-A, used to describe analog designs.
Glossary ADC, A/D Analog-to-Digital Converter. AHDL A Hardware Description Language, such as Verilog-A, SpectreHDL, or VHDL-A, used to describe analog designs. AMBA Advanced Microcontroller Bus Architecture.
Chapter 1. Introduction. System-on-Chip Test Architectures Ch. 1 Introduction - P. 1 EE141
Chapter 1 Introduction System-on-Chip Test Architectures Ch. 1 Introduction - P. 1 What is this chapter about? Review of Importance of Testing Yield and Reject Rate Reliability and System Availability
CONTACT: ,
S.N0 Project Title Year of publication of IEEE base paper 1 Design of a high security Sha-3 keccak algorithm 2012 2 Error correcting unordered codes for asynchronous communication 2012 3 Low power multipliers
Platform-based Design
Platform-based Design The New System Design Paradigm IEEE1394 Software Content CPU Core DSP Core Glue Logic Memory Hardware BlueTooth I/O Block-Based Design Memory Orthogonalization of concerns: the separation
The SOCks Design Platform. Johannes Grad
The SOCks Design Platform Johannes Grad System-on-Chip (SoC) Design Combines all elements of a computer onto a single chip Microprocessor Memory Address- and Databus Periphery Application specific logic
Embedded Systems: Architecture
Embedded Systems: Architecture Jinkyu Jeong (Jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu)
Testing Embedded-Core Based System Chips
Testing Embedded-Core Based System Chips Yervant Zorian Erik Jan Marinissen Sujit Dey LogicVision 101 Metro Drive Third floor San Jose, CA 95110 U.S.A. zorian@lvision.com Philips Research Dept. VLSI Design
1687 Proposed Hardware Architecture Summary Update v7.0 June 25, 2007 IEEE 1687 IJTAG HW Proposal
IEEE 1687 IJTAG HW Proposal - 0 - 1687 Proposed Hardware Architecture This document contains the key components of the proposed 1687 Hardware Architecture that were recently adopted with a working group
TEST SCHEDULING OPTIMIZATION FOR EMBEDDED CORE TESTING
TEST SCHEDULING OPTIMIZATION FOR EMBEDDED CORE TESTING K. CHAKRAPANI 1, DR. P. NEELAMEGAM 2 School of Computing SASTRA University School of EEE SASTRA University ABSTRACT Test scheduling is crucially important
FPGA Based Digital Design Using Verilog HDL
FPGA Based Digital Design Using Course Designed by: IRFAN FAISAL MIR ( Verilog / FPGA Designer ) irfanfaisalmir@yahoo.com * Organized by Electronics Division Integrated Circuits Uses for digital IC technology
Chapter 2 Why use the IEEE 1500 Standard?
Chapter 2 Why use the IEEE 1500 Standard? 2.1 Introduction Before the question of Why use the IEEE 1500 Standard? is asked, another question should be addressed. Why do we need a wrapper at all? A wrapper
JTAG TAP CONTROLLER PROGRAMMING USING FPGA BOARD
JTAG TAP CONTROLLER PROGRAMMING USING FPGA BOARD 1 MOHAMED JEBRAN.P, 2 SHIREEN FATHIMA, 3 JYOTHI M 1,2 Assistant Professor, Department of ECE, HKBKCE, Bangalore-45. 3 Software Engineer, Imspired solutions,
Test-Access Planning and Test Scheduling. Sandeep Kumar Goel
Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips Sandeep Kumar Goel Promotiecommissie: Voorzitter: prof.dr.ir. A.J. Mouthaan University of Twente, NL Secretaris: prof.dr.ir.
Development of a Boundary Scan Test controller creation tool
Eindhoven University of Technology MASTER'S THESIS Development of a Boundary Scan Test controller creation tool by J.H. Coenen Supervisors: Prof. Ir. M.T.M. Segers Ir. M.N.M. Muris The faculty of Electronical
Betrouwbare Elektronica ontwerpen en Produceren
Betrouwbare Elektronica ontwerpen en Produceren Verbeter betrouwbaarheid, time to market en winstgevendheid met boundary scan JTAG Technologies B.V. Rik Doorneweert rik@jtag.com Boundary scan Testing HW
DFT Trends in the More than Moore Era. Stephen Pateras Mentor Graphics
DFT Trends in the More than Moore Era Stephen Pateras Mentor Graphics steve_pateras@mentor.com Silicon Valley Test Conference 2011 1 Outline Semiconductor Technology Trends DFT in relation to: Increasing
A Unified DFT Architecture for use with IEEE and VSIA/IEEE P1500 Compliant Test Access Controllers
A Unified DFT Architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers Bulent I. Dervisoglu Cadence Design Systems 2655 Seely Avenue San Jose, CA 95134 (408)-895 2184
Keysight Technologies Expanding IEEE Std Boundary-Scan Architecture Beyond Manufacturing Test of PCBA
Keysight Technologies Expanding IEEE Std 1149.1 Boundary-Scan Architecture Beyond Manufacturing Test of PCBA Article Reprint This paper was first published in the 2017 IPC APEX Technical Conference, CA,
SECTION 11 JTAG PORT
nc. SECTION JTAG PORT MOTOROLA DSP5662 User s Manual - nc.. INTRODUCTION....................................-3.2 JTAG PINS........................................-5.3 TAP CONTROLLER.................................-6.4
Expanding IEEE Std Boundary-Scan Architecture Beyond Manufacturing Test of Printed Circuit Board Assembly
Expanding IEEE Std 1149.1 Boundary-Scan Architecture Beyond Manufacturing Test of Printed Circuit Board Assembly Jun Balangue Keysight Technologies Singapore Jun_balangue@keysight.com Abstract This paper
COEN-4730 Computer Architecture Lecture 12. Testing and Design for Testability (focus: processors)
1 COEN-4730 Computer Architecture Lecture 12 Testing and Design for Testability (focus: processors) Cristinel Ababei Dept. of Electrical and Computer Engineering Marquette University 1 Outline Testing
SCANWORKS TEST DEVELOPMENT STATION BUNDLE
SCANWORKS TEST DEVELOPMENT STATION BUNDLE The ScanWorks Test Development Station is the most powerful set of boundary-scan test development and application tools available. It not only includes all the
A Review paper on the Memory Built-In Self-Repair with Redundancy Logic
International Journal of Engineering and Applied Sciences (IJEAS) A Review paper on the Memory Built-In Self-Repair with Redundancy Logic Er. Ashwin Tilak, Prof. Dr.Y.P.Singh Abstract The Present review
Embedded Systems: Hardware Components (part I) Todor Stefanov
Embedded Systems: Hardware Components (part I) Todor Stefanov Leiden Embedded Research Center Leiden Institute of Advanced Computer Science Leiden University, The Netherlands Outline Generic Embedded System
Test of NoCs and NoC-based Systems-on-Chip. UFRGS, Brazil. A small world... San Diego USA. Porto Alegre Brazil
Test of NoCs and NoC-based Systems-on-Chip Érika Cota Marcelo Lubaszewski UFRGS, Brazil 1 A small world... San Diego USA Porto Alegre Brazil 2 1 Where we are 3 Porto Alegre 4 2 Porto Alegre and UFRGS Porto
Designing with ALTERA SoC Hardware
Designing with ALTERA SoC Hardware Course Description This course provides all theoretical and practical know-how to design ALTERA SoC devices under Quartus II software. The course combines 60% theory
JTAG and I 2 C on ELMB
JTAG and I 2 C on ELMB Henk Boterenbrood NIKHEF, Amsterdam Nov 2000 Version 0.3 ABSTRACT The ELMB is designed as a general-purpose plug-on module for distributed monitoring and control applications in
FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
Design and Test Solutions for Networks-on-Chip. Jin-Ho Ahn Hoseo University
Design and Test Solutions for Networks-on-Chip Jin-Ho Ahn Hoseo University Topics Introduction NoC Basics NoC-elated esearch Topics NoC Design Procedure Case Studies of eal Applications NoC-Based SoC Testing
Overview of SOC Architecture design
Computer Architectures Overview of SOC Architecture design Tien-Fu Chen National Chung Cheng Univ. SOC - 0 SOC design Issues SOC architecture Reconfigurable System-level Programmable processors Low-level
Aeroflex Colorado Springs Application Note
Synchronous SRAM (SSRAM) JTAG Operation Table : Cross Reference of Applicable Products Product Name: Manufacturer Part Number SMD # Device Type Internal PIC #. Overview 64Mbit Synchronous SRAM UT8SP2M32
Fujitsu System Applications Support. Fujitsu Microelectronics America, Inc. 02/02
Fujitsu System Applications Support 1 Overview System Applications Support SOC Application Development Lab Multimedia VoIP Wireless Bluetooth Processors, DSP and Peripherals ARM Reference Platform 2 SOC
Introduction to System-on-Chip
Introduction to System-on-Chip COE838: Systems-on-Chip Design http://www.ee.ryerson.ca/~courses/coe838/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University
SCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE (JTAG) Port
Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop
Microprocessors, Lecture 1: Introduction to Microprocessors
Microprocessors, Lecture 1: Introduction to Microprocessors Computing Systems General-purpose standalone systems (سيستم ھای نھفته ( systems Embedded 2 General-purpose standalone systems Stand-alone computer
New and Emerging JTAG Standards: Changing the Paradigm of Board Test (A tutorial)
New and Emerging JTAG Standards: Changing the Paradigm of Board Test (A tutorial) Artur Jutman November 23 th, 2010 Drammen, NORWAY Presentation Outline Introduction Overview of the standards IEEE 1149.7
The S6000 Family of Processors
The S6000 Family of Processors Today s Design Challenges The advent of software configurable processors In recent years, the widespread adoption of digital technologies has revolutionized the way in which
Overview of Microcontroller and Embedded Systems
UNIT-III Overview of Microcontroller and Embedded Systems Embedded Hardware and Various Building Blocks: The basic hardware components of an embedded system shown in a block diagram in below figure. These
BOUNDARY-SCAN: AN INTRODUCTION. by James Stanbridge, Sales Manager of JTAG Technologies
BOUNDARY-SCAN: AN INTRODUCTION by James Stanbridge, Sales Manager of JTAG Technologies Once considered to be something of a black art, and solely an aid to manufacturing, boundary-scan is coming of age
SCANSTA111. SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE (JTAG) Port. Literature Number: SNLS060J
SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port Literature Number: SNLS060J Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port General Description The SCANSTA111
microsparc-iiep TM Introduction to JTAG Boundary Scan
microsparc-iiep TM Introduction to JTAG Boundary Scan White Paper Introduction Historically, most Print Circuit Board (PCB) testing was done using bed-of-nail in-circuit test equipment. Recent advances
Design-for-Test and Test Optimization. Techniques for TSV-based 3D Stacked ICs
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs by Brandon Noia Department of Electrical and Computer Engineering Duke University Date: Approved: Krishnendu Chakrabarty, Supervisor
POLITECNICO DI TORINO Repository ISTITUZIONALE
POLITECNICO DI TORINO Repository ISTITUZIONALE A Hierachical Infrastrucutre for SOC Test Management Original A Hierachical Infrastrucutre for SOC Test Management / Benso A.; Di Carlo S.; Prinetto P.; Zorian
Intelop. *As new IP blocks become available, please contact the factory for the latest updated info.
A FPGA based development platform as part of an EDK is available to target intelop provided IPs or other standard IPs. The platform with Virtex-4 FX12 Evaluation Kit provides a complete hardware environment
Scalable Controller Based PMBIST Design For Memory Testability M. Kiran Kumar, G. Sai Thirumal, B. Nagaveni M.Tech (VLSI DESIGN)
Scalable Controller Based PMBIST Design For Memory Testability M. Kiran Kumar, G. Sai Thirumal, B. Nagaveni M.Tech (VLSI DESIGN) Abstract With increasing design complexity in modern SOC design, many memory
Introduction. Sungho Kang. Yonsei University
Introduction Sungho Kang Yonsei University Outline VLSI Design Styles Overview of Optimal Logic Synthesis Model Graph Algorithm and Complexity Asymptotic Complexity Brief Summary of MOS Device Behavior
System Level Instrumentation using the Nexus specification
System Level Instrumentation using the Nexus 5001-2012 specification Neal Stollon, HDL Dynamics Chairman, IEEE 5001 Nexus Forum neals@hdldynamics.com nstollon@nexus5001.org HDL Dynamics SoC Solutions System
TAP Expander Blackhawk Emulator Expansion Pod. Document Part Number: REV B
CORELIS TAP Expander TAP Expander Blackhawk Emulator Expansion Pod User s Manual Document Part Number: 70397 REV B Copyright 2008 Corelis Inc. 13100 Alondra Blvd. Suite 102 Cerritos, CA 90703-2262 Telephone:
Design and Optimization of Test Architecture for IP Cores on SoC Based on Multi-objective Genetic Algorithm
JOURNAL OF COMPUTERS, VOL. 8, NO. 2, FEBRUARY 2013 517 Design and Optimization of Test Architecture for IP Cores on SoC Based on Multi-obective Genetic Algorithm Enmin Tan Guilin University of Electronic
Digital Systems Design. System on a Programmable Chip
Digital Systems Design Introduction to System on a Programmable Chip Dr. D. J. Jackson Lecture 11-1 System on a Programmable Chip Generally involves utilization of a large FPGA Large number of logic elements
IC Testing and Development in Semiconductor Area
IC Testing and Development in Semiconductor Area Prepare by Lee Zhang, 2004 Outline 1. Electronic Industry Development 2. Semiconductor Industry Development 4Electronic Industry Development Electronic
! Program logic functions, interconnect using SRAM. ! Advantages: ! Re-programmable; ! dynamically reconfigurable; ! uses standard processes.
Topics! SRAM-based FPGA fabrics:! Xilinx.! Altera. SRAM-based FPGAs! Program logic functions, using SRAM.! Advantages:! Re-programmable;! dynamically reconfigurable;! uses standard processes.! isadvantages:!
SCANSTA112 Designers Reference
SCANSTA112 Designers Reference Introduction The SCANSTA112 is the third device in a series that enable multi-drop address and multiplexing of IEEE-1149.1 scan chains. The 'STA112 is a superset of its predecessors
Zynq-7000 All Programmable SoC Product Overview
Zynq-7000 All Programmable SoC Product Overview The SW, HW and IO Programmable Platform August 2012 Copyright 2012 2009 Xilinx Introducing the Zynq -7000 All Programmable SoC Breakthrough Processing Platform
L2: FPGA HARDWARE : ADVANCED DIGITAL DESIGN PROJECT FALL 2015 BRANDON LUCIA
L2: FPGA HARDWARE 18-545: ADVANCED DIGITAL DESIGN PROJECT FALL 2015 BRANDON LUCIA 18-545: FALL 2014 2 Admin stuff Project Proposals happen on Monday Be prepared to give an in-class presentation Lab 1 is
Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE
FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6 ACCESS IC LAB Outline Concepts of Xilinx FPGA Xilinx FPGA Architecture Introduction to ISE Code Generator Constraints
What Do Embedded Instruments Look Like? Jeff Rearick, Agilent Technologies
What Do Embedded Instruments Look Like? Jeff Rearick, Agilent Technologies Outline! IEEE P1687 Background! HSSIO Background! Embedded Instruments for HSSIO! P1687-based HSSIO Characterization Results!
Early Design Review of Boundary Scan in Enhancing Testability and Optimization of Test Strategy
Early Design Review of Boundary Scan in Enhancing Testability and Optimization of Test Strategy Sivakumar Vijayakumar Keysight Technologies Singapore Abstract With complexities of PCB design scaling and
Copyright 2016 Xilinx
Zynq Architecture Zynq Vivado 2015.4 Version This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able to: Identify the basic building
The Design of a Debugger Unit for a RISC Processor Core
Rochester Institute of Technology RIT Scholar Works Theses Thesis/Dissertation Collections 3-2018 The Design of a Debugger Unit for a RISC Processor Core Nikhil Velguenkar nv8840@rit.edu Follow this and
Lecture 28 IEEE JTAG Boundary Scan Standard
Lecture 28 IEEE 49. JTAG Boundary Scan Standard Motivation Bed-of-nails tester System view of boundary scan hardware Elementary scan cell Test Access Port (TAP) controller Boundary scan instructions Summary
ARM Processors for Embedded Applications
ARM Processors for Embedded Applications Roadmap for ARM Processors ARM Architecture Basics ARM Families AMBA Architecture 1 Current ARM Core Families ARM7: Hard cores and Soft cores Cache with MPU or
Hardware Reference. DIL/NetPC DNP/9265 Board Revision 1.0
DIL/NetPC DNP/9265 Board Revision 1.0 Hardware Reference SSV Embedded Systems Dünenweg 5 D-30419 Hannover Phone: +49 (0)511/40 000-0 Fax: +49 (0)511/40 000-40 E-mail: sales@ssv-embedded.de Document Revision:
Universität Dortmund. IO and Peripheral Interfaces
IO and Peripheral Interfaces Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: Microprocessor 8,16,32 bit architecture Usually simple in-order microarchitecture,
l Some materials from various sources! Soma 1! l Apply a signal, measure output, compare l 32-bit adder test example:!
Acknowledgements! Introduction and Overview! Mani Soma! l Some materials from various sources! n Dr. Phil Nigh, IBM! n Principles of Testing Electronic Systems by S. Mourad and Y. Zorian! n Essentials
A Built-in Self-Test for System-on-Chip
A Built-in Self-Test for System-on-Chip Rashid Rashidzadeh University of Windsor Digital 1 Objective : Design an intellectual property (IP) core which enables low speed Automatic Test Equipment (ATE) to
P-ROC. Pinball Remote Operations Controller. Version 2.4 August 8, Copyright 2017, Multimorphic, Inc. 1/28
P-ROC Pinball Remote Operations Controller Version 2.4 August 8, 2017 Copyright 2017, Multimorphic, Inc. 1/28 Table of Contents 1 Introduction... 3 2 Block Diagram... 4 3 Theory of Operation... 6 4 Functional