Mentor Graphics Tools for DFT. DFTAdvisor, FastScan and FlexTest

Transcription

1 Mentor Graphics Tools for DFT DFTAdvisor, FastScan and FlexTest 1

2 DFT Advisor Synthesis tool capable of doing DRC, Scan Insertion and Test point Synthesis Creates a do file and a test procedure file after scan insertion Supports identification and insertion of full scan, partial scan, partition scan and test points Supports mux scan, clocked scan or LSSD Supports both manual and automatic scan identifications Accepts most of the gate level netlist formats 2

3 DFT Advisor what it does? Design flattening Circuit Learning & Testability Analysis DFT Rules Check ( DRC ) Scan structure identification and insertion Generate output files (dofile and testprocedure file) 3

4 DFT Advisor output files It generates 3 files: A new netlist with scan cells inserted 4 do_file, which provides circuit setup and scan circuitry information, used by fastscan /flextest for Automatic Test Pattern Generation test_procedure file, which contains cycle based procedures and timing definitions, used by fastscan/flextest, to operate the scan structures within a design

5 DFT Advisor Flow DFT Advisor : 2. Setup 3. DRC 4. Test Structure Identification 5. Test Structure Insertion 6. Write Results 5

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27 DFT Advisor commands for Full scan SETUP > add clocks 0 /CK SETUP > set system mode dft DFT > setup scan identification full_scan DFT > setup test_point identification control 0 observe 0 noverbose DFT > run DFT > insert test logic scan on test_point on ram on DFT > report statistics DFT > write netlist /project/mtech/../s27_fs.v verilog DFT > write atpg setup /project/mtech/../s27_fs.v Note: Exit of SETUP mode triggers three major operations : 1. Flattening of design model, 2. Performing learning analysis on the flattned model and 3. If the design passes DRC, the system enters into ATPG mode 27 procfile Performing DFT rules check.

28 Fastscan Fastscan is the full scan ATPG tool Offers high fault coverage and good run time Supports testing of stuck at faults, iddq, transition faults Automatically generates test patterns Runs patterns for good & fault simulations Generates test reports Uses random patterns for fault simulation and stops when a pattern fails to detect atleast 0.5% of remaining faults And then uses deterministic patterns to detect remaining faults which have a very low chance of detection by random patterns 28

29 Fast Scan Flow 2. Setup 3. DRC 4. Configuration ( use defaults ) 5. Pattern Generation 6. Fault Simulation 7. Good Simulation 8. Analysis of results 29

30 Fastscan full scan commands SETUP > SETUP > SETUP > SETUP > ATPG > ATPG > ATPG > ATPG > ATPG > FAULT > FAULT > FAULT > FAULT > GOOD > GOOD > GOOD > 30 add clocks 0 /CK add scan groups grp1 /project/mtech/../s27_fs.v.testproc add scan chains chain1 grp1 /scan_in1 /scan_out1 set system mode atpg add faults all run report statistics save patterns /project/mtech/../s27_fs.v.pattern set system mode fault set pattern source external /project/../s27_fs.v.pattern ascii run report statistics set system mode good set pattern source external /project/../s27_fs.v.pattern ascii run exit discard

31 Flextest Flextest is a non scan to full scan tool It is most suited for testing designs with few or no inserted test structures Supports partial scan and partition scans ( partial scan is extremely useful in situations where the design cannot accomodate any extra delay added to the critical path, due to added scan elements delay; those flip flops in the critical path can be excluded in the partial scan ) Automatically generates test patterns Runs patterns for good & fault simulations Generates fault analysis reports 31

32 Flextest has capabilities for inserting test logic circuitry on uncontrollable pins like set, reset, tristate enable and RAM read/write controls Flextest uses a proprietory sequential ATPG algorithm called BACK 32

33 DFT Advisor commands for partial scan Insertion SETUP > add clocks 0 /CK SETUP > set system mode dft DFT > setup scan identification sequential atpg internal percent 90 controllability 100 observability 100 cycle 16 time 100 DFT > DFT > DFT > DFT > DFT > DFT > 33 min_detection 0.01 backtrack 30 setup test_point identification control 0 observe 0 noverbose run insert test logic scan on test_point on ram on write netlist /project/mtech/../s27_ps.v verilog write atpg setup /project/mtech/../s27_ps.v procfile exit discard

34 Flextest commands for partial scan testing SETUP > add clocks 0 /CK SETUP > add scan groups grp1 /project/mtech/../s27_ps.v.testproc SETUP > add scan chains grp1 /scan_in1 /scan_out1 SETUP > set test cycle 2 SETUP > add pin constraints /CK SR SETUP > set system mode drc DRC > set system mode atpg ATPG > set fault type stuck ATPG > add faults all ATPG > run ATPG > save patterns /project/mtech/s27_ps.v.pattern profile ascii cell_placement bottom parallel begin 0 all_test ATPG > report statistics ATPG > set system mode fault FAULT > set pattern source external /project/mtech/../s27_ps.v.pattern ascii 34

35 Flextest commands for partial scan testing contd. FAULT > run FAULT > report statistics FAULT > set system mode good GOOD > set pattern source external project/mtech/../s27_ps.v.pattern ascii GOOD > run GOOD > exit discard 35 /

36 Thank You!! 36