isplsi 8000 and 8000V Family Architectural Description

Transcription

1 October 21 Introduction The of Register-Intensive, SuperBIG In-System Programmable Logic evices is based on Big Fast Megablocks of 12 registered macrocells and a Global Routing Plane (GRP) structure interconnecting the Big Fast Megablocks. Each Big Fast Megablock contains 12 registered macrocells arranged in six groups of 2, a group of 2 being referred to as a Generic Logic Block, or GLB. Within the Big Fast Megablock, a interconnects the six GLBs to each other and to 24 Big Fast Megablock I/O cells with optional I/O registers. The Global Routing Plane which interconnects the Big Fast Megablocks has an additional 144 global I/Os with optional I/O registers. Outputs from the GLBs in a Big Fast Megablock can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. Switching resources are provided to allow signals in the Global Routing Plane to drive any or all the Big Fast Megablocks in the device. This mechanism allows fast, efficient connections, both within the Big Fast Megablocks and between them. Figure 1. isplsi 884 and 884V Functional Block iagram Global Routing Plane (GRP) with Tristate Bus Lines 1 8karch_6

2 Figure 2. isplsi 8 and 8V GLB I/O Big Fast Megablock Input Tracks AN Array Input Routing General Purpose Big Fast Megablock Input Tracks Feedback Inputs 2 PT PT 1 PT 2 PT 3 43 Product Term Sharing Array Macrocell Shared PT 4 PT 5 PT 6 PT 7 Macrocell 1 Shared 1 PT 8 PT PT 1 PT 11 Fully Populated AN Array Macrocell 2 Shared 2 PT 12 PT 13 PT 14 PT 15 Macrocell 3 Shared 3 To interconnect PT 76 PT 77 PT 78 PT 7 PT 8 Macrocell 1 Shared 1 PT 81 To Output Control MUX Note: Macrocells and 1 do not support Tristate Bus Feedback. Function Selector (E 2 Cell Controlled) 2

3 Generic Logic Block Each GLB contains 2 macrocells and a fully populated, programmable AN-array with 8 general purpose logic product terms. The GLB has 44 inputs which are available in both true and complement form for every product term can be driven from both BRP and GRP. Up to 2 of these inputs can be driven from the local feedback of the GLB for logic functions that require fast feedback. The 8 general purpose product terms can be grouped in 2 sets of four and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 28 product terms for a single macrocell function. Alternatively, the PTSA can be bypassed for functions of four product terms or less. Macrocell The 2 registered macrocells in the GLB are driven by the 2 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch/toggle flip-flop and the necessary clocks and control logic to allow combinatorial or registered operation. The macrocells each have two outputs, one output can be fed back inside the GLB to the AN-array, while the other output drives both the Big Fast Megablock Routing Pool and the Global Routing Plane. This dual or concurrent output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function feeding more complex logic functions elsewhere in the chip. Macrocell registers can be clocked from one of several global, local or product term clocks available on the device. A global, local and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers. Reset and preset for the macrocell register is provided from both global and product term signals. The polarity of all of these control signals is selectable on an individual macrocell basis. The macrocell register can be programmed to operate as a -type register, a -type latch or a T-type flip-flop. Figure 3. isplsi 8 and 8V Macrocell isplsi 8 isplsi 8V * Feedback to AN Array PTSA To Big Fast Megablock or Global Interconnect Global Clock Enable Clk En To Specific Global Tristate Bus* Global Clock Global Clock 1 Global Clock 2 R R/L P From Macrocell or 1 GRST Reset pin GRST To All Macrocells and I/O Cells Preset/Reset Input has Global Polarity Control From PT8 *Not available for Macrocells and 1. : Function Selector (E 2 Cell Controlled) 3

4 Embedded Tristate Bus The Global Routing Plane (GRP) includes a 18-line embedded internal tristate bus that enables multiple GLBs to drive the same tracks. This bus can be partitioned into various bus widths such as twelve -line buses, six 18-line buses or three 36-line buses. The GLBs can dynamically share a subset of the Global Routing Plane tracks. This feature eliminates the need to convert tristate buses to wide multiplexers on the programmable device. Up to 18 macrocells per GLB can participate in driving the embedded tristate bus. The remaining two macrocells per GLB are used to generate the internal tristate driver control signals on each data byte (with parity). The embedded tristate bus can also be configured as an extension of an external tristate bus using the bidirectional capability of the I/O cells connected to the Global Routing Plane. The Global Routing Plane I/Os -8 and from each group (I/OGx as defined in the I/O Pin Location Table) can connect to the internal tristate bus as well as the unidirectional/non-tristate global routing channels. I/Os -14 connect only to the global routing channel. The embedded tristate bus has internal bus hold and arbitration features in order to make the function more user friendly. The bus hold feature keeps the internal bus at the previously driven logic state when the bus is not driven to eliminate bus float. The bus arbitration is performed on a first come, first served priority. In other words, once a logic block drives the bus, other logic blocks cannot drive the bus until the first releases the bus. This arbitration feature prevents internal bus contention when there is an overlap between two bus enable signals. Typically, it takes about 3ns to resolve one bus signal coming off the bus to another bus signal driving the bus. The arbitration feature combined with the predictability of CPL, makes the embedded tristate bus the most practical for the real world bus implementations. Figure 4. Embedded Tristate Bus Global I/O Cells GLB 1 BFM 1 Global Routing Pool BFM n Global I/O Cells I/O G <-8> I/O G <15-23> I/O G1 <-8> I/O G1 <15-23> GLB 2 GLB 1 GLB 2 GLB 3 GLB 3 I/O G2 <-8> I/O G2 <15-23> I/O G3 <-8> I/O G3 <15-23> GLB 4 GLB 4 GLB 5 GLB 5 I/O G4 <-8> I/O G4 <15-23> I/O G5 <-8> I/O G5 <15-23> GLB 6 GLB 6 Tristate Bus Lines 4

5 I/O Cell and I/O Controls Control signals for the I/O cell registers are generated using an extra product term within each GLB, or using dedicated input pins. Each GLB has two extra product terms beyond the 8 general purpose available for the macrocell logic. The first additional product term is used as an optional shared product term clock for all the macrocells within the GLB. The second additional product term is then routed to an I/O using a separate routing structure from the Big Fast Megablock Routing Pool and Global Routing Plane. Use of a separate control bus routing structure allows the I/O registers to have many high-speed control signals with no impact on the interconnection of the GLBs and Big Fast Megablocks. The I/O is split into four quadrants, each servicing the I/O cell control requirements for one edge of the device. Signals in the control bus can be independently selected by any or all I/O cells to act as clock, clock enable, output enable, reset or preset. Each Big Fast Megablock has 24 I/O cells. The Global Routing Pool has 144 I/O cells. Each I/O cell can be configured as a combinatorial input, combinatorial output, registered input, registered output or bidirectional I/O. I/O cell registers can be clocked from one of several global, local or product term clocks which are selected from the I/O control bus. A global and product term clock enable is also provided, eliminating the need for the user to gate the clock to the I/O cell registers. Reset and preset for the I/O cell register is provided from both global and product term signals. The polarity of all of these control signals is selectable on an individual I/O cell basis. The I/O cell register can be programmed to operate as a -type register or a -type latch. Figure 5. I/O Cell TOE VCCIO VCCIO VCCIO GLOBAL OE GLOBAL OE1 GLOBAL OE2 GLOBAL OE3 Multiplexed Output From Big Fast Megablock Track Big Fast Megablock I/O Pad GLOBAL I/O CLOCK ENABLE CLKEN Slew Open Rate rain isplsi 8V GLOBAL CLOCK GLOBAL CLOCK2 isplsi 8 GLOBAL I/O CLOCK GLOBAL I/O CLOCK1 UARANT I/O CLOCK R/L To Specific Big Fast Megablock or Global Tracks To Specific Global Tristate Bus P R Global I/O Cell Only GRST : Function Selector (E 2 Cell Controlled) 5

6 Clock istribution The isplsi 8 and 8V family has several clock inputs from which the GLB and the I/O cell register clocks can be driven. There are three Global Clocks (CLK-2), two Global I/O Clocks (GIOCLK-1 for isplsi 8 Family only), and four uadrant Clocks (IOCLK-3). In addition to the clock inputs, there is one GLB clock enable (CLKEN) and one I/O clock enable (IOCLKEN). The clock polarity can be selected at the individual register. The GLB global clocks can be used as master clocks which have the lowest internal clock skew. Global Clock and Global Clock2 in the isplsi 8V Family are also capable of driving the I/O register clocks. Similarly, the quadrant clocks are divided to drive each quadrant s I/Os (defined in the individual data sheets) with minimum clock skew. Boundary Scan In-System Programming (ISP ) of the device is performed via IEEE114.1 compliant JTAG state machine or Lattice ISP state machine for the isplsi 8 family. The BSCAN/ispEN pin selects between the two protocols. The four-wire interface on the isplsi 8 Family includes Test ata In (TI)/Serial ata In (SI), Test Clock (TCK)/Serial Clock (SCLK), Test Mode Select (TMS)/Mode Control (MOE), and Test ata Out (TO)/Serial ata Out (SO). ISP program enable and disable is controlled by the private programming instruction set for the ispjtag interface and by the BSCAN/ispEN pin for the ISP interface. The EPEN signal, when high, enables the Test Access Port (TAP) for programming and test for the isplsi 8V Family. The isplsi 8V Family provides the dedicated four-wire interface via TI, TO, TMS and TCK. In addition to ISP programming, the JTAG state machine also provides standard boundary scan test capability. Standard boundary scan instructions supported are Sample/Preload, Extest, Bypass and High-Z instructions. The boundary scan test registers associated with each of the I/O pins control the state of the I/O pin when the device is not in normal functional mode. This feature allows users to define the state of the I/O pins during test and ISP programming modes. Figure 6. Boundary Scan Register for I/O Pins SCANIN (from previous cell) BSCAN Registers EXTEST PROG_MOE BSCAN Latches HIGHZ TOE Normal Function OE 1 EXTEST PROG_MOE Normal Function 1 I/O Pin SCANOUT (to next cell) Shift R Clock R Update R Reset 6

7 Figure 7. Boundary Scan Register for edicated Input Pins Input Pin SCANIN (from previous cell) SCANOUT (to next cell) Shift R Clock R Timing Model The task of determining the timing through the isplsi 8 and 8V family, just as any CPL, is relatively simple. The device timing model provided in Figure 8 shows the specific delay paths. Once the implementation of a given function is determined either conceptually or from the Fitter/Place and Route software report file, the delay path of the function can easily determined from the timing model. The software timing analyzer reports the timing delays based on the same timing model for a particular design. Note that the internal timing parameters are given for reference only, and are not tested. The external timing parameters are tested and guaranteed for every device. Figure 8. isplsi 8 and 8V Simplified Timing Model I/O pad Input pad Input Buffer and I/O Cell Register #6, t bcom Output #7, t breg buffer Output routing #71, t delays gcom I/O register delays #72, t greg #34, t odreg #25, t obp Output path #35, t odcom #26, t ibp Input path #36, t odz Input buffer #27, t iolat delays #28, t ioco #61, t #2, t iosu BFM Routing Pool bfmi #67, t bfmg #23, t idcom #64, t #24, t idreg #3, t bfmm ioh #31, t z iorst GLB/ #32, t Local feedback iosuce Macrocell Toggle feedback #33, t iohce #54, t floc isplsi 8 Family only #53, Global PTSA t Mcell register Routing ftog #41, t 1pt #45, t Plane #42, t mbp AN array 4ptcom #46, t #43, t mlat 4ptreg #3, #47, t #62, t #44, t mco grpi t ptsa andhs #48, t msu #63, t grpiz PT Mcell controls #4, t mh #65, t grpm #4, #55, t #5, t #66, t t pck mrst grpmz andlp #56, t pcken #51, t msuce #68, t grpb #57, t sck #52, t mbce #58, t scken Bus direct #5, t prst #6, t rdir PT I/O control bus Global control delay #78, t #73, t piock gck #74, t #7, t piocken gcken #75, t #8, t poe giock #76, t #81, t piorst giocken #77, t pioz #82, t qck #83, t goe #84, t toe #85, t gmrst #86, t giorst 8K_Model.eps Output slew rate adders #37, t slf #38, t sls I/O pad 7