Application Brief 117 Barrel Shifters in FLEX 8000 Devices. May 1994, ver. 2 Application Brief 117. Product Term v Speed 16 Bits v Area 32 Bits

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1 pplication rief 117 arrel Shifters in FLEX 8000 evices arrel Shifters in FLEX 8000 evices May 1994, ver. 2 pplication rief 117 Summary Files using the techniques described in this application brief are available from the ltera S at (408) in the following self-extracting file: arrel shifters are circuits that perform a binary shift on a given input. Unlike a conventional shifter, which shifts data bits one position to the right or left, a barrel shifter can shift data to any position. ata bits shifted out at one end of a barrel shifter re-appear at the other end. This application brief describes two barrel shifter designs that are optimized for the FLEX 8000 architecture: one is optimized for area, the other is optimized for speed. esign techniques described in this application brief can be used to create design files optimized for the following characteristics (numbers in parentheses are for the speed-optimized barrel shifter): ab_117.exe esign Goals: esign Results: rchitecture Optimization Width Logic ells Speed (MHz) v Look-Up Table Routability 8 its 24 (38) 32.2 (98) Product Term v Speed 16 its v rea 32 its rea-optimized arrel Shifter Table 1 shows the truth table for an 8-bit barrel shifter that is optimized for area. This design has 8 data bits, a[7..0], and 3 shift control bits, s[s..0]. In this shifter, any shift greater than 7 can be performed by letting s[2..0] = n mod 7, where n is the number of shifts. pplications Table 1. Truth Table for 8-it arrel Shifter S2 S1 S Number of Shifts ltera orporation Page 203

2 arrel Shifters in FLEX 8000 evices pplication rief 117 right barrel shift of 6 positions on the byte ' ' can be described as follows: if S2 = 1, S1 = 1, S0 = 0, and [7..0] = , the output of the circuit is [7..0] = In this example, the two leftmost bits of the input byte have been shifted to the two rightmost positions. See Figure 1. Figure 1. 8-it arrel Shifter S0 S1 S Page 204 ltera orporation

3 pplication rief 117 arrel Shifters in FLEX 8000 evices The barrel shifter design in Figure 1 consists of eight 2-to-1 multiplexers arranged into 3 rows with 8 multiplexers per row. Each row of multiplexers has a common select line where S0 feeds the first row, S1 the second, and S2 the third. 1 in the first row (S0 = 1) represents a shift of one bit to the right. When S1 = 1, the data is shifted by 2 bits; when S2 = 1, the data is shifted by 4 bits. When any of the shift control bits are zero, data is passed through the row of multiplexers to the next row. For example, when S0 = 1, the first row of multiplexers shifts one space to the right; when S1 = 0, the second row of multiplexers passes straight down without shifting; when S2 = 1, the third row of multiplexers shifts four spaces to the right. With these inputs, the total shift in Figure 1 is five positions. Speed- Optimized arrel Shifter The speed-optimized barrel shifter design builds upon the first design and uses pipelining for synchronizaton. In pipelining, registers are inserted between combinatorial logic, decreasing register-to-register delays and increasing operating frequency. The second design is partitioned into stages with a register inserted between each intermediate stage. In this case, an intermediate stage corresponds to a shift performed by a single row. Figure 2 shows an 8-bit pipelined barrel shifter created by inserting registers before each row of multiplexers. [7..0] is registered before feeding the first 2-to-1 multiplexer. When pipelining a design, you must insert the pipelining registers so that the correct inputs correspond to the correct data byte at each stage. In Figure 2, S2 requires three pipeline registers, S1 requires two, and S0 requires one for its row of multiplexers. With pipelining, this design runs at 98 MHz. For more information about pipelining, refer to pplication Note 36 (esigning with FLEX 8000 evices) in this handbook. pplications ltera orporation Page 205

4 arrel Shifters in FLEX 8000 evices pplication rief 117 Figure 2. 8-it arrel Shifter with Pipelining [7..0] 8 LK S1 8-it 2-to-1 8-it Register S2 8-it 2-to-1 8-it Register S3 8-it 2-to-1 8-it Register 8 [7..0] Page 206 ltera orporation

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