Programmable Peripheral Application Note 021 Interfacing The PSD3XX To The MC68HC16 and The MC68300 Family of Microcontrollers By Ching Lee

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1 Programmable Peripheral pplication Note 0 Interfacing The PSXX To The MC68HC16 and The MC680 Family of Microcontrollers By Ching Lee Introduction Typical MC683 Design The PSXX devices are user-configurable microcontroller peripherals which offer an ideal solution for embedded control applications. The PSXX family provides basic building blocks to microcontroller based designs including I/O ports, logic replacement, programmable address decoder (PD), Memory Page Register, 2K bytes of SRM and up to 128K bytes of EPROM. Please consult pplication Note 011 for detail features and operations. In this pplication Note we will demonstrate how the PSXX interfaces to the 16-bit MC68HC16 and the MC680 family of -bit microcontrollers from Motorola. The MC680 family includes microcontrollers such as the MC680, MC683, MC683 and MC These devices share a common MC680 CPU core. lthough the MC68HC16 is not a member of the family, it does have a MC680 type bus interface and timing. The MC683 will be chosen as the microcontroller used with the PSXX device in this pplication Note, but the description applies to other members of the group as well. typical MC683 design consists of two EPROMs, two SRMs, an I/O block and glue logic. The complexity of the I/O block and glue logic depends on the application. Figure 1 shows the block diagram of such a design. The MC683 Bus Interface Before interfacing the PSXX to the MC683, we have to understand the MC683 bus and the bus features. rea's of interest to the PSXX interface are discussed in the following sections. ddress Bus The MC683 bus has non-multiplexed address lines (0 ). ddress lines 19 can be selected either as address lines or as chip select signals (CS6 CS10) at reset time. Data Bus The data bus (5 ) is a non-multiplexed bus which transfers 8 or 16 bits of data. The processor supports byte, word, and long word operands. The MC683 transfers the even data byte (with 0 = 0) through 5, and the odd byte (with 0 = 1) through. Table 1 shows the different data transfer cases for a 16- bit bus, and the status of the control signals involved in the bus cycles. For byte transfer, the positioning of the byte is determined by address 0. OP0 refers to the most significant byte of a word operand, and OP1 is the least significant byte. Operands in parentheses are ignored during read cycles, but are driven by the processor during write cycles. Misaligned words are not supported by the MC683. Table 1. MC683 Data Transfer On 16-Bit (Word) Port Transfer SIZ1 SIZ0 0 CK1 CK2 5 Upper Byte (even) X OP0 (OP0) Lower Byte (odd) X (OP0) OP0 Word (aligned) X OP0 OP1 Long Word (aligned) X OP0 OP1 Return to Main Menu 1-191

2 PSXX pplication Note 0 The MC683 Bus Interface (cont.) Figure 1. MC683 System Block Diagram 0 18 EPROM EPROM SRM SRM MC680 MC683 MC683 MC68340 MC68HC16 5 CS0 RMCS 5 5 SIZ CS1 WRL WRH LTCH I/O PL CTRL OUT 0 I/O PORTS CTRL OUT 1 5 CTRL OUT 2 CTRL OUT 3 CTRL OUT

3 PSXX pplication Note 0 The MC683 Bus Interface (Cont.) Chip Select Logic The MC683 provides 12 chip select output signals ( and CS0 CS10). CS0 CS10 are multiplexed with other signals and default to chip select mode during reset. The chip select signals are user-programmable, flexible and powerful. The following list outlines some of the options/features which can be programmed into any chip select signal: 1. Base ddress: Specify base address and block size. 2. Mode Option: Select asynchronous/synchronous bus mode. 3. Byte Option: Specify upper byte, lower byte, or both. 4. Read/Write Option: Specify read or write bus cycle. 5. Strobe Option: Specify CS signal to be synchronized with the or S signal. 6. CK Option: Specify internal/external source of the CK signal. If internal CK is specified, then select the number of wait states. fter system reset, CS0 CS10 lines are disabled since they should not select any device until the system is configured. But has a default reset value such that it can be used to enable a boot PROM, or PSXX in this case. The other chip selects are then initialized by the boot program. may or may not be re-programmed to a different value. The reset value of the signal is listed in Table 2. Table 2. Reset Value Fields/Option Reset Values Base ddress Block Size synchronous/synchronous Mode Upper/Lower Byte Read/Write Strobe CK ddress Space Interrupt Priority Level utovector 1M Byte synchronous Mode Both Bytes Read/Write S 13 Wait States Supervisor/User ny Level Interrupt Vector Externally Typical MC683 Design With PSXX s seen in the typical MC683 design block diagram in Figure 1, the basic building blocks include EPROMs, SRMs, a PL, and I/O port. The PSXX will replace all or most of these blocks. Depending on the amount of EPROM and SRM space and the I/O port requirement, one or two PSXX devices can be used. The two PSXX system does have a different interface to the MC683 than a single PSXX design. The two designs will be discussed separately

4 PSXX pplication Note 0 The Two PSXX Design Figure 2 shows a two PSXX implementation of a typical MC683 system. In this design the PS12s replace the EPROMs, the SRMs, the PL, and the I/O port in the typical design. The two PS12 devices provide 128K bytes of EPROM and 4K bytes of SRM. Two PS13's can be used if more EPROM space is needed. The configurations of the two PS12's in this design are as follow: Bus Width Each PS12 is configured to operate in 8-bit non-multiplexed mode. PSD#1 supplies the even data byte to the processor while PSD#2 supplies the odd data byte. Together they appear to the MC683 as a single 16-bit port. Port Port in a PSXX can be an I/O port, address output latch or as a data port with a non-multiplexed bus. In this design example, Port is configured as a data port. Port of PSD#1 is connected to 5 and PSD#2 is connected to of the processor. Port B Port B can be an I/O port, chip select outputs, or as a data port in a 16-bit non-multiplexed bus. In this design, half of Port B is used to replace the I/O port in the typical design, and the other half is used as logic replacement for the PL. The two B ports together provide two 4-bit I/O ports, and 8 output control signals. Port C Port C can be used as an address/logic input port to the PD, or as chip select outputs. In our case, Port C is used as logic input. Bus Interface The PS12's are configured to interface to a bus with a read/write signal () and a data strobe signal (). Since the MC683 has a non-multiplexed bus, the address strobe (S) input signal is not required by the PS12 to latch the address lines internally. Instead, the S and the CSI/19 pins are used as address input pins to select the internal PS12 sections. The 3 signals which select the PS12's are, CS0 and CS1. The selects the EPROMs. The CS0 selects the even byte SRM and I/O Port B; CS1 selects the odd byte only. No wait states are required if the MC683 is running at a 16 MHz system clock. Please refer to Figure 2 for the bus interface connections. fter reset, selects the PS12's to run the boot program. During this time, the 3 chip select lines can be re-programmed to reflect the correct address range and wait state. This has to be done before the SRMs can accessed. Table 3 shows some typical option values for this application. There is no 4 KB block size option, so 8 KB is assigned to the SRM

5 PSXX pplication Note Figure 2. MC683/Two PS12 Interfacing V CC MC683 PS12 ODD BYTE PS12 EVEN BYTE PSD#1 PSD# _CS6 _CS7 _CS8 _CS9 _CS10 CK0 CK1 CS0 CS1 V CC BHE/PSEN S 19/CSI CS P0 P1 P2 P3 P4 P5 P6 P7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 P0 P1 P2 P3 P4 P5 P6 P7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 BHE/PSEN S 19/CSI CS CTRL OUT 1 CTRL OUT 2 CTRL OUT 0 CTRL OUT 3 I/O PORT I/O PORT I/O PORT I/O PORT CTRL IN 0 CTRL IN 1 CTRL IN 2 CTRL OUT 4 CTRL OUT 5 CTRL OUT 6 CTRL OUT 7 I/O PORT B I/O PORT B I/O PORT B I/O PORT B CTRL IN 3 CTRL IN 4 CTRL IN 5 S SIZ0 SIZ1 BR_CS0 BG_CS1 BGCK_CS2 FC0_CS3 FC1_CS4 FC2_CS5 The Two PSXX Design (cont.)

6 PSXX pplication Note 0 The Two PSXX Design (Cont.) Table 3. Chip Select Option Value Option CS0 CS1 Base ddress Block Size 6 KB 8 KB 8 KB synchronous/synchronous Mode synchronous synchronous synchronous Upper/Lower Byte Both Bytes Upper Byte Lower Byte Read/Write Read Read/Write Read/Write Strobe S S S CK 0 Wait State 0 Wait State 0 Wait State Bus Interface (Cont.) Figure 3 shows the ddress Map for the PSD#1 configuration. In the ddress Map truth table, the 19 column is the input, and the Q.F. S column is the CS0 input. EPROM is selected when is low; SRM or I/O Port B is selected when CS0 is low. The addresses in FILE STRT/FILE STOP columns are shifted right by one to reflect the fact that the input pins on the PS12's are connected actually to the of the MC683. Figure 3. ddress Map Truth Table DDRESS MP SEGMT STRT SEGMT STOP FILE STRT FILE STOP Q. F. S ES0 0 X X X N N 0 1fff 1 ES1 0 X X X N N 00 3fff 1 ES2 0 X X X N N fff 1 ES3 0 X X X N N fff 1 ES4 0 X X X N N fff 1 ES5 0 X X X N N a000 bfff 1 ES6 0 X X X N N c000 dfff 1 ES7 0 X X X N N e000 ffff 1 RS0 1 X X X N/ N/ 0 CSP 1 X X X N/ N/ 0 END 1-196

7 PSXX pplication Note 0 The Two PSXX Design (Cont.) Power Down Mode The PSXX's power down mode is particularly useful in a system which uses a PSXX mostly as a boot PROM. The power down mode is controlled by the input pin 19/CSI. This pin can be configured by the PSDabel portion of PSDsoft as address input (19) or as chip select (CSI). To implement the power down mode to the two-ps12 design, the following changes are required: Configure the 19/CSI pin with the PSDabel portion of PSDsoft as the CSI pin. Connect the pin to the signal. The PSXX's are normally in power down mode except when is asserted. The PSXX has a 10 ns hold time requirement on the CSI input with reference to the trailing edge of the signal. The MC683 does not provide this hold time; designers have to delay the signal to meet this requirement. The signal is programmed to have a block size of 512 KB. This will cover both the EPROM and SRM space. When accessing the SRM, the signal is asserted to take the PSXX out of power down mode. In power down mode, the Port B I/O ports will maintain their output values but the chip select output signals will be inactive. When the is used as CSI input to the PSXX, the access time from CSI valid to data out is 1 ns (PS02-12), 10 ns more than the normal address valid to data out time. This requires and CS0 CS1 to be programmed with one wait state. The Single PSXX Design The single PSXX design is for applications which need less EPROM and SRM space. Figure 4 illustrates the schematic of a PS02 interfacing to the MC683. The PS02 provides 64 KB of EPROM and 2 KB of SRM; Port and Port B are configured as data ports for the MC683. Port C generates the I/O latch signal for the I/O port and two chip select signals. The single PSXX interface to the MC683 is different from the two PSXX design. In order for the PS02 to operate in the 16-bit mode, it needs a Byte High Enable (BHE) signal. If the design has a BHE signal available (generated from decoding to 0 and SIZ0 signals from the MC683), connect it directly to the PS02's BHE pin. or other high address bits are then used to select the PS02. If there is no BHE signal available, the signal can be programmed to provide this function. fter reset, the signal operates as a chip select signal with initial values shown in Table 2. It will serve temporarily as the BHE input to the PS02 until the is programmed as a BHE signal. The programming should be done shortly after reset with the value listed in Table 4. Now that the signal is used as the BHE signal, the PS02 needs other means to select the internal device. Other chip select signals from the MC683 cannot be used since they are inactive at the time of boot up. ddress lines are used instead as decoding address inputs to the PS02 as shown in Figure 4. For example, the EPROM is enabled if are equal to 00H; SRM and I/O Ports are enabled if are equal to 01H. Depending on the application, any other high address bits can be used for this purpose. The PS02 is configured to operate in the 16-bit mode. The high byte is coming from Port B and is connected to on the MC683 data bus. Table 5 shows which port and byte it is driving for different bus cycles. Please note the low byte/high byte definition in the PS02 Data Book is the opposite to that defined in the MC683 User's Manual

8 PSXX pplication Note Figure 4. MC680/PS02 Interface _CS6 _CS7 _CS8 _CS9 _CS S SIZ0 SIZ BHE/PSEN S 19/CSI P0 P1 P2 P3 P4 P5 P6 P7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC V CC BR_CS0 BG_CS1 BGCK_CS2 FC0_CS3 FC1_CS4 FC2_CS5 (BHE) CK0 CK P CS0 P CS1 I/O PORT LTCH I/O PS02 MC683 The Single PSXX Design (cont.)

9 PSXX pplication Note 0 The Single PSXX Design (cont.) Table 4. as BHE Signal Fields/Option Values as BHE Base ddress Block Size 128 K Byte synchronous/synchronous Mode synchronous Mode Upper/Lower Byte Lower Byte (Odd Byte) Read/Write Read/Write Strobe S CK 0 Wait State Table 5. PS02 Data Ports 0 BHE () Port Port B (Even Byte) (Odd Byte) Tri-State 1 0 Tri-State 1 1 Tri-State Tri-State Conclusion s we have seen from the two PSXX design examples, the PSXX's are able to replace at least 6 ICs in the typical 16-bit MC683 design. The PSXX programmable microcontroller peripheral not only provides a cost effective solution to embedded applications, but it also reduces printed circuit board space, power consumption and offers code protection from unauthorized access. PL is a registered trademark of dvanced Micro Devices Corporation. Return to Main Menu 1-199

Programmable Peripheral Application Note 029 Interfacing PSD4XX/5XX To Microcontrollers

Programmable Peripheral Application Note 029 To Microcontrollers By Ravi Kumar Abstract This application note is intended to give the reader a general guideline on how to interface Field Programmable Microcontroller