Introduction to PEEL TM Arrays

Transcription

1 Features ntroduction to PEEL TM s Programmable Electrically Erasable s Programmable Electrically Erasable s Family of medium-density PLs Reprogrammable MOS EEPROM Technology 24, 28, 40 and 44 pins in P, PL, and SO packages Versatile Programmable PL structure with true product-term sharing llows buried logic, registers and latches 40 to 60 registers/latches 40 to 72 logic cell output functions Most Flexible ell of all PLs Multiple output functions per cell,t and JK registers with on the fly selection ndependent or global clocks, resets, presets, programmable clock polarity and output enables ll controls allow sum-of-products logic Overview Programmable Electrically Erasable (PEEL ) s are a family of omplex Programmable evices (PLs) based on T s MOS EEPROM technology. PEEL s free designers from the limitations of ordinary PLs by providing the architectural flexibility and the speed needed for today s programmable logic designs. The PEEL family consists of three parts in 24, 28, and 44 pin packages in plastic P, PL, and SO formats. T s MOS EE technology allows reprogrammability and high-speed performance. Widegate delays as fast as 9ns for internal (buried) and 15ns external (pin to pin) are possible with PEEL s. lock frequencies can be as fast as 76.9MHz for sequential functions. The PEEL architecture is a versatile multi-level programmable logic array (PL) architecture rich in input latches, buried registers and sum-of-product logic functions. The PL logic array structure provides (programmable N, programmable OR) allowing true product term sharing. PEEL s offers more flexible logic and cells than any comparable PL available today. The PEEL logic cell incorporates multiple outputs, allowing PEEL s High-Speed Wide-gate Performance tpd as fast as 9ns/15ns (internal/external) fmax as fast as 76.9MHz deal for ombinatorial, Synchronous and synchronous pplications ntegration of multiple PLs and random logic uried counters, complex state-machines omparators, decoders, multiplexers and other wide-gate functions evelopment and Programmer Support Familiar PL development methodology T PLE evelopment Software Fitters for EL, UPL, and other PL Software Programming support by popular 3rd party programmers registers and combinatorial logic to be buried without limiting the use of pins as with other PLs. cell registers are user-configurable to be true, T and JK registers with independent or global clocks, resets, presets, clock polarity and other special features. ll registers and output enables allow full sum-of-products control. PEEL s are ideal for implementing a wide variety of general purpose combinatorial, synchronous and asynchronous logic applications, including: buried counters, complex state-machines, comparators, decoders, encoders, adders, address and data decoding and other wide-gate logic. ecause PEEL s allow for multi-level buried logic, designs normally requiring multiple PLs or random logic can be efficiently integrated. evelopment support for PEEL s is provided by T and popular third party development tool manufacturers. T offers the powerful PLE evelopment Software complete with architectural editor, logic compiler, and waveform simulator. evelopment with EL, Synario, UPL and Or is accommodated by PEEL fitters from T. Programming for PEEL s is supported by popular third party programmers

2 PEEL s nput Pins nput (N) (O) Pins nput/lock Pins (L) uried functions to cells True product-term sharing for all logic cell sum-terms Multi-function logic cells are equal to 2 or 3 ordinary PL macrocells PEEL rchitecture Overview Figure 1 - PEEL TM rchitecture The primary elements of the PEEL architecture include cells (Os), input cells (Ns), logic control cells (Ls) and a logic array, as illustrated by the architecture diagram in Figure 1. their resources vary relative to the number of inputs, s, logic cells, and array size. The architectural variety of the family efficiently addresses a range of mediumdensity PL applications. Looking at the diagram, input signals to the PEEL are first fed through either cells or input cells, each equipped with a user-configured register/latch. The signals from the and input cells, as well as feedbacks from the logic control cells, are fed to the logic array with both true and complements available. The logic array, incorporates a PL structure with true product term sharing. This allows full sum-of-product logic functions to be fed to each logic control cell. The logic control cells allocate and control the sum-ofproduct functions to implement register and cell functions with clocks, sets, presets and output enables as well as combinatorial and sequential output functions. PEEL logic cells provide multiple outputs (multi-function) that are equivalent to two or three macrocells of ordinary PLs. The multiple outputs ensure that registers and logic functions can be buried and that s can still be used for both inputs and outputs. Finally, the global cells allocate global clock signals and other register control functions for logic control cells and cells. The PEEL Family The PEEL family includes three parts in pincounts ranging from 24 to 44 pins: the P7540, P7536 and P7572. lthough the basic architecture is similar, The newly released P7572, P7540 and P7536 devices are higher performance, lower power and functional equivalent replacements for the P7140, P7024 and P7124 device types. The P7540 lthough smallest in pin count of the PEEL s, the P7540 is by far the most powerful 24-pin PL today. With 20 pins, 2 inputs/global-clock pins and 40 registers/ latches, (20 L, 20 O) the P7540 is suitable for a wide variety of applications, see Figure 2. The P7540 s logic array provides 84 sum-of-product functions that share up to 80 product terms. ts multifunction logic cells have two outputs per cell for a total of 40 output functions (20 of which can be buried). put this in perspective, the popular 22V10 has only 10 non-buried output functions. The P7540 can implement designs that exceed the architectural capabilities of devices such as the 22V10, 20R10, EP610/630, TV750, GL6002, EPM5032. t is also a pin compatible super-set of most other 24-pin PLs. The P7540 has propagation delays as fast as 10ns/15ns (internal/external) and synchronous clocking frequencies to 71MHz. Power consumption is 80m 25MHz (55m typ.). The P7540 is available in 24-pin P, SO and 28-pin PL packages

3 PEEL s 2 nput/ lock Pins /LK1 V 2 84 (42X2) nputs true and complement 20 (O) 20 Pins GN P7540 /LK2 4 sum terms 4 product terms for 80 sum terms (four per L) 20 (L) uried logic 20 functions to cells output functions per cell (40 total output functions possible) Figure 2 - P7540 lock and rchitecture iagrams 2 nput/ lock Pins 12 nput Pins nput (N) (38X2) nputs true and complement 12 (O) 12 Pins /LK1 V nput /LK2 GN 2 sum terms 3 product terms for 48 sum terms (four per L) 12 (L) uried logic 12 functions to cells up to 3 output functions per cell (36 total output functions possible) P7536 Figure 3 - P7536 lock and rchitecture iagrams

4 PEEL s 2 nput/ lock Pins 12 nput Pins nput (N) (62X2) nputs true and complement 24 (O) 24 Pins /LK nput V 4 sum terms 5 product terms for 96 sum terms (four per L) 24 (L) uried logic 24 functions to cells up to 3 output functions per cell (72 total output functions possible) GN P7572 /LK2 Figure 4, P7572 lock and rchitecture iagrams The P7536 With a slightly larger pin count and fewer logic cells than the P7540, the P7536 addresses applications requiring more input pins, fewer output pins and a lower cost. The P7536 architecture consists of 12 pins, 14 input pins and 36 registers/latches (12 L, 12 O, 12 N), see Figure 3. The P7536 logic array provides 50 sum-of-product logic functions that share 64 product terms. The P7536 multi-function logic cells offer up to three outputs per cell for a total of 36 possible output functions (24 of which can be buried). n enhanced O cell allows for additional buried register capability. The P7536 can implement designs that exceed the architectural capabilities of devices such as the 26V12, 22V10, 20R10, Y7-330/331/332, TV750, EPM5032 and EPM7032. t is also a pin compatible superset to several 28-pin PLs. The P7536 offers propagation delays of 9ns/15ns (internal/external) and clocking frequencies to 83MHz. Power consumption is 85m 25MHz (55m typ.). The P7536 is available in 28-pin P, TSSOP, PL, and SO packages. The P7572 Offering more pin and logic density than the P7540 or P7536, the P7572 architecture consists of 24 pins, 14 input pins and 60 registers/latches (24 L, 24 O, 12 N), see Figure 4. The P7572 logic array has 100 sum-of-product logic functions that can share up to 60 each of 120 product terms. The 24 L s are divided into two groups (group and ) each with 12 Ls. Each L group can fully share half (60) of the 120 product terms available for sum-of-product logic functions. The P7572 multifunction logic cells offer up to three outputs per cell for a total of 72 possible output functions (48 of which can be buried). The P7572 also has a special global cell feature to preload and unload buried registers for test purposes. The P7572 can implement designs that exceed the architectural capabilities of devices such as the MH110/210, TV2500, EPM7032, EPM5064 and EP910. The P7572 offers propagation delays as fast as 13ns/20ns (internal/external) and synchronous clocking frequencies to 66MHz. Power consumption is 75m 25MHz (50m typ.). The P7572 is available in 40-pin P, 44-pin PL, and 44-pin TFP packages

5 PEEL s From O (O,N, /LK) nput Pins nput/lock Pins nput (N) uried (O) Pins nputs (L) From (L) Product Terms (L) Sum Terms Figure 5. nside the loser Look at the PEEL nside the The heart of the PEEL architecture is based on a logic array structure similar to that of a PL (programmable N, programmable OR). The logic array implements all logic functions and provides interconnection and control of the cells. epending on the PEEL selected, a range of 38 to 62 inputs is available into the array from the cells, inputs cells and input/global-clock pins. ll inputs provide both true and complement signals which can be programmed to any product term in the array. The number of product-terms among PEEL s ranges from 67 to 125. ll product terms (with the exception of certain ones fed to the global cells) can be programmably connected to any of the sum-terms of the logic control cells (four sum-terms per logic control cell). Product-terms and sum-terms are also routed to the global cells for control purposes. Figure 5 shows a detailed view of the logic array structure. True Product-Term Sharing The PEEL logic array provides several advantages over common PL logic arrays. First, it allows for true product-term sharing, not simply product-term steering, as commonly found in other PLs. Product term sharing ensures that product-terms are used where they are needed and not left unutilized or duplicated. Secondly, the sum-of-products functions provided to the logic cells can be used for clocks, resets, presets and output enables instead of just simple product-term control. The PEEL logic array can also implement logic functions with many product terms within a single-level delay. For example a 16-bit comparator needs 32 shared product terms to implement 16 exclusive-or functions. The PEEL logic array easily handles this in a single level delay. Other PLs/PLs either run out of product-terms or require expanders or additional logic levels that often slow performance and skew timing

6 PEEL s nput Pins nput (N) (O) Pins From ell System lock Preset RegType Reset nput/lock Pins uried (L) P,T,J REG K On/Off P = after clocked Register R est for storage, simple counters, shifters and state machines with few hold (loop) conditions. R From T P T Register toggles when T = 1 holds when T = 0 R est for wide binary counters (saves product terms) and state machines with many hold (loop) conditions. ell J K P R JK Register toggles when J/K = 1/1 holds when J/K = 0/0 = 1 when J/K = 1/0 = 0 when J/K = 0/1 ombines features of both and T registers. Figure 6. ell lock iagram ell (L) (L) are used to allocate and control the logic functions created in the logic array. Each L has four primary inputs and three outputs. The inputs to each L are complete sum-of-product logic functions from the array, which can be used to implement combinatorial and sequential logic functions, and to control L registers and cell output enables. s shown in Figure 6, the L is made up of three signal routing multiplexers and a versatile register with synchronous or asynchronous, T, or JK registers (clocked-sr registers, which are a subset of JK, are also possible). EEPROM memory cells are used for programming the desired configuration. Four sum-ofproduct logic functions (SUM terms,, and ) are fed into each L from the logic array. Each SUM term can be selectively used for multiple functions as listed below. Sum- =, T, J or Sum- Sum- = Preset, K or Sum- Sum- = Reset, lock, Sum- Sum- = lock, Output Enable, Sum- SUM- can serve as the, T, or J input of the register or a combinatorial path. SUM- can serve as the K input, or the preset to the register, or a combinatorial path. SUM- can be the clock, the reset to the register, or a combinatorial path. SUM- can be the clock to the register, the output enable for the connected cell, or an internal feedback node (7536, and 7572 only). Note that the sums controlling clocks, resets, presets and output enables are complete sum-of-product functions, not just product terms as with most other PLs. This also means that any input or pin can be used as a clock or other control function. Several signals from the global cell are provided primarily for synchronous (global) register control. The global cell signals are routed to all Ls. These signals include a high speed clock of positive or negative polarity, global preset and reset, and a special registertype control that selectively allows dynamic switching of register type. This last feature is especially useful for saving product terms when implementing loadable counters and state machines by dynamically switching from -type registers to load and T-type registers to count (see Figure 9)

7 PEEL s nput ell for P7536, P7572 nput From ell nput ell lock REG/ Latch nput nput Pins nput/lock Pins nput (N) uried (L) (O) Pins nput ell (N) ell for P7540 From ell ell for P7536, P7572 From ell nput ell lock nput ell lock O/N Register = after rising edge of clock REG/ Latch REG/ Latch holds until next rising edge nput nput L O/N Latch = L when clock is high holds value when clock is low From ell,, or 1 0 ell (O) Pin From ell,, or 1 0 ell (O) Pin Figure 7. nput ell (N) and ell (O) lock iagrams Multiple Outputs Per ell n important feature of the logic control cell is its capability to have multiple output functions per cell, each operating independently. s shown in Figure 6, two of the three outputs can select the output from the register or the Sum, or combinatorial paths. Thus, one L output can be registered, one combinatorial and the third, an output enable, or with the 7536 and 7572, an additional buried logic function. The multi-function PEEL logic cells are equivalent to two or three macrocells of other PLs, which have only one output per cell. They also allow registers to be truly buried from pins without limiting them to input-only (see Figure 7 & Figure 8). nput (N) nput cells (N) are included with the P7536 and P7572 on dedicated input pins. The block diagram of the N is shown in Figure 7. Each N consists of a multiplexer and a register/transparent latch which can be clocked from various sources selected by the global cell. The register is rising edge clocked. The latch is transparent when the clock is high and latched on the clock s falling edge. The register/latch can also be bypassed for a non-registered input. ell (O) ll PEEL s have cells (O) as shown above in Figure 7. nputs to the Os can be fed from any of the Ls in the array. Each O consists of routing and control multiplexers, an input register/transparent latch, a three-state buffer and an output polarity control. The register/ latch can be clocked from a variety of sources determined by the global cell. t can also be bypassed for a non-registered input. feature of the 7536 and 7572 O is the use of SUM- as a feed-back to the array when the pin is a dedicated output. This allows for additional buried registers and logic paths. (See Figure 7 & Figure 8)

8 PEEL s nput with optional register/latch uried register or logic paths Output 1 2 OE with independent output enable uried register limits pin to be input only nput Only PEEL Macrocell configured for two outputs/cell PEEL Macrocell configured for three outputs/cell Other PLs typically provide only one output per macrocell Figure 8. PEEL L/O onfiguration Flexibility The global cells, shown in Figure 9, are used to direct global clock signals and/or control terms to the Ls, Os and Ns. The global cells allow a clock to be selected from the LK1 pin, LK2 pin, or a product term from the logic array (PLK). They also provide polarity control for N and O clocks enabling rising or falling clock edges for input registers/latches. Note that each individual L clock has its own polarity control. The global cell for Ls includes sum-ofproducts control terms for global reset and preset, and a fast product term control for L register-type, used to save product terms for loadable counters and state machines (see Figure 9). f additional flexibility is needed, the P7540 and P7572 provide a second global cell that divides the L and Os into two groups, and. Half of the Ls and Os use global cell, half use global cell. This means, for instance, two high speed global clocks can be used among the Ls. nput Pins nput/lock Pins nput (N) (O) Pins (L) LK1 LK2 PLK N locks Reg-Type from ell ell: N Group & Register Type hange Feature LK1 LK2 PLK Reg-Type L locks O locks L Reg-Type P R ell can dynamically change userselected L registers from to T or from to JK. This saves product terms for loadable counters or state machines. Use as register to load, use as T or JK to count. Timing allows dynamic operation. Preset Reset ell: L & O L Presets L Resets T P R Example: Product terms for 10 bit loadable binary counter uses 57 product terms (47 count, 10 load) T uses 30 product terms (10 count, 20 load) /T uses 20 product terms (10 count, 10 load) Figure 9. ell lock iagrams

9 PEEL s PEEL evelopment Support evelopment support for PEEL s is provided by T and manufacturers of popular development tools. T offers the powerful PLE evelopment Software (free to qualified PL designers). Figure 11. PLE L & O Screen Figure 10. PLE rchitectural Editor for P7540 The PLE software includes an architectural editor, logic compiler, waveform simulator, documentation utility and a programmer interface. The PLE editor graphically illustrates and controls the PEEL s architecture, making the overall design easy to understand, while allowing the effectiveness of boolean logic equations, state machine design and truth table entry. The PLE compiler performs logic transformation and reduction, making it possible to specify equations in almost any fashion and fit the most logic possible in every design. PLE also provides a multi-level logic simulator allowing external and internal signals to be simulated and analyzed via a waveform display.(see Figure 10, Figure 11and Figure 12) esign Security and Signature Word The PEEL s provide a special EEPROM security bit that prevents unauthorized reading or copying of designs. Once set, the programmed bits of the PEEL s cannot be accessed until the entire chip has been electrically erased. nother programming feature, signature word, allows a user-definable code to be programmed into the PEEL. The code can be read back even after the security bit has been set. The signature word can be used to identify the pattern programmed in the device or to record the design revision. PEEL development is also supported by popular development tools, such as EL and UPL, via T s PEEL fitters. special smart translator utility adds the capability to directly convert JEE files for other devices into equivalent JEE files for pin-compatible PEEL s. Programming PEEL s are EE-reprogrammable in all package types, plastic-p, PL and SO. This makes them an ideal development vehicle for the lab. EEreprogrammability is also useful for production, allowing unexpected changes to be made quickly and without waste. Programming of PEEL s is supported by many popular third party programmers. Figure 12. PLE Waveform and Simulator Screen

10 PEEL s Flexible (over 8000 configurations per cell) Figure 13. uried ombinatorial & Figure 15. -Reg (w/ clock, preset & reset) & nput Figure 14. uried ombinatorial, -Reg w/ Latch PEEL pplications The unique combination of logic array speed and architectural flexibility lets PEEL s address a multitude of combinatorial, sequential and asynchronous applications. The versatile PEEL logic control cell is key to this flexibility offering over 8,000 possible user-selected configurations per cell (see Figure 13 to Figure 16). cells can be configured to support combinatorial functions including address decoders, encoders, multiplexers, comparators, and adders. They also handle asynchronous random logic such as flip-flops (i.e., 7474) with independent clock reset and preset, SR latches and gated latches. dditionally, synchronous registered functions, including shifters, clock dividers, Figure Functions: uried T-Reg, uried -Reg & Output counters, and state machines can be created. PEEL multiple registers and outputs easily support buried counters and state machines (see Figure 17). nput latches add further flexibility allowing pipelined operation, direct demultiplexing and gated-strobing of address and data lines. dditionally, the number of registers and latches available for data storage, as well as tri-state s, open many possibilities for bus interfaced sub-systems. For more information on PEEL applications examples please refer to the PLE Users Manual and the example design files provided with the PLE software nputs Next State ecode uried State Machine or ounter Registers Output ecode Outputs Figure 17. uried ounters and State Machines

11 PEEL s Why PEEL s are Unique The PEEL architecture combines a nonsegmented programmable logic array (PL) with FPGstyle logic cells that free PL users from the architectural restrictions of simple PLs/GLs and the PL-like blocks of segmented PLs. They are also rich in buried registers/ latches and logic functions (see Table 1). Key PEEL architectural features include: omplete nput/feedback vailability. Every input pin and feedback is available for use by any logic function. s a result, PEEL input availability is two to three times that of segmented PL blocks, guaranteeing connectivity for wide-gate logic in single level delays, as well as flexible assignment. Real Product Term Sharing via a Wide-gate PL. The PEEL non-segmented PL allows real product term sharing for wide-gate functions such as comparators and state-machines. Over 60 product terms are available per function as compared to segmented PLs, which have a limited number of product terms per function, supplemented by term steering or expander schemes that can limit logic utilization or adversely affect timing. True buried registers via FPG-style logic cells. PEEL logic cells have multiple functions per cell, similar to FPGs and equal to 2-3 ordinary PL macrocells. Thus, registers (or combinatorial logic functions) can be buried from pins without sacrificing the output functions of s, as do many PL macrocells. Flexible Registers with independent clocks and Sum-of-products control. PEEL s have,t and JK registers that allow clocks, presets and resets to be individually or globally controlled via full sum-of-product functions from the PL. Some segmented PLs share register clocks, presets and resets via single product terms. ndependent Output Enables with Sum-of-products control. PEEL s allow for complex output enables with individual sum-of-products control instead of dedicated pins or single product terms, as used by most segmented PLs. For more information on PEEL s and other T products contact T at SY-PEEL ( ) rchitecture Specification P7540 P7536 P7572 Pin ount 24/ /44 Package Types P, SO, PL P, SO, PL P, PL, TFP tal PL nputs/feedback) True & omplement 84 (42x2) 76 (38x2) 124 (62x2) locks (or nput) nputs s uriable Feedback ual Function 12 Triple Function 24 Triple Function tal Product Terms tal Sum Terms tal Registers/Latches uriable Registers nput Registers/Latches Table 1. PEEL Family rchitecture Specifications

12 PEEL s uick PEEL ross Reference ltera T EP312 EP600P EP600P-45 EP600P-3 EP600* EP600-3* EP610P-35 EP610P-30 EP610P-25T EP610P-25 EP610P-20T EP610P-20 EP610P-15T EP610P-15 EP610P-30 EP610-35* EP610-30* EP610-35* EP610-30* EP610S-30 P7540S-15 EP610S-25 P7540S-15 EP610S-20 P7540S-15 EP610S-15 P7540S-15 EP900P EP900P-3 EP900P-2 EP910P-40 EP910P-35 EP910P-30 EP910P-30T EP910-40* EP910-35* EP910-30* tmel T TV750-20* TV750-20G* TV750-20J P7540J-15 TV750-20K* P7540J-15 TV750-20P TV750-20S P7540S-15 TV750-25* TV750-25G* TV750-25J P7540J-15 TV750-25K* P7540J-15 TV750-25P TV750-25S P7540S-15 TV750-30* TV750-30G* TV750-30J P7540J-15 TV750-30K* P7540J-15 TV750-30P TV750-30S P7540S-15 TV750-35* tmel (cont.) T TV750-35G* TV750-35J P7540J-15 TV750-35K P7540J-15 TV750-35P TV750-35S P7540S-15 ypress T PL20R10-15P PL20R10-15W PL20R10-20P PL20R10-20W G H* G J G H* G J ntel T PPL PL610-15* PPL PL610-25* PPL PL910-15* PPL PL910-25* * P * P * P * P * P * P Lattice T GL20R10-15LP GL20R10-15LJ GL20R10-20LP GL20R10-20LJ GL20R10-30LP GL20R10-30LJ GL20XV10-15LP GL20XV10-15LJ GL20XV10-20LP GL20XV10-20LJ GL26V12-15LP P7536P-15 GL26V12-15LJ P7536J-15 GL26V12-20LP P7536P-15 GL26V12-20LJ P7536J-15 Lattice (cont.) T GL LP GL LJ P7540J-15 GL LP GL LJ GL LP P7540P-20 GL LJ National T GL20R10-15N GL20R10-20N GL20R10-25N GL20R10-15V GL20R10-20V GL20R10-25V GL LN GL LV Philips T PLS173N PLS173N PLS179N PL42V12F* PL42V12N PL42V12 T T EP630-15NT EP630-20NT Vantis (M) T PLE24V10H-15P P7536P-15 PLE24V10H-15J P7536J-15 PLE24V10H-25P P7536P-15 PLE24V10H-25J P7536J-15 PLE26V12H-15P P7536P-15 PLE26V12H-15J P7536J-15 PLE26V12H-25P P7536P-15 PLE26V12H-25J P7536J-15 PLE29M16-25P PLE29M16-25J P7572J-20 PLE29M16-25P PLE29M16-25J P7572J-20 PLE610H-15P PLE610H-25P P7572J-20 PLE20R10H-20P PLE20R10H-20J P7572J-20 * These devices use ceramic P or J-lead packages; the equivalent T devices use plastic packages.