5 GT/s and 8 GT/s PCIe Compared

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Iris Martin
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5 GT/s and 8 GT/s PCIe Compared Bent Hessen-Schmidt SyntheSys

2 Disclaimer The material included in this presentation reflects current thinking of the presenter and should not be evaluated as direction from the PCI-SIG. Information is from a draft specification and subject to change. Copyright 2008, PCI-SIG, All Rights Reserved 2

3 Introduction As the next generation of PCI Express is defined, the information throughput will double and yet the symbol rate will only move from 5 GT/s to 8 GT/s. There are some significant changes and challenges: While 5 GT/s communications used 8b/10b encoding to limit the longest occurrences of consecutive 1 s and 0 s, 8 GT/s will use scrambling. This has system budget and signal integrity impact on both transmitter and receivers. Baseline wander due to the long runs of consecutive 1 s and 0 s will impact the available eye height. AC coupling capacitors of 220 nf will be required in order to reduce the baseline wander The combination of higher data rate and channel length up to 20 combine to cause Inter Symbol Interference (ISI), in addition to jitter from reference clocks and transmitters. These will limit the eye opening width available. Copyright 2008, PCI-SIG, All Rights Reserved 3

4 Content Similarities for 5 GT/s (Giga Transfers/second) & 8 GT/s System communicating over same 20 channel Differences between 5 GT/s and 8 GT/s Double data throughput rate 8b/10b encoding versus PRBS23 scrambling Base line wander Transmitter Phase Locked Loop (PLL) bandwidth Pre-emphasis 2 taps at 5 GT/s versus 3 taps at 8 GT/s Pre-, main and post cursor Receiver Tolerance Clock Data Recovery (CDR) bandwidth Equalization Copyright 2008, PCI-SIG, All Rights Reserved 4

5 Interconnect Model Model represents typical 1U or 2U server consisting of motherboard, riser, and adapter Rx package Tx package Stripline Riser (4 ) Via Adapter Stripline (4 ) Socket AC Cap Connector Motherboard PCB (12 ) Stripline or Microstrip Copyright 2008, PCI-SIG, All Rights Reserved 5

7 Baseline Wander Long length of consecutive 1 s or 0 s create baseline wander due to the high pass filter effect of the AC coupling capacitor Original Signal After AC Coupling Baseline Wander Copyright 2008, PCI-SIG, All Rights Reserved 7

8 Scrambling Missing the disparity control which provided a balanced number of 1 s and 0 s at 5 GT/s. 128/130 encoding inserts 01 or 10 symbols. However no upper bound on longest length of consecutive identical transmitted data levels. Theoretically the data could be un-doing the scrambling sequence. The likely hood of this worst case is however small and diminishing as the length of the scrambling sequence increases. X^23+X^21+X^18+X^15+X^7+X^2 Scrambling polynomial is longer than 8 Mbits. Copyright 2008, PCI-SIG, All Rights Reserved 8

9 AC coupling Capacitors Even with the seed for PRBS to selected to minimize baseline wander: Baseline wander is simulated to be < +/-2.3 mv. The group which I work with will be conducting real measurements of the baseline wander using averaged waveforms of PRBS23 and worst case patterns. It is still important to increase the AC coupling capacitors to 220 nf nominal value: Baseline wander more than doubles to +/-5.4 mv in simulations if AC coupling capacitor is 75 nf. Copyright 2008, PCI-SIG, All Rights Reserved 9

10 PLL Loop Bandwidth From Table 4-9, 2.0 Base Spec (Example measured 2.5GT/s Device) Peaking (db) Acceptable Region, 2.5GT/s Acceptable Region, 5.0GT/s Loop BW (MHz) Copyright 2008, PCI-SIG, All Rights Reserved 10

11 Possible Measurement Methods Currently two methods for characterizing PLL response: Spectrum Analyzer Reference issues Clock PLL Analyzer Follows data edge for Better Accuracy & Repeatability 1a. 1b. Frequency domain analysis Area of peaking each side Where to put cursor? 3.9MHz 7.8MHz Where to place the (0 Hz, 0 db) reference cursor? Phase Noise & Inter-modulation, Power Supply & Interference AM Noise -3dB? MHz Response without noise Copyright 2008, PCI-SIG, All Rights Reserved 11

12 Transmitter PLL Test C. (Replaces CBB on-board reference clock) Clock PLL Analyzer 100MHz Clock, phase modulated A. Add-in Card B. Compliance Base Board (CBB) 2.5 or 5 or 8 GT/s data Copyright 2008, PCI-SIG, All Rights Reserved 12

13 Transmitter PLL Test Close Loop Response Function = 1/(1+G(s)) 3 db points Jitter Transfer Function = G(s)/(1+G(s)) Shows how well SSC & jitter is tracked Copyright 2008, PCI-SIG, All Rights Reserved 13

14 Assumptions/Enablers Statistical jitter analysis More closely approximates reality Doing without leaves too much margin on the table Optimized reference clock and CDR bandwidths Permits use of existing reference clock infrastructure Min CDR BW PLL BW PCIe MHz 5-16 MHz PCIe 3.0*** 10 MHz 2-4 MHz Trainable equalization to mitigate channel effects Rx equalization: multi-tap linear or DFE?*** (study in progress) Tx equalization: multi-tap linear*** (study in progress) *** Currently in discussion; not the final spec Copyright 2008, PCI-SIG, All Rights Reserved 14

Dual Port Measurements Acquire 100 MHz clock Acquire 5 GT/s data

B. Hardware clock recovery applies PLL function in real time Measure

Real Time Scope Analyzer Differential data Differential data Clk CR

15 Dual Port Measurements Acquire 100 MHz clock Acquire 5 GT/s data Apply PLL in math to derive Tx clock Measure data relative to clock A. B. Hardware clock recovery applies PLL function in real time Measure data relative to clock 4 ch. Real Time Scope Analyzer Differential data Differential data Clk CR Differential clock = Equivalent methods, but B gives faster results. Copyright 2008, PCI-SIG, All Rights Reserved 15

16 Traditional Q-scale jitter The CDF obtained from measurement is transformed onto a Q axis Q is the inverse normal CDF Gaussian jitter is linear on this scale where units of Q represent sigma of the Gaussian distribution Sample size required for the distribution to have become linear depends on pattern and device, typically in the range of The straight line of slope 1/sigma is then extrapolated up to Q=0 and down to Q=7 Intersection with Q=0 is DJ DD Used for T TX-DJ-DD Intersection with Q=7 is TJ DD Used for UI-T TX-EYE Q (x) Q (x) Copyright 2008, PCI-SIG, All Rights Reserved 16

17 Jitter from de-emphasis Jitter due to de-emphasis is actually desirable and the transmitter should not be punished for this. Channel effectively removes the de-emphasis jitter Tx approximates the inverse of the HF loss of the channel De-emphasis causes a timing error in cumulative eye measurement Closes the eye on right side Overestimates eye opening on left side up to17 ps error at 5 GT/s Timing error t TX-EYE (too small) Copyright 2008, PCI-SIG, All Rights Reserved 17

Compensation for deemphasis in 5 GT/s tests Timing error can be removed by applying a form of measurement DFE

with - 6dB de-emphasis Small timing error occurs with current technique if Tx not exactly -6dB Actual measurement

IF fullswing : scale = deemp; 2 deemp scale = ; 1+ deemp ELSE : 2 deemp scale = ; 1+ deemp t TX-EYE (correct)

18 Compensation for deemphasis in 5 GT/s tests Timing error can be removed by applying a form of measurement DFE Waveform is voltage scaled and offset based on current and previous logical values Scaling exactly match a Tx with - 6dB de-emphasis Small timing error occurs with current technique if Tx not exactly -6dB Actual measurement data needs to be averaged to increase the effective sampling rate and remove noise floor of measurement equipment IF fullswing : scale = deemp; 2 deemp scale = ; 1+ deemp ELSE : 2 deemp scale = ; 1+ deemp t TX-EYE (correct) offset = 0.0 ELSEIF previousbit == 1: 1 scale offset = 4 1 scale offset = 4 Copyright 2008, PCI-SIG, All Rights Reserved 18

19 8 GT/s Statistical approach for Tx & pulse width tests De-emphasis complicates timing measurements as voltage swing vary Need to make measurements as if they were convolved with the inverse of the Tx equalization De-embedding back to the die-pad (8 GT/s reference plane) Available tools include open source version 5 from If statistics are based on averaged clean eye measurements then: Uncorrelated jitter needs to be added back in after de-embedding Fluctuations removed by measuring millions of samples per bit. Measurements to 1E -12 BER are possible! 80% 20% 20% 80% 50% 50% Pulse width measurement allows worse case channel induced pulse compression to be modeled. Pulse width CDF measurements at N=1 and N=2 are important as these are most affected by the channel (low pass filtering) and sub-rate clocking techniques. T TX-RISE-FALL t MIN-PULSE Copyright 2008, PCI-SIG, All Rights Reserved 19

20 Receiver Tolerance 2a. Rj Low MHz Rj 1. Residual SSC MHz Dj 2b. Rj High MHz Rj Σ Mod Input Clk Pattern Generator Low Jitter Clock 4. Σ DM/CM Crosstalk For Common Clock Architectures Only 6. Calibration Channel ISI Receiver Under Test 100 MHz BER SJ to test decisions 3. (5.) MHz Dj Crosstalk Based on Figure 4-36, Base Spec Copyright 2008, PCI-SIG, All Rights Reserved 20

21 5.0 GT/s Rx Tolerancing Parameters (common clock architecture) Parameter UI V RX-MIN-MAX-RATIO Description Unit Interval without including of SSC Min/max pulse voltage ratio seen over an time interval of 2 UI. Min T RX-HF-RMS MHz RMS jitter 3.4 T RX-HF-DJ-DD Max Dj impinging on Rx under 88 test T RX-SSC-RES 33 khz Refclk residual T RX-LF-RMS <1.5 MHz RMS jitter T RX-MIN-PULSE Minimum single pulse applied at 120 Rx -- Max Units ps ps RMS ps ps ps RMS ps Notes Over 10 6 UI Spectrally flat 2, 4 Spectrally flat 2 2 V RX-EYE Receive eye voltage opening 120 mvpp diff 1, 3 V RX-CM-CH-SRC Common mode noise from Rx mvpp 2 Notes: 1. Refer to Figure 4-41 for a description of how the Rx eye voltage is defined. 2. Accumulated over 10 6 UI. 3. Minimum eye is obtained by first injecting maximum Dj and then adjusting Rj until a minimum eye (defined by T RX-EYE ) is reached. Rj is filtered with a BPF having f C-LOW and f C-HIGH of 1.5 MHz and 100 MHz, respectively with step rolloff at 1.5 MHz and a 20 db/decade rolloff on the high side. Minimum eye width is defined for a sample size equivalent to a BER of Different combinations of T RX-HF-DJ-DD and T RX-HF-RMS are needed to measure T RX-TJ_CC and T RX-DJ-DD-CC. Copyright 2008, PCI-SIG, All Rights Reserved 21

22 5.0 GT/s Rx Tolerancing Parameters (common clock architecture) Parameter UI Units T RX-HF-RMS MHz RMS jitter 3.4 ps RMS Spectrally flat T RX-HF-DJ-DD Max Dj impinging on Rx under 88 ps 2, 4 test T RX-SSC-RES 100 MHz, respectively 33 khz Refclk residual with step rolloff -- at MHz psand a 20 T RX-LF-RMS db/decade <1.5 rolloff MHz RMS on jitter the high side ps RMS Spectrally flat T RX-MIN-PULSE Minimum single pulse applied at 120 ps 2 Rx V RX-MIN-MAX-RATIO Description Unit Interval without including of SSC Min/max pulse voltage ratio seen over an time interval of 2 UI ps Notes Over 10 6 UI 3. Rj is filtered with a BPF having f C-LOW and f C-HIGH of 1.5 MHz and Min Max 2 V RX-EYE Receive eye voltage opening 120 mvpp diff 1, 3 V RX-CM-CH-SRC Common mode noise from Rx mvpp 2 Notes: 1. Refer to Figure 4-41 for a description of how the Rx eye voltage is defined. 2. Accumulated over 10 6 UI. 3. Minimum eye is obtained by first injecting maximum Dj and then adjusting Rj until a minimum eye (defined by T RX-EYE ) is reached. Rj is filtered with a BPF having f C-LOW and f C-HIGH of 1.5 MHz and 100 MHz, respectively with step rolloff at 1.5 MHz and a 20 db/decade rolloff on the high side. Minimum eye width is defined for a sample size equivalent to a BER of Different combinations of T RX-HF-DJ-DD and T RX-HF-RMS are needed to measure T RX-TJ_CC and T RX-DJ-DD-CC. Copyright 2008, PCI-SIG, All Rights Reserved 22

23 Band limited Random Jitter On one hand it is clear by specifying f C-HIGH = 100 MHz with a 20 db/decade roll off that the Rj level is required to be down by 3dB at 100 MHz. This is further substantiated by the definition of f C-HIGH in the original workgroup documents and version 0.4 of the base specification. db(s(1,2)) Filter function applied to white Rj corresponds to: f C_LOW = 1.0 MHz, f C_HIGH = 20 MHz Rolloff = 20 db/decade -25 1E5 1E6 1E7 1E8 2E8 Copyright 2008, PCI-SIG, All Rights Reserved 23

24 Band limited Random Jitter On the other hand the note appears to require spectral flatness to 100MHz. The question is: How flat? Flatness to 100 MHz 3 db 2 db 1 db 0.5 db 0.25 db 0.1 db -3 db Frequency 100 MHz 133 MHz 200 MHz 300 MHz 420 MHz 666 MHz Copyright 2008, PCI-SIG, All Rights Reserved 24

25 Band limited Random Jitter What would happen if one tested the same receiver with 100 MHz and 666 MHz 3 db bandwidth Rj? If the receiver CDR jitter transfer bandwidth is less than 1.5 MHz nothing would happen If the CDR bandwidth was let s say 10 MHz then the receiver would see 91.4% of the Rj from the 100 MHz but as much as 98.7% from the 666 MHz source. Loop Magnitude Response 1-H(jw) (Observed Jitter Transfer Function) Jitter Frequency Copyright 2008, PCI-SIG, All Rights Reserved 25

26 Band limited Random Jitter The two requirements are inconsistent unless: HF Rj noise source that is spectrally flat from 1.5MHz to 100MHz before filtering. This spectrally flat noise source is then cascaded through two shaping filters: 1. A high pass filter with a step roll off that is 3dB down at 1.5MHz. 2. A low pass filter with a 20dB/decade roll off that is 3dB down at 100MHz. Copyright 2008, PCI-SIG, All Rights Reserved 26

Return loss requirements for 5 GT/s calibration channel Low Jitter Clock For Common Clock Architectures Only 0.01 1.5 MHz Rj 0.01 1.5 MHz Dj 1.5 100 MHz Rj 1.

27 Return loss requirements for 5 GT/s calibration channel Low Jitter Clock For Common Clock Architectures Only MHz Rj MHz Dj MHz Rj MHz Dj Already includes reflection DJ Σ From: Figure 4-39, Base Spec Rev. 2.0 Mod Input Clk Pattern Generator Return Loss (db) Σ DM/CM Crosstalk Calibration Channel ISI Receiver Under Test 100 MHz BER Maximum amount of allowed reflections S11 Any non-compliant reflections add in as non-compensable Dj Copyright 2008, PCI-SIG, All Rights Reserved 27

28 Going beyond T RX-HF-DJ-DD Search algorithms allow increasing of Sine jitter (Sj) until the failure point at each frequency is reached. CDR Response (Jitter Transfer function directly visible in Rx testing) Loop Magnitude Response Increase SJ 2.09 db CDR usually most sensitive to jitter just beyond the loop bandwidth. Indicates peaking in the inverse response, caused by deviation from ideal critical damping (2.09 db peaking) and/or delay in the closed loop response. 1-H(jw) (Observed Jitter Transfer Function) H(jw) (Loop Response) Jitter Frequency Copyright 2008, PCI-SIG, All Rights Reserved 28

PCI Express Electrical Basics

PCI Express Electrical Basics Dean Gonzales Advanced Micro Devices Copyright 2015, PCI-SIG, All Rights Reserved 1 Topics PCI Express Overview Enhancements for 8GT/s Target Channels for the Specification