TSTE12 Design of Digital Systems. TSTE12 Practical issues 09/05/ :48. Project group definition published Wednesday 6/9.

Transcription

1 TSTE12 Design of Digital Systems 1 Friendly reminder 2 Lecture 4 Project group definition published Wednesday 6/9 Practical issues Project information Hardware details (DE2-115 board) Mark the project participation list! 1 st project meeting (with supervisor) deadline 8/9 Requirement specification More detailed simulation model 1 st version deadline Tuesday 12/9 Inertial and transport delay Final version deadline Friday 15/9 Lab deadline Lab 1 completed by 13/9 at to be allowed project participation TSTE12 Practical issues 3 Useful resources 4 Sign up for lab group Lists outside ISYtan (B-Building, 1 st floor, corridor C, between entrance 25 and 27) Each group will be one or two people Directory /sw/altera/kits/de2_115_v.1.0.5_systemcd Lab board Datasheets, schematic over hardware Lab open 24/7, keycards have been upgraded Other labs may be used, using remote login to ixtab Can not do the lab without first signing up See timeedit for available other labs All software have online manuals See help menu

2 Handin information 5 Handin information, cont. 6 1 st handin deadline Monday 18 September Available on web from Monday 11 September Use web page to hand in answers to theory questions (see homework entry on web page) Use your own home directory for code (Not lab group directory) Use ~/TSTE12/EXAM/Part1/src/ Start a TSTE12handin shell and work from there module load TSTE12 ; tste12handin Create handin code answers using a plain text editor emacs, vim, or the built-in editor in modelsim (started from within the handin12shell window) See in the tutorial how start and use modelsim Remember to compile and simulate the design Will use source code for checking handin results Do not use handin directory for anything else but handin code you make yourself! Anything located in ~/TSTE12/EXAM must be your own work Hand-in reminder 7 Project information 8 Hand-ins are checked automatically (using scripts) Project directory will be available for all groups /site/edu/es/projects/projgroupxx Make sure all names are correct in code answers Access only to members of the group Directories used in the hand-ins are locked at answer deadline Test your code! Do not assume that you have written correct code. This directory must be used Not enough to use other internal/external sites There will be quota defined (approx 750 MB) NOTE: Do NOT use hdl-designer (do not start the software using tste12lab or tste12proj) See modelsim chapter in the tutorial on exercise page

3 Project directive, high priority Directive document available on the web 9 Project directive, options, medium priority Oscilloscope 10 ecification_2015.pdf Volume & balance control Vertical vs horizontal Zoom, color coding, average FFT Volume is logarithmic Complex algorithm Simplifications are often possible Multiplication is generally expensive Use available designs if possible (include reference in documentation) Amplification (factor > 1) may lead to overflow! Each project group make their own choice No problem if more than one group selects the same project Project directive, options, medium priority Echo 11 Project directive, options, medium priority Signal level indication 12 Long echo requires large memory (2MByte SRAM) Peak, average Number representation Screen update ~ 50Hz 44 Khz, 20 bit, stereo => 220KByte/s Do not want a flickering output Dynamic range Large number of samples to average on Accuracy 2's complement/floating point Controls? On/off Length Peak indication move slowly towards zero quickly updated when large peak found Compare with various media player formats Strength

4 Project directive, options, medium priority Loudness, supression of mono 13 Big hall simulation (reverb) 14 Loudness control => attenuate medium frequencies Principle: Echoes from walls and objects Equalizer Requires understanding of digital filters Test filter algorithms using Matlab Other sound modification algorithms possible Reverb, Flange Pitch shifts... Reverb, cont. 15 Reverb algorithm 16 Three parts of the sound Direct path Delayline with feedback Early reflections Decaying mix of reflexions Time in the echoes are short Example: 5,10,20,30,45,60,75 ms versions added together Add together a number of attenuated taps Create attenuated feedback

5 Project directive, low priority 17 Project directive, low priority 18 Try to think of a lot of optional features Play around with additional hardware Color coding, background image 2GB SD-card Animations, different VGA screen backgrounds Remote control Special keys to use (e.g., arrow keys) 5 Mpixel camera module Change parameters at run time Additional volume/balance steps... Try to optimize the size of the design Many clock cycles between input samples Project issues 19 Important reminder 20 Expected project participation conduct Weekly meeting transcripts Do no be late to meetings Meeting every week (without supervisor) required! Inform the rest of the group if you have problem attending a meeting (in advance if possible) Keep track of your project work, noting amount and type of task Documents should be discussed and approved by supervisor Possible to fail project even if design works Possible for individual to fail project even if rest of group get a pass! Meeting transcript submitted to supervisor within two days of the meeting! Send Use meeting transcript template /site/edu/es/tste12/material/project/lips-templates The supervisor need to understand what you have done, what you will do, and how many hours each individual have worked on the project.

6 Project hardware 21 Project 22 All FPGA board documentation Note on templates /sw/altera/kits/de2_115_v.1.0.5_systemcd Hardware will be located in the lab from the first lab to the last day of the project Hint: Check both chip datasheets AND the schematic showing how a unit is connected on the board! They are imports of the Microsoft Office versions Help point out information that should be in document Formatting not critical, but please try to fix problems Latex documents acceptable if in pdf-format with the same information as the libreoffice templates Project, cont. 23 Design flow and tools 24 Hints about Requirement specification Three types of activities in the course Possible subsystem: control, display, audio processing Handin Add plenty of features Lab Avoid multiple requirements in one requirement statement Hints about design specification Should indicate idea about general building blocks Interfaces (signals/data to communicate) Behavior Project For handins: use simple text editor + modelsim Start the TSTE12handin shell Write code, compile, simulate Chapter 2 tutorial notes shows how to use modelsim

7 HDL Designer tool 25 HDL Designer tool, cont. 26 Design entry tool, main entry tool to the project Top level: The project (defined by xxx.hdp file) Tutorial also available to get you started Tools used to manage libraries, design, and other tools for use by larger designer groups Graphic and text design entry Tool startup configurations Contains list of libraries, (1 or more) Each library contains design units Described as components (green and blue boxes) Each unit have different view Graphic and/or textual Various forms of architectures (text, block, FSM, ) Support many different languages and tools Version control, team management... A default architecture view is indicated by a blue arrow Interfaces with simulation and synthesis tools Highly configurable HDL Designer tool, cont. 27 File IO 28 Green boxes (components) Differs between 87 and 93 standard! Fixed interface (does not automatically update) mostly syntax differences Possible to reuse in multiple designs Formatted IO Blue boxes (subsystems) Not generally human readable (platform dependent) Updates interface when adding/removing inputs/outputs in block diagram Tools can generate valid vhdl from graphical representation (schematics, state machines, etc.) Text IO Human readable Can only be in or out, not inout (87 specific)

8 29 30 File Text IO VHDL 93 Special package STD.TEXTIO Most of 87 is the same, only minor changes File is accessed in steps Full ISO character set (256 values) Declare file (Opens the file) file my_file : text is in my_inputs.vec ; Read a complete line readline(my_file,text_line); Read individual data from the line read(textline,inputval); Extended identifiers Delimited by \, e.g., \74ls04\ May contain reserved words Always different from short identifier, e.g., \XYZ\ is not the same as XYZ VHDL 93, cont. 31 VHDL 93, cont. Direct instantiation in structural code 32 Some minor declaration simplificatons Component declarations may end with end componentname instead of end component Other similar changes applied to configurations, blocks, processes, records, if, case, subprograms Postponed processes No need to declare the component before instantiation Expressions on inputs Assign fixed values on inputs to blocks in structural code. Shared variables Executed only when all other processes for a given simulation time step has completed (stable signals) Improved reporting Include variable values in report string

9 VHDL VHDL 2008, cont. 34 Simplified sensitivity list Conditional assignment in sequential code Keyword all will replace all signals used in the process NextState <= FLASH when FP else IDLE Unary logic functions Simplified conditions If statements accept bit and std_logic result Additional relational operators?=,?/=,?>,?<= Return element value (bit or std_logic) when comparing vectors Signal Data : std_logic_vector(7 downto 0); Signal parity : std_logic; Parity <= xor Data; Array / Bit logic Signal Sel: std_logic; Signal Y, A : unsigned(3 downto 0); Y <= A and Sel; Will expand Sel to vector matching A VHDL 2008, cont. 35 VHDL model testing 36 Expressions in port maps Testbench U_CHIP: CHIP port map (A, Y and C, B); Reading out ports in entity Standard approach Test of design will be independent of simulation tool Define referenced sets of packages as context Testbench contents Stimuli generation Design under test (DUT) Analysis of design output The stupid user approach Stimuli DUT Analysis Load design, run -all, wait for simulation to stop, look at printouts

10 VHDL model testing, cont. 37 Modeling techniques 38 Stimuli Expected input signals, including reset and clocks Usually validation only (typical inputs) Analysis Check if output is the expected one Make sure test is done at correct time Report results (ok/non-ok) Stimuli Stimuli and synthesis not synthesized, only for simulation! DUT Analysis Details on the VHDL delay model and concurrency How to create a more accurate simulation model Examples of some common primitives in digital systems Some new language constructs not yet covered Timing and concurrency 39 Signals vs Variables 40 Simulate hardware (concurrent events) on a sequential machine (computer) Must have the same result from simulation independent of execution order of individual events Electronic signals can not change in 0 seconds Common sequential code assumes variables are updated before the next state is executed Both variables and signals can be synthesized Delay is important in simulation of hardware

11 Signals vs Variables, example 41 Signal assignment with delta delay 42 X: Y: Z: initial t1 t1+2 t1+4 t1+6 AS <= X*Y after 2 ns; BS <= AS+Z after 2 ns; AS: BS: AV := X*Y; BV := AV + Z; AV: BV: Minimum delay is a delta delay Delta delay is > 0 but much smaller than the minimum time step X: Y: Z: initial t1 t1+delta t1+2*delta AS <= X*Y; BS <= AS+Z; AS: BS: Delta delay Can not be explicitly specified Delta delays will never add up to a simulation delay in seconds (standard time) Sometimes referred to as Macro (simulation time) and micro (delta delays) timing. 43 Simulation cycle including delta delay 1. If no entries in queue then stop, else increase time to next time entry in queue 2. Start a new simulation cycle without advancing simulation time. Remove all entries scheduled for current simulation time, update all signals. Activate triggered processes 3. Execute activated processes. Schedule new time queue entries. 4. If there are new transactions on signals due to assignment with delta delay, then goto 2, otherwise goto 1 44

12 45 46 Macro and micro timing Time may stand still in simulation by continuous signal updates Example: process triggered by a signal that it is updating Combinatorial loops without macro delay in assignments Simulation models Delta delay only Functional verification of models Standard time unit delay only Validate system timing Mixed Delta delay where delay is not important Standard time unit delay where delay is significant Study system timing Entity BUFF is port (X: in BIT; Z out BIT); end; Architecture ONE of BUFF is signal Y: BIT; process(x) variable Y : BIT; Z <= X; end process; end ONE; architecture TWO of BUF is signal Y: BIT; process(x) Y <= X; end process Z <= Y; end TWO; Example of models Simple buffer examples All buffers have different propagation delay Difference in delta delay is difficult to see in waveform windows Possible to create multiple delta delay architecture THREE of BUF is signal Y1,Y2: BIT; Y1 <= X; Y3 <= Y2; Y2 <= Y1; Z <= Y3; end THREE; 47 Architecture FIVE of BUFF is signal Y5: BIT; process(x) Y5 <= X; Z <= Y5; end process; end FIVE; architecture FIVE_A of BUF is signal Y5: BIT; process(x,y5) Y5 <= X; Z <= Y5; end process end FIVE_A; Example of models, cont. Two almost identical buffers Have very different simulation behavour Both probably generate same hardware in synthesis Lacking entries in sensitivity list Solution: Always add all input signals to the sensitivity list Drawback: unnecessary process triggering may give slower simulation 48

13 Inertial and Transport delay Delay can be of two types (3 in VHDL93) Inertial If input change again before end of delay then do not update output Filter out short glitches (RC delay) Z <= I after 10 ns; Transport True delay of signal (like transmission lines) Z <= transport I after 10 ns; Reject (VHDL93) Q <= reject 4 ns inertial a after 10 ns; 49 Implementation of Inertial and Transport delay Important to understand why a signal change may not reach the assigned signal Transaction Pair of value and time. What value when Waveform A series of transactions (sorted by time value) Current value of driver Value of transaction whose time is not greater than current simulation time. Removed when simulation time is updated if next transaction time is reached Q_tmp <= A after 4 ns; Q <= Q_tmp after 6 ns; 50 Waveform update algorithm 1. All old transactions with time at or after earliest new transaction are deleted. Add new transactions to the waveform If inertial then 2. Mark all new transactions 3. Mark old transaction if it immediately precedes a marked transition and its value is the same as the marked transaction 4. Mark the current value transaction 5. All unmarked transactions are removed 51 Waveform update example Z <= I after 10 ns; (I is a 5 ns pulse starting at t=0) First change Z updated to '1' at t=0, (10,'1') transaction added Both current and transaction marked and kept Second change, Z updated to '0' at t=5, (15,'0') transaction added If inertial: (10,'1') not marked, removed 52

14 53 Inertial delay side effects Process Z <= '1' after 50 ns; Z <= '0' after 100 ns; wait; end process; Only executed once at start First assignment is eliminated by second assignment Use transport or combined assignment to get pulse Z <= transport '1' after 50 ns; Z <= transport '0' after 100 ns; Z <= '1' after 50 ns, '0' after 100 ns;