Design Problem 5 Solutions

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1 CS/EE 260 Digital Computers: Organization and Logical Design Design Problem 5 Solutions Jon Turner Due 5/4/04 1. (100 points) In this problem, you will implement a simple shared memory multiprocessor system and run a small test program using it. Your system will use two copies of the simple processor introduced in class (with a couple modifications). These will each connect to a separate port of a two port memory module. Both processors will execute a program stored in the memory module and will exchange data through the memory. You will need to make two changes to the processor. First, add an input signal called pid (this stands for processor id). In your top level entity, you will instantiate the cpu module twice. One instance will have its pid input connected to a constant 0 and the other will have its pid input connected to a constant 1. Now, inside the cpu module itself, add a new instruction to load the value of the pid input into the accumulator. Use 0002 as the numerical value for this instruction. Next, you will need to create a different version of the memory module. This version will have two sets of ports (0 and 1), each with its own enable, r/w signal, address and data. These two sets of ports will operate independently of one another, so that one processor can read a location in the memory at the same time that the other processor is writing a different location. Note that if both processors attempt to write the same location at the same time, the result may be unpredictable. It s up to the person who programs the processors to make sure this doesn t happen. In the top level module, connect your processors to the corresponding ports of the memory module. To test your multiprocessor system, write a simple program that causes the two processors pass a value back and forth, incrementing the value between each pass. Both processors will be executing the same program (which they get from the shared memory), but the behavior of processor 0 will be slightly different from processor 1. To allow the processors to behave differently, your program will need to look at the pid value and perform some operations differently, based on the pid. Your program should use memory location 63 (hex 3f) to store a count (which the processors will each increment) and location 62 to store a flag to control access to the count. The flag is used as follows. Whenever the flag value is equal to the processor s pid value, that tells the processor that it is its turn to increment the count. After the processor increments the counter, it writes the pid of the other processor into the flag location. When the flag value is not equal to the processor s pid, the processor should just wait in a loop, checking the flag on each iteration, and exiting the loop when the flag value matches its pid. Both processors should stop as soon as the value of the counter is greater than 20. For your design notes, make a copy of the processor block diagram on page 6.19 of the notes and modify it to show where the pid comes in. Include notes with the block diagram - 1 -

2 explaining how the pid is used. The figure below is a block diagram of the memory module. Draw a similar diagram for the two port memory module. This should correspond to your VHDL for the memory. Your notes should also include a brief description of what parts of the VHDL source code need to be modified to implement the changes and an explanation of the changes necessary. Also, include a pseudo-code description of your test program and a listing of the machine language instructions that implement the pseudo-code. Include the pseudo-code in the form of comments along with your machine language instructions. Turn in your VHDL source code, with all the changes that you made highlighted. Perform a functional simulation of the running program. Turn in simulation output for the first several iterations, highlighting the instructions that increment the count. Also, show the last iteration; this should show both processors halting. Since you will only be doing a functional simulation, it s not necessary to bring all the CPU registers out to external signals, since you can display these using the simulator. Be sure to show all the internal registers for both processors (including state and tick), as well as both address and data buses and both sets of memory control signals. Organize the signals to make it easy to follow what s going on. In particular, put all the signals for processor 0 together, followed by all the signals for processor 1 and list them in the same order. Use hex format for all registers and buses. Make sure that everything is legible. dbus 0 D C word 0 Q 0 1 D C word 1 Q 1 decoder (6-64) 27 D C word 27 Q 27 dbus 63 D C word 63 Q 63 abus en r/w - 2 -

3 Design notes. The processor diagram is shown below. The pid appears as another input to the accumulator (with zeros in bits 15 downto 1). Wnen the processor performs a load pid instruction, the control circuit will select that input to the multiplexor when performing the load. Addr Bus Data Bus IREG LD decode PC LD + IAR LD 0..0 & pid ACC LD compare ALU OP Control Logic (combinational circuit) mem_en mem_rw state tick - 3 -

4 The dual port memory block diagram is shown below. The circuitry at left allows two writes to take place at the same time, so long as they don t access the same word. Similarly, the circuitry at right allows two reads to take place at the same time (in this case, it s ok if they access the same word. Also, of course, you can have a write that is simultaneous with the read, but if they access the same word, the result of the read may be unpredictable. dbus0 dbus1 0 0 D C word 0 Q 0 0 decoder (6-64) 27 decoder (6-64) 27 D C word 27 Q dbus0 dbus D C word 63 Q abus0 abus1 en0 en1 r/w1-4 -

5 The pseudo-code for the test program is shown below. The processor waits in the first while loop until the flag matches its pid value. It then checks if the count has reached the limit or not and halts if it has. Otherwise, it increments the count, then checks again to see if the limit has been reached. If it has, it changes the flag before halting, so that the other processor will halt. loop forever while flag /= pid wait; if count = 20 then halt; count := count + 1; if count = 20 then if pid = 0 then flag := 1; else flag := 0; halt; if pid = 0 then flag := 1; else flag := 0; end loop; The machine language version of the program is shown below while flag /= pid wait; a03e fec -- if count = 20 then halt; 0006 a03f a a count := count + 1; 000b a03f 000c 403f 000d 1fec -- if count = 20 then 000e a03f 000f if pid = 0 then flag := 1 else flag := 0; e e halt if pid = 0 then flag := 1 else flag := 0; 001a 701e 001b c 403e 001d e f 403e goto top; 003e flag (initialized to 0) 003f count (initialized to 0) - 5 -

6 VHDL Source. The changes are highlighted in bold. package commonconstants is constant wordsize: integer := 16; constant adrlength: integer := 16; end package commonconstants; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.commonconstants.all; entity ram2port is port ( reset: in STD_LOGIC; en0, r_w0: in STD_LOGIC; abus0: in STD_LOGIC_VECTOR(adrLength-1 downto 0); dbus0: inout STD_LOGIC_VECTOR(wordSize-1 downto 0); en1, r_w1: in STD_LOGIC; abus1: in STD_LOGIC_VECTOR(adrLength-1 downto 0); dbus1: inout STD_LOGIC_VECTOR(wordSize-1 downto 0)); end ram2port; architecture ramarch of ram2port is constant resadrlength: integer := 6; -- address length restricted within architecture constant memsize: integer := 2**resAdrLength; type ram_typ is array(0 to memsize-1) of STD_LOGIC_VECTOR(wordSize-1 downto 0); signal ram: ram_typ; begin process(reset, en0, r_w0, abus0, dbus0, en1, r_w1, abus1, dbus1) begin if reset = '1' then -- basic instruction check ram(0) <= x"0002"; -- while flag /= pid wait; ram(1) <= x"0001"; ram(2) <= x"a03e"; ram(3) <= x"7005"; ram(4) <= x"6000"; ram(5) <= x"1fec"; -- if count = 20 then halt; ram(6) <= x"a03f"; ram(7) <= x"7009"; ram(8) <= x"600a"; ram(9) <= x"0000"; ram(10) <= x"1001"; -- count := count + 1; ram(11) <= x"a03f"; ram(12) <= x"403f"; ram(13) <= x"1fec"; -- if count = 20 then ram(14) <= x"a03f"; ram(15) <= x"7011"; ram(16) <= x"6019"; ram(17) <= x"0002"; -- if pid = 0 then flag := 1 else flag := 0; ram(18) <= x"7016"; ram(19) <= x"1000"; ram(20) <= x"403e"; ram(21) <= x"6018"; ram(22) <= x"1001"; ram(23) <= x"403e"; ram(24) <= x"0000"; -- halt ram(25) <= x"0002"; -- if pid = 0 then flag := 1 else flag := 0; ram(26) <= x"701e"; ram(27) <= x"1000"; ram(28) <= x"403e"; ram(29) <= x"6020"; - 6 -

7 ram(30) <= x"1001"; ram(31) <= x"403e"; ram(32) <= x"6000"; -- goto top; ram(62) <= x"0000"; -- flag (initialized to 0) ram(63) <= x"0000"; -- count (initialized to 0) else if en0 = '1' and r_w0 = '0' then ram(conv_integer(unsigned(abus0(resadrlength-1 downto 0)))) <= dbus0; if en1 = '1' and r_w1 = '0' then ram(conv_integer(unsigned(abus1(resadrlength-1 downto 0)))) <= dbus1; end process; dbus0 <= ram(conv_integer(unsigned(abus0(resadrlength-1 downto 0)))) when reset = '0' and en0 = '1' and r_w0 = '1' else (dbus0'range => 'Z'); dbus1 <= ram(conv_integer(unsigned(abus1(resadrlength-1 downto 0)))) when reset = '0' and en1 = '1' and r_w1 = '1' else (dbus1'range => 'Z'); end ramarch; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.commonconstants.all; entity cpu is port ( clk, reset, pid : in std_logic; m_en, m_rw : out std_logic; abus : out std_logic_vector(adrlength-1 downto 0); dbus : inout std_logic_vector(wordsize-1 downto 0)); end cpu; architecture cpuarch of cpu is type state_type is ( reset_state, fetch, halt, negate, loadpid, mload, dload, iload, dstore, istore, branch, brzero, brpos, brneg, add ); signal state: state_type; type tick_type is (t0, t1, t2, t3, t4, t5, t6, t7); signal tick: tick_type; signal pc: std_logic_vector(adrlength-1 downto 0); -- program counter signal ireg: std_logic_vector(wordsize-1 downto 0); -- instruction register signal iar: std_logic_vector(adrlength-1 downto 0); -- indirect address register signal acc: std_logic_vector(wordsize-1 downto 0); -- accumulator signal alu: std_logic_vector(wordsize-1 downto 0); -- alu output begin alu <= (not acc) + x"0001" when state = negate else acc + dbus when state = add else (alu'range => '0'); process(clk) -- perform actions that occur on rising clock edges - 7 -

8 function nexttick(tick: tick_type) return tick_type is begin -- return next logical value for tick case tick is when t0 => return t1; when t1 => return t2; when t2 => return t3; when t3 => return t4; when t4 => return t5; when t5 => return t6; when t6 => return t7; when others => return t0; end case; end function nexttick; procedure decode is begin -- Instruction decoding. case ireg(15 downto 12) is when x"0" => if ireg(11 downto 0) = x"000" then state <= halt; elsif ireg(11 downto 0) = x"001" then state <= negate; elsif ireg(11 downto 0) = x"002" then state <= loadpid; when x"1" => state <= mload; when x"2" => state <= dload; when x"3" => state <= iload; when x"4" => state <= dstore; when x"5" => state <= istore; when x"6" => state <= branch; when x"7" => state <= brzero; when x"8" => state <= brpos; when x"9" => state <= brneg; when x"a" => state <= add; when others => state <= halt; end case; end procedure decode; procedure wrapup is begin -- Do this at end of every instruction state <= fetch; tick <= t0; end procedure wrapup; begin if clk'event and clk = '1' then if reset = '1' then state <= reset_state; tick <= t0; pc <= (pc'range => '0'); ireg <= (ireg'range => '0'); acc <= (acc'range => '0'); iar <= (iar'range => '0'); else tick <= nexttick(tick) ; -- advance time by default case state is when reset_state => state <= fetch; tick <= t0; when fetch => if tick = t1 then ireg <= dbus; if tick = t2 then decode; pc <= pc + '1'; tick <= t0; when halt => tick <= t0; -- do nothing when negate => acc <= alu; wrapup; when loadpid => acc <= x"000" & "000" & pid; wrapup; -- load instructions when mload => if ireg(11) = '0' then -- sign extension acc <= x"0" & ireg(11 downto 0); else acc <= x"f" & ireg(11 downto 0); - 8 -

9 wrapup; when dload => if tick = t1 then acc <= dbus; if tick = t2 then wrapup; when iload => if tick = t1 then iar <= dbus; if tick = t4 then acc <= dbus; if tick = t5 then wrapup; -- store instructions when dstore => if tick = t4 then wrapup; when istore => if tick = t1 then iar <= dbus; if tick = t7 then wrapup; -- branch instructions when branch => pc <= x"0" & ireg(11 downto 0); wrapup; when brzero => if acc = x"0000" then pc <= x"0" & ireg(11 downto 0); wrapup; when brpos => if acc(15) = '0' and acc /= x"0000" then pc <= x"0" & ireg(11 downto 0); wrapup; when brneg => if acc(15) = '1' then pc <= x"0" & ireg(11 downto 0); wrapup; -- arithmetic instructions when add => if tick = t1 then acc <= alu; if tick = t2 then wrapup; when others => state <= halt; end case; end process; process(clk) begin -- perform actions that occur on falling clock edges if clk'event and clk ='0' then if reset = '1' then m_en <= '0'; m_rw <= '1'; abus <= (abus'range => '0'); dbus <= (dbus'range => 'Z'); else case state is when fetch => if tick = t0 then m_en <= '1'; abus <= pc; if tick = t2 then m_en <= '0'; abus <= (abus'range=> '0'); when dload => if tick=t0 then m_en<='1'; abus<=x"0" & ireg(11 downto 0); if tick = t2 then m_en <= '0'; abus <= (abus'range=> '0'); when iload => if tick=t0 then m_en<='1'; abus<=x"0" & ireg(11 downto 0); if tick = t2 then m_en <= '0'; abus <= (abus'range=> '0'); if tick = t3 then m_en <= '1'; abus <= iar; - 9 -

10 if tick = t5 then m_en <= '0'; abus <= (abus'range=> '0'); when dstore => if tick=t0 then m_en<='1'; abus<=x"0" & ireg(11 downto 0); if tick = t1 then m_rw <= '0'; dbus <= acc; if tick = t3 then m_rw <= '1'; if tick = t4 then m_en <= '0'; abus <= (abus'range => '0'); dbus <= (dbus'range => 'Z'); when istore => if tick=t0 then m_en<='1'; abus<=x"0" & ireg(11 downto 0); if tick = t2 then m_en <= '0'; abus <= (abus'range=> '0'); if tick = t3 then m_en <= '1'; abus <= iar; if tick = t4 then m_rw <= '0'; dbus <= acc; if tick = t6 then m_rw <= '1'; if tick = t7 then m_en <= '0'; abus <= (abus'range => '0'); dbus <= (dbus'range => 'Z'); when add => if tick=t0 then m_en<='1'; abus<=x"0" & ireg(11 downto 0); if tick = t2 then m_en <= '0'; abus <= (abus'range=> '0'); when others => -- do nothing end case; end process; end cpuarch; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.commonconstants.all; entity top is port( clk, reset: in STD_LOGIC); end top; architecture toparch of top is component ram2port port ( reset: in STD_LOGIC; en0, r_w0: in STD_LOGIC; abus0: in STD_LOGIC_VECTOR(adrLength-1 downto 0); dbus0: inout STD_LOGIC_VECTOR(wordSize-1 downto 0); en1, r_w1: in STD_LOGIC; abus1: in STD_LOGIC_VECTOR(adrLength-1 downto 0); dbus1: inout STD_LOGIC_VECTOR(wordSize-1 downto 0) ); end component; component cpu port ( clk, reset, pid: in STD_LOGIC; m_en, m_rw: out STD_LOGIC; abus: out STD_LOGIC_VECTOR(adrLength-1 downto 0); dbus: inout STD_LOGIC_VECTOR(wordSize-1 downto 0)); end component; signal mem_en0, mem_rw0: STD_LOGIC;

11 signal abus0, dbus0: STD_LOGIC_VECTOR(15 downto 0); signal mem_en1, mem_rw1: STD_LOGIC; signal abus1, dbus1: STD_LOGIC_VECTOR(15 downto 0); begin ramc: ram2port port map(reset, mem_en0, mem_rw0, abus0, dbus0, mem_en1, mem_rw1, abus1, dbus1); cpu0: cpu port map(clk, reset,'0',mem_en0, mem_rw0, abus0, dbus0); cpu1: cpu port map(clk, reset,'1',mem_en1, mem_rw1, abus1, dbus1); end toparch;

12 Simulation results. The simulation results shown below cover the first increment step. The instruction performed by processor 0 that updates the count is highlighted. From the PC for processor 1, we can see that it s staying in the wait loop. direct store at location 12 makes count = 1 cpu1 in wait loop

13 More simulation results. These results show the second increment step. The instruction performed by processor 1 that updates the count is highlighted. From the PC for processor 0, we can see that it s staying in the wait loop. cpu0 in wait loop direct store at location 12 makes count =

14 More simulation results. The simulation results shown below cover the third increment step. The instruction performed by processor 0 that updates the count is highlighted. From the PC for processor 1, we can see that it s staying in the wait loop. direct store at location 12 makes count = 3 cpu1 in wait loop

15 More simulation results. These results show the fourth increment step. The instruction performed by processor 1 that updates the count is highlighted. From the PC for processor 0, we can see that it s staying in the wait loop. cpu0 in wait loop direct store at location 12 makes count =

16 More simulation results. These results show the final increment step. The instruction performed by processor 1 that updates the count is highlighted. From the PC for processor 0, we can see that it s staying in the wait loop, but then exits from the wait loop and halts. cpu0 in wait loop direct store at location 12 makes count = 20 cpu0 exits wait loop, then halts

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