Microprogrammed Control
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- Bennett Crawford
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1 Calcolatori Elettroici e Sistemi Operativi Microprogrammed Microprogrammed Iputs (state) Status sigals (from datapath) NS = δ(s,i) = ((S),I) O = λ(s) Next state Outputs sigals (to datapath) Microprogrammed Microprogrammed Iputs Status sigals (from datapath) (state) Next state Iputs Address geerator Memory Status sigals (from datapath) Sequecer Memory is also called Store CAR: Address ROM PROM RAM PLA CDR: Data Outputs sigals (to datapath) Data for the ext address (optioal) Outputs Microistructio sigals (to datapath)
2 Microprogrammed Microprogrammed Sequecer: geerates the states sequece successio of cosecutive states => coutig break o successio => jump Sigals Memory REG Sigals Memory REG Iputs ad Status Sigals Status Sigals Iputs Microistructios ad jumps sequece Microistructios sequece jumps are coditioed by status bits the sequece start is decided by iputs Calcolatori Elettroici e Sistemi Operativi CTRL Example: microprogrammed Oes couter Sigals microistructio Memory REG +1 jump Status Sigals Jumpig logic jump Status sigals coditio0 coditio1 DEC jumpalways Architecture jcoditio
3 CTRL Datapath Sigals microistructio Memory REG +1 Status sigals jump Architecture coditio0 coditio1 Jump ecodig (jcoditio): o jump coditio0 = coditio1 = jump if first flag = jump if secod flag = 0... jump if first flag = ucoditioal jump Z C N V Status flags DA RW addr_d addr_a 2 write_d addr_a 1 D A 1 file A 2 Z C N V A Op 1 Op 2 Fuctio uit Res AA BA 0 1 B MB B operatio FS 0 1 D MD 4 registers (8 bit) Data output Data iput Oes couter 8 8 X DATAIN oescouter OUTP START R0 <= R0 xor R0 START2 R0 <= R0 +1 INIT WAITD R1 <= DataI DataOut <= R3 OK 0 1 CALC R1 <= DataI 1 DATAIN 0 R3ADD R3 <= R3 + R0 SHIFT R1 <= R1 >> 1 SH2 R1 through adder (op) 0 Z 1 costraits test: oly 1 flag ext state: state+1 or other CALC OK R3RST R3 <= R3 xor R3 R1TEST R2 <= R1 ad R0 WAITD2 R1 <= DataI OUTP: umber of bits equal to '1' received o X DATAIN=1 sigals a ew iput data CALC=1 data fiished: provide result =1 ready to get data OK=1 computatio eded result ready device ready for a ew computatio DATAIN=1 oly whe CALC=0 CALC=1 oly whe DATAIN=0 DATAIN active util device sigals that data are read(=0) CALC active util the ed of computatio (OK=1) R1TEST2 R2 through adder (op) 1 0 Z WAITD4 1 DATAIN 0 WAITD3 0 1 CALC R1 <= DataI
4 Oes couter (µprogrammed) s usage (datapath) R0 <=1 ; R1 <= datai ; R3 <= ONES µistructio datapath CW + output ctrl sigals + jcoditio + dest address Status Word datapath flags + iput ctrl sigals DA AA BA MB FS MD RW OK Jcoditio DEST Datapath Word CTRLOUT V C N Z DATAIN CALC Datapath flags CTRLIN Oes couter: ctrluit (µprogr) library ieee; use ieee.std_logic_1164.all; use ieee.umeric_std.all; file: ctrluit.vhdl -- iterface etity ctrluit is port ( CLK, rst_ : i std_logic; -- cotrol iputs DATAIN : i std_logic; CALC : i std_logic; -- cotrol outputs : out std_logic; OK : out std_logic; DA : out std_logic_vector(1 dowto 0); AA : out std_logic_vector(1 dowto 0); BA : out std_logic_vector(1 dowto 0); MB : out std_logic; FS : out std_logic_vector(4 dowto 0); MD : out std_logic; RW : out std_logic; -- status sigals V,C,N,Z : i std_logic ); ed ctrluit; Oes couter: ctrluit (µprogr) Oes couter: ctrluit (µprogr) file: ctrluit.vhdl architecture struct of ctrluit is compoet micro_rom is port ( address : i std_logic_vector( 5 dowto 0); data : out std_logic_vector(25 dowto 0) ); ed compoet; sigal state, extstate : std_logic_vector( 5 dowto 0); sigal microistructio : std_logic_vector(25 dowto 0); sigal cotrol_word : std_logic_vector(13 dowto 0); sigal cotrol_out : std_logic_vector( 1 dowto 0); sigal jcoditio : std_logic_vector( 3 dowto 0); sigal coditio0 : std_logic_vector( 5 dowto 0); sigal coditio1 : std_logic_vector( 5 dowto 0); sigal jump_dest : std_logic_vector( 5 dowto 0); sigal jumpalways : std_logic; sigal jump : std_logic; sigal status_word : std_logic_vector(5 dowto 0); begi MEM : micro_rom port map (address => state, data => microistructio); state <= (others=>'0') whe rst_='0' extstate whe risig_edge(clk); extstate <= jump_dest whe jump='1' std_logic_vector(usiged(state)+1); status_word <= V & C & N & Z & DATAIN & CALC; cotrol_word <= microistructio(25 dowto 12); cotrol_out <= microistructio(11 dowto 10); jcoditio <= microistructio(9 dowto 6); jump_dest <= microistructio(5 dowto 0); file: ctrluit.vhdl sigal rescod0,rescod1: std_logic_vector(coditio0'left dowto 0);
5 Oes couter: ctrluit (µprogr) Oes couter: ctrluit (µprogr) coditio decoder file: ctrluit.vhdl coditio0(5) <= '1' whe "0001" = jcoditio '0'; coditio0(4) <= '1' whe "0010" = jcoditio '0'; coditio0(3) <= '1' whe "0011" = jcoditio '0'; coditio0(2) <= '1' whe "0100" = jcoditio '0'; coditio0(1) <= '1' whe "0101" = jcoditio '0'; coditio0(0) <= '1' whe "0110" = jcoditio '0'; coditio1(5) <= '1' whe "0111" = jcoditio '0'; coditio1(4) <= '1' whe "1000" = jcoditio '0'; coditio1(3) <= '1' whe "1001" = jcoditio '0'; coditio1(2) <= '1' whe "1010" = jcoditio '0'; coditio1(1) <= '1' whe "1011" = jcoditio '0'; coditio1(0) <= '1' whe "1100" = jcoditio '0'; jumpalways <= '1' whe "1111" = jcoditio '0'; rescod0 <= (ot status_word) ad coditio0; rescod1 <= status_word ad coditio1; jump <= '1' whe jumpalways='1' '1' whe (rescod0 or rescod1) /= "000000" '0'; DA <= cotrol_word(13 dowto 12); AA <= cotrol_word(11 dowto 10); BA <= cotrol_word(9 dowto 8); MB <= cotrol_word(7); FS <= cotrol_word(6 dowto 2); MD <= cotrol_word(1); RW <= cotrol_word(0); <= cotrol_out(1); OK <= cotrol_out(0); ed struct; file: ctrluit.vhdl Oes couter: µprogram Oes couter: ctrluit (µprogr) : R0 <= R0 xor R : R0 <= R : R1 <= DataI ; DataOut <- R3 ; <- 1 ; OK <- 1 ; jump if CALC=1 to (INIT) : R1 <= DataI ; DataOut <- R3 ; <- 1 ; jump if DATAIN=0 to (WAITD) : R3 <= R3 xor R : R2 <= R1 ad R : R2 through Arithmetic Uit ; jump if Z=1 to (SHIFT) : R3 <= R3 + R : R1 <= R1 >> : R1 through Arithmetic Uit ; jump if Z=0 to (R1TEST) : R1 <= DataI ; DataOut <- R3 ; <- 1 ; jump if DATAIN=1 to (R1TEST) : op ; <- 1 ; jump if CALC=1 to (INIT) : R1 <= DataI ; DataOut <- R3 ; <- 1 ; jump to (WAITD2) file: micro_rom.vhdl library ieee; use ieee.std_logic_1164.all; etity micro_rom is port ( address : i std_logic_vector( 5 dowto 0); data : out std_logic_vector(25 dowto 0) ); ed micro_rom; architecture behav of micro_rom is begi data <= B"00_00_00_0_01100_0_1_00_0000_000000" whe address="000000" B"00_00_00_0_00001_0_1_00_0000_000000" whe address="000001" B"01_00_11_0_00000_1_1_11_1100_000010" whe address="000010" B"01_00_11_0_00000_1_1_10_0101_000011" whe address="000011" B"11_11_11_0_01100_0_1_00_0000_000000" whe address="000100" B"10_01_00_0_01000_0_1_00_0000_000000" whe address="000101" B"00_10_00_0_00000_0_0_00_1010_001000" whe address="000110" B"11_11_00_0_00010_0_1_00_0000_000000" whe address="000111" B"01_00_01_0_10100_0_1_00_0000_000000" whe address="001000" B"00_01_00_0_00000_0_0_00_0100_000101" whe address="001001" B"01_00_11_0_00000_1_1_10_1011_000101" whe address="001010" B"00_00_00_0_00000_0_0_10_1100_000010" whe address="001011" B"01_00_11_0_00000_1_1_10_1111_001010" whe address="001100" (others=>'-'); ed behav;
6 Oes couter: testbech (µprogr) Oes couter: testbech (µprogr) library ieee; use ieee.std_logic_1164.all; use ieee.umeric_std.all; use STD.textio.all; -- iterface etity TB is ed TB; architecture behav of TB is costat CLK_SEMIPERIOD0: time := 25 s; costat CLK_SEMIPERIOD1: time := 15 s; costat CLK_PERIOD : time := CLK_SEMIPERIOD0+CLK_SEMIPERIOD1; costat RESET_TIME : time := 3*CLK_PERIOD + 9 s; sigal CLK, rst_ : std_logic; sigal cout : std_logic_vector(23 dowto 0) := (others=> '0'); sigal it_cout : iteger := 0; sigal start : iteger := 0; sigal doe : iteger := 0; sigal couter_data : std_logic_vector(23 dowto 0) := (others=> '0'); sigal it_couter_data : iteger := 0; type TBstatetype is (WAIT1, SEND, WAIT0, WAITOK); sigal TBstate : TBstatetype; sigal X : std_logic_vector(7 dowto 0); sigal OUTP : std_logic_vector(7 dowto 0); sigal DATAIN : std_logic; sigal CALC : std_logic; sigal : std_logic; sigal OK : std_logic; Oes couter: testbech (µprogr) Oes couter: testbech (µprogr) compoet oescouter is port ( CLK, rst_ : i std_logic; X : i std_logic_vector(7 dowto 0); OUTP : out std_logic_vector(7 dowto 0); DATAIN : i std_logic; CALC : i std_logic; : out std_logic; OK : out std_logic ); ed compoet; begi DUT : oescouter port map (CLK, rst_, X => X, OUTP => OUTP, DATAIN => DATAIN, CALC => CALC, =>, OK => OK); start_process: process begi rst_ <= '1'; wait for 1 s; rst_ <= '0'; wait for RESET_TIME; rst_ <= '1'; start <= 1; wait; ed process start_process;
7 Oes couter: testbech (µprogr) Oes couter: testbech (µprogr) -- CLOCK geerator clk_process: process begi if CLK = '0' the CLK <= '1'; wait for CLK_SEMIPERIOD1; CLK <= '0'; wait for CLK_SEMIPERIOD0; cout <= std_logic_vector(usiged(cout) + 1); it_cout <= it_cout + 1; if doe = 1 the wait; ed process clk_process; -- datafile: data.txt read_file_process: process(clk) file ifile : TEXT ope READ_MODE is "data.txt"; variable iputlie : LINE; variable i_x : bit_vector(x'rage); variable i_datain : bit; variable i_calc : bit; begi if (clk='0') the if (start = 1) the case TBstate is whe WAIT1 => DATAIN <= '0'; CALC <= '0'; if /= '1' the TBstate <= WAIT1; TBstate <= SEND; Oes couter: testbech (µprogr) Oes couter: testbech (µprogr) whe SEND => -- load data ad set sigals if ot edfile(ifile) the readlie(ifile, iputlie); read(iputlie, i_x); readlie(ifile, iputlie); read(iputlie, i_datain); readlie(ifile, iputlie); read(iputlie, i_calc); readlie(ifile, iputlie); if i_calc='1' ad i_datain='1' the i_datain := '0'; X <= to_ux01(i_x); DATAIN <= to_ux01(i_datain); CALC <= to_ux01(i_calc); couter_data <= std_logic_vector(usiged(couter_data) + 1); it_couter_data <= it_couter_data + 1; if i_calc='1' the TBstate <= WAITOK; elsif i_datain='1' the TBstate <= WAIT0; TBstate <= WAIT1; TBstate <= WAIT1; doe <= 1;
8 Oes couter: testbech (µprogr) Microprogrammig whe WAIT0 => if = '0' the TBstate <= WAIT1; TBstate <= WAIT0; whe WAITOK => DATAIN <= '0'; CALC <= '1'; if OK='1' the TBstate <= WAIT1; TBstate <= WAITOK; ed case; ed process read_file_process; Horizotal microprogram each cotrol sigal is a bit i microistructio o decodig larger words ( larger memories) Vertical microprogram cotrol sigals are ecoded i shorter formats multiple microistructio formats e.g., oe format for data operatios, oe format for jumps eed decodig smaller memory Microprogrammig Simplify developmet Decouples HW ad algorithm desig desig becomes SW developmet Requires a fast cotrol memory Reduces flexibility ad efficiecy Datapath is ot applicatio specific Tradeoff: potetial efficiecy vs HW resources
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